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https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Cleanup Timer & Clock Multiplier Code
This commit is contained in:
Wayne Warthen
@@ -2,4 +2,4 @@
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#DEFINE RMN 9
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#DEFINE RUP 2
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#DEFINE RTP 0
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#DEFINE BIOSVER "2.9.2-pre.20"
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#DEFINE BIOSVER "2.9.2-pre.21"
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@@ -981,22 +981,69 @@ HB_CPU1:
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LD A,L
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LD (HB_CPUTYPE),A
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;
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#IF (DSRTCENABLE)
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CALL DSRTC_PREINIT
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z180)
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;
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; AT BOOT, Z180 PHI IS OSC / 2
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LD C,(CPUOSC / 2) / 1000000
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LD DE,(CPUOSC / 2) / 1000
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;
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#IF (Z180_CLKDIV >= 1)
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LD A,(HB_CPUTYPE) ; GET CPU TYPE
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CP 2 ; Z8S180 REV K OR BETTER?
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JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
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; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
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LD A,$80
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OUT0 (Z180_CCR),A
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; REFLECT SPEED CHANGE
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LD C,CPUOSC / 1000000
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LD DE,CPUOSC / 1000
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#ENDIF
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#IF (Z180_CLKDIV >= 2)
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LD A,(HB_CPUTYPE) ; GET CPU TYPE
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CP 3 ; Z8S180 REV N OR BETTER?
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JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
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; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
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LD A,$80
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OUT0 (Z180_CMR),A
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; REFLECT SPEED CHANGE
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LD C,(CPUOSC * 2) / 1000000
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LD DE,(CPUOSC * 2) / 1000
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#ENDIF
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;
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HB_CPU2:
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; SAVE CPU SPEED IN CONFIG BLOCK
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LD A,C
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LD (CB_CPUMHZ),A
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LD (CB_CPUKHZ),DE
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;
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#ENDIF
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;
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DIAG(%00011111)
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;
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; PERFORM DYNAMIC CPU SPEED DERIVATION
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;
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CALL HB_CPUSPD ; CPU SPEED DETECTION
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;
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CALL DELAY_INIT ; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS
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;
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#IF (CPUFAM == CPU_Z180)
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;
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; SET FINAL DESIRED WAIT STATES
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LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
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OUT0 (Z180_DCNTL),A
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;
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#ENDIF
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;
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#IF (KIOENABLE)
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LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN
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OUT (KIOBASE+$0E),A ; DO IT
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;CALL DLY64 ; WAIT A BIT FOR RESET TO COMPLETE
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#ENDIF
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;
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; SETUP INTERRUPT VECTORS, AS APPROPRIATE
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;
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;#IF (INTMODE == 1)
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; ; OVERLAY $0038 WITH JP INT_IM1
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; LD A,$C3 ; JP INSTRUCTION
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; LD ($0038),A ; INSTALL IT
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; LD HL,INT_IM1 ; DESTINATION ADDRESS
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; LD ($0039),HL ; INSTALL IT
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;#ENDIF
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;
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#IF (INTMODE == 2)
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; SETUP Z80 IVT AND INT MODE 2
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LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS
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@@ -1010,7 +1057,7 @@ HB_CPU1:
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IM 2 ; SWITCH TO INT MODE 2
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#ENDIF
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;
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#IF (PLATFORM == PLT_SBC)
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;
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#IF (HTIMENABLE) ; SIMH TIMER
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@@ -1142,7 +1189,6 @@ HB_CPU1:
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;
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#ENDIF
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;
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;
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#IF (PLATFORM == PLT_RCZ80)
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;
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; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO
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@@ -1245,11 +1291,10 @@ HB_CPU1:
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LD (IVT(INT_TIM0)),HL ; Z180 TIMER 0
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; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0
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; LD HL,CPUOSC/TICKSPERSEC/20-1 ; 50HZ = 18432000 / 50 / 20
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LD HL,(CPUKHZ) ; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
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DEC HL ; RELOAD OCCURS *AFTER* ZERO
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LD HL,(CB_CPUKHZ) ; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
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OUT0 (Z180_TMDR0L),L ; INITIALIZE TIMER 0 DATA REGISTER
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OUT0 (Z180_TMDR0H),H
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DEC HL ; RELOAD OCCURS *AFTER* ZERO
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OUT0 (Z180_RLDR0L),L ; INITIALIZE TIMER 0 RELOAD REGISTER
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OUT0 (Z180_RLDR0H),H
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LD A,%00010001 ; ENABLE TIMER0 INT AND DOWN COUNTING
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@@ -1259,67 +1304,6 @@ HB_CPU1:
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;
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#ENDIF
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;
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#IF (DSRTCENABLE)
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CALL DSRTC_PREINIT
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z180)
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;
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; AT BOOT, Z180 PHI IS OSC / 2
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LD C,(CPUOSC / 2) / 1000000
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LD DE,(CPUOSC / 2) / 1000
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;
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#IF (Z180_CLKDIV == 1)
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LD A,(HB_CPUTYPE) ; GET CPU TYPE
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CP 2 ; Z8S180 REV K OR BETTER?
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JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
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; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
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LD A,$80
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OUT0 (Z180_CCR),A
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; REFLECT SPEED CHANGE
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LD C,CPUOSC / 1000000
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LD DE,CPUOSC / 1000
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#ELSE
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;
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#IF (Z180_CLKDIV == 2)
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LD A,(HB_CPUTYPE) ; GET CPU TYPE
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CP 3 ; Z8S180 REV N OR BETTER?
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JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
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; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
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LD A,$80
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OUT0 (Z180_CMR),A ; MUST SET CMR BEFORE CCR
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OUT0 (Z180_CCR),A
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; REFLECT SPEED CHANGE
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LD C,(CPUOSC * 2) / 1000000
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LD DE,(CPUOSC * 2) / 1000
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#ENDIF
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;
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#ENDIF
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;
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HB_CPU2:
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; SAVE CPU SPEED IN CONFIG BLOCK
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LD A,C
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LD (CB_CPUMHZ),A
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LD (CB_CPUKHZ),DE
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;
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#ENDIF
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;
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; PERFORM DYNAMIC CPU SPEED DERIVATION
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;
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CALL HB_CPUSPD ; CPU SPEED DETECTION
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;
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#IF (CPUFAM == CPU_Z180)
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;
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; SET DESIRED WAIT STATES
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LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
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OUT0 (Z180_DCNTL),A
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;
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#ENDIF
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;
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CALL DELAY_INIT ; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS
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;
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DIAG(%00011111)
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;
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; INITIALIZE HEAP STORAGE
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;
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; INITIALIZE POINTERS
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@@ -2,4 +2,4 @@
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#DEFINE RMN 9
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#DEFINE RUP 2
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#DEFINE RTP 0
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#DEFINE BIOSVER "2.9.2-pre.20"
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#DEFINE BIOSVER "2.9.2-pre.21"
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