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b1ackmai1er
2019-08-04 20:22:12 +08:00
parent d22d83f2c8
commit 65bce62b26
2 changed files with 1 additions and 12 deletions
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5
Source/HBIOS/plt_sbc.inc
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@@ -20,7 +20,4 @@ MPGENA .EQU SBC_BASE + $1C ; PAGING ENABLE REGISTER - BIT 0 = 1 (WRITE ONLY)
RTC .EQU SBC_BASE + $10 ; ADDRESS OF RTC LATCH AND INPUT PORT
PPIBASE .EQU SBC_BASE + $00 ; PPI 82C55 I/O IS DECODED TO PORT 60-67
PIOZBASE .EQU $88 ; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
PIO4BASE .EQU $90 ; ECB-4PIO DEFAULT PIO DEFAULT
;
;
FIFO_BASE .EQU $0C ; ECB USB-FIFO DEFAULT PORT
PIO4BASE .EQU $90 ; ECB-4PIO DEFAULT PIO DEFAULT

8
Source/HBIOS/std.asm
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@@ -269,14 +269,6 @@ IVT_PIO3 .EQU 24
IVT_SER2 .EQU 26
IVT_SER3 .EQU 28
;
;
; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE,
; SET FORCECON TO 2 IN YOUR CUSTOM CONFIGURATION FILE i.e. "FORCECON: .SET 2"
;
FORCECON .EQU 0 ; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
;
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
;
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))