diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index 64eb7ea4..e7e06a72 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Architecture.pdf b/Doc/RomWBW Architecture.pdf index 4260e3e2..f8391b5c 100644 Binary files a/Doc/RomWBW Architecture.pdf and b/Doc/RomWBW Architecture.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index 05aa5486..173e6e55 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Getting Started.pdf b/Doc/RomWBW Getting Started.pdf index 607b60df..3af3d3ac 100644 Binary files a/Doc/RomWBW Getting Started.pdf and b/Doc/RomWBW Getting Started.pdf differ diff --git a/Source/Doc/Architecture.md b/Source/Doc/Architecture.md index 9cedae91..674d6a8e 100644 --- a/Source/Doc/Architecture.md +++ b/Source/Doc/Architecture.md @@ -701,7 +701,7 @@ Write Block Count sectors to buffer address starting at current target sector. Current sector must be established by prior seek function; however, multiple read/write/verify function calls can be made after a seek function. Current sector is incremented after each sector successfully -written. On error, current sector is sector is sector where error occurred. +written. On error, current sector is sector where error occurred. Blocks written indicates number of sectors successfully written. Caller must ensure: 1) buffer address is large enough to contain data for diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index 2e3b1adb..0584d066 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -36,6 +36,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index a29e0331..f6eb252d 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -35,6 +35,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR WDOGIO .EQU $6F ; WATCHDOG REGISTER ADR ; diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 95680f9c..2ef0c8b4 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -35,6 +35,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index d2e61d32..890e8240 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -31,6 +31,8 @@ RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) MEMMGR .EQU MM_Z180 ; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index 6db938cd..e5fbe20c 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -31,6 +31,8 @@ RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) MEMMGR .EQU MM_N8 ; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index f133cdb6..4c9d8edb 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -36,6 +36,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm index 5d17cfdb..913b67fc 100644 --- a/Source/HBIOS/cfg_rcz280.asm +++ b/Source/HBIOS/cfg_rcz280.asm @@ -35,6 +35,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z280_MEMWAIT .EQU 0 ; Z280: MEMORY WAIT STATES (0-3) Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3) diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 24c03d87..a6e70e90 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -35,6 +35,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index ce5a46c8..034a004d 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -32,6 +32,8 @@ MEMMGR .EQU MM_SBC ; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; @@ -202,5 +204,3 @@ AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER AY_CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4 AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180] SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -FFENABLE .EQU TRUE ; ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 8ef910d8..4cac4122 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -31,6 +31,8 @@ RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) MEMMGR .EQU MM_Z180 ; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index 6fdf350e..793a01b1 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -32,6 +32,8 @@ MEMMGR .EQU MM_SBC ; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index daf6eb27..7d08114f 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -35,6 +35,8 @@ MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; +FFENABLE .EQU FALSE ; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER +; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; diff --git a/Source/HBIOS/flashfs.asm b/Source/HBIOS/flashfs.asm index 2d70111c..baf6af34 100644 --- a/Source/HBIOS/flashfs.asm +++ b/Source/HBIOS/flashfs.asm @@ -148,4 +148,4 @@ FF_CHIP(0C2A4H,"MX29F040$ ",512,ST_NORMAL) ; FF_T_CNT .EQU ($-FF_TABLE) / 17 FF_UNKNOWN .DB "UNKNOWN$" -FF_STACK: .DW 0 \ No newline at end of file +FF_STACK: .DW 0