Z280 UART Flow Control

- Implement RTS flow control on Z280 UART using C/T 2 output pin.  Must be supported on PCB and wired properly at serial adapter.

Source/HBIOS/Config/RCZ280_nat.asm

@@ -49,5 +49,3 @@ IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-;
-Z2UOSCEXT	.SET	TRUE		; Z2U: USE EXTERNAL OSCILLATOR

Source/HBIOS/Config/RCZ280_nat_zz.asm

@@ -28,3 +28,5 @@
 ;
 RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 RAMBIAS		.SET	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z2U0HFC		.SET	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL

Source/HBIOS/cfg_master.asm

@@ -141,6 +141,7 @@ Z2UOSC		.EQU	1843200		; Z2U: OSC FREQUENCY IN MHZ
 Z2UOSCEXT	.EQU	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
 Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
 Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
+Z2U0HFC		.EQU	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT

Source/HBIOS/cfg_rcz280.asm

@@ -114,6 +114,7 @@ Z2UOSC		.EQU	1843200		; Z2U: OSC FREQUENCY IN MHZ
 Z2UOSCEXT	.EQU	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
 Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
 Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
+Z2U0HFC		.EQU	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
 ;
 ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT

Source/HBIOS/hbios.asm

@@ -425,7 +425,6 @@ HBX_ROM:
 	INC	A			;
 	OUT	(MPGSEL_1),A		; BANK_1: 16K - 32K
   #IF (CPUFAM == CPU_Z280)
-	;.DB	$ED,$65			; PCACHE
 	PCACHE
   #ENDIF
 	RET				; DONE
@@ -601,7 +600,6 @@ HBX_BNKCALL:
 HBX_BNKCALL2:
 	HB_EI				; INTS ARE OK
 	LD	(HBX_BNKCALL_GO+1),IX	; SETUP DEST ADR
-	;.DB	$ED,$65			; PCACHE (CRITICAL!!!)
 	PCACHE				; CRITICAL!!!
 HBX_BNKCALL_GO:
 	JP	$FFFF			; DO THE REAL WORK AND RETURN
@@ -1026,7 +1024,7 @@ Z280_BOOTERR	.TEXT	"\r\n\r\n*** Application mode boot not supported under Z280 n
 	; ENABLE MMU (SYSTEM AND USER TRANSLATION)
 	LD	C,Z280_MMUMCR		; MMU MASTER CONTROL REGISTER
 	LD	HL,$BBFF		; ENABLE USER & SYSTEM TRANSLATE
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 ;
 	; DISABLE MEMORY REFRESH CYCLES
 	LD	A,$08			; DISABLED
@@ -1630,9 +1628,9 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 	OUT	(Z280_CT0_CFG),A	; SET C/T 0
 	LD	HL,Z280_TC		; TIME CONSTANT & COUNTER
 	LD	C,Z280_CT0_TC		; SET C/T 0
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	LD	C,Z280_CT0_CT		; SET C/T 0
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	LD	A,%11100000		; CMD: EN, GT
 	OUT	(Z280_CT0_CMDST),A	; SET C/T 0
 ;
@@ -4180,22 +4178,22 @@ Z280_BNKSEL2:
 Z280_BNKSEL3:
 	; PROGRAM 8 PDR VALUES
 	; LOOP UNROLLED FOR SPEED
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
-	.DB	$ED,$BF			; OUTW (C),HL
-	.DB	$ED,$6D			; ADD HL, A ; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
+	OUTW	(C),HL			; WRITE VALUE
+	ADD	HL,A			; BUMP VALUE
 	;DJNZ	Z280_BNKSEL3		; DO ALL PDRS
 ;
 	; RESTORE I/O PAGE
@@ -4246,11 +4244,11 @@ Z280_BNKCPY:
 	CALL	Z2DMAADR		; SETUP SOURCE ADR REGS
 ;
 	POP	HL			; COUNT TO HL
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	INC	C			; BUMP TO TDR
 ;
 	LD	HL,$8000		; ENABLE DMA0 TO RUN!
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 ;
 	; WAIT FOR XFER TO COMPLETE
 Z2DMALOOP:
@@ -4314,12 +4312,12 @@ Z2DMAADR2:
 	LD	H,A			; HL=1111 AAAA AAAA AAAA
 ;
 	; SET ADR LO REG
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	INC	C			; BUMP TO ADR HI REG
 ;
 	; SET ADR HI REG
 	POP	HL			; RECOVER THE HI VAL
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	INC	C			; BUMP TO NEXT REG
 ;	
 	RET

Source/HBIOS/z2u.asm

@@ -56,8 +56,13 @@
 ; UNLESS FULL BLOWN INTERRUPT MODE 3 W/ NATIVE MEMORY MANAGEMENT
 ; IS BEING USED.
 ;
-;Z2U_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
-Z2U_BUFSZ	.EQU	128		; RECEIVE RING BUFFER SIZE
+;
+;
+#IF (Z2U0HFC)
+Z2U_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
+#ELSE
+Z2U_BUFSZ	.EQU	144		; RECEIVE RING BUFFER SIZE
+#ENDIF
 ;
 Z2U_NONE	.EQU	0		; NOT PRESENT
 Z2U_PRESENT	.EQU	1		; PRESENT
@@ -193,9 +198,15 @@ Z2U_INTRCV1:
 	JR	Z,Z2U_INTRCV4		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
 	LD	(HL),A			; AND SAVE IT
-	;CP	Z2U_BUFSZ / 2		; BUFFER GETTING FULL?
-	;JR	NZ,Z2U_INTRCV2		; IF NOT, BYPASS CLEARING RTS
-	; THIS IS WHERE WE SHOULD DEASSERT RTS, BUT THE Z2U HAS NONE
+#IF (Z2U0HFC)
+	CP	Z2U_BUFSZ / 2		; BUFFER GETTING FULL?
+	JR	NZ,Z2U_INTRCV2		; IF NOT, BYPASS CLEARING RTS
+	PUSH	HL			; SAVE HL
+	LD	HL,0			; TC VALUE 0 CAUSES HIGH OUTPUT (RTS DEASSERTED)
+	LD	C,Z280_CT2_TC		; SET C/T 2
+	OUTW	(C),HL
+	POP	HL			; RESTORE HL
+#ENDIF
 Z2U_INTRCV2:
 	INC	HL			; HL NOW HAS ADR OF HEAD PTR
 	PUSH	HL			; SAVE ADR OF HEAD PTR
@@ -285,7 +296,27 @@ Z2U_IN:
 	LD	A,(HL)			; GET COUNT
 	DEC	A			; DECREMENT COUNT
 	LD	(HL),A			; SAVE UPDATED COUNT
-	; THIS IS WHERE WE SHOULD ASSERT RTS, BUT THE Z2U HAS NONE
+;
+#IF (Z2U0HFC)
+	CP	Z2U_BUFSZ / 4		; BUFFER LOW THRESHOLD
+	JR	NZ,Z2U_IN1		; IF NOT, BYPASS SETTING RTS
+;
+	; ASSERT RTS
+	PUSH	HL
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
+	PUSH	HL			; SAVE IT
+	LD	L,$FE			; NEW COUNTER/TIMER I/O PAGE
+	LDCTL	(C),HL
+	LD	HL,1			; TC VALUE ~0 CAUSES LOW OUTPUT (RTS ASSERTED)
+	LD	C,Z280_CT2_TC		; SET C/T 2
+	OUTW	(C),HL
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	POP	HL			; RECOVER ORIGINAL I/O PAGE
+	LDCTL	(C),HL
+	POP	HL
+#ENDIF
+;
 Z2U_IN1:
 	INC	HL			; HL := ADR OF TAIL PTR
 	INC	HL			; "
@@ -497,7 +528,7 @@ Z2U_INITDEV2:
 	LD	H,0			; H MUST BE ZERO
 	LD	DE,1			; RATIO, SO NO CONSTANT
 	CALL	DECODE			; DECODE INTO DE:HL
-	JR	NZ,Z2U_INITFAIL		; HANDLE FAILURE
+	JP	NZ,Z2U_INITFAIL		; HANDLE FAILURE
 ;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	DE,(Z2U_NEWCFG)		; GET NEW CONFIG BACK
@@ -525,9 +556,9 @@ Z2U_INITDEV8:
 #ENDIF
 	OUT	(Z280_CT1_CFG),A	; SET C/T 1
 	LD	C,Z280_CT1_TC		; SET C/T 1 FROM HL
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	LD	C,Z280_CT1_CT		; SET C/T 1 FROM HL
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	LD	A,%11100000		; CMD: EN, GT, TG
 	OUT	(Z280_CT1_CMDST),A	; SET C/T 1
 ;
@@ -548,8 +579,18 @@ Z2U_INITDEV9:
 	LD	A,%10000000		; ENABLE, NO RCV INTS
 #ENDIF
 	OUT	(Z280_UARTRCTL),A	; SET RCV CTL REGISTER
-;	
-	; RESTORE I/O PAGE TO $00
+;
+#IF (Z2U0HFC)
+	; SETUP C/T 2 FOR FLOW CONTROL
+	LD	A,%00001000		; CONFIG: TIMER
+	OUT	(Z280_CT2_CFG),A	; SET C/T 2 CONFIG
+	LD	HL,1			; TC VALUE ~0 CAUSES LOW OUTPUT (RTS ASSERTED)
+	LD	C,Z280_CT2_TC		; SET C/T 2
+	OUTW	(C),HL
+	LD	A,%00000000		; CMD: EN, GT
+	OUT	(Z280_CT2_CMDST),A	; SET C/T 2
+#ENDIF
+;
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	LDCTL	(C),HL

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.50"
+#DEFINE BIOSVER	"3.1.1-pre.51"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.50"
+	db	"3.1.1-pre.51"
 	endm