Add Support for MBC FDC in FDU

- The FDU support is not yet tested!
- The MBC FDU is not yet supported in HBIOS!

Doc/ChangeLog.txt

@@ -45,6 +45,7 @@ Version 3.1.1
 - WBW: Added Phil Summers' ROM Updater into ROM Loader
 - AJL: Added ramtest app (requires SBC and MBC for now)
 - L?N: Provided SCOPY, XSUB01, and EX applications
+- WBW: Added support for MBC FDC to FDU application
 
 Version 3.1
 -----------

Source/Apps/FDU/fdu.asm

@@ -48,6 +48,7 @@
 ;   2020-04-29: v5.5	ADDED SUPPORT FOR ETCHED PIXELS FDC
 ;   2020-12-12: v5.6	UPDATED SMALLZ80 TO NEW I/O ADDRESSES
 ;   2021-03-24: v5.7    ADDED SOME SINGLE-SIDED FORMATS
+;   2021-07-26: v5.8	ADDED SUPPORT MBC FDC
 ;			
 ;_______________________________________________________________________________
 ;
@@ -83,6 +84,7 @@ FDC_RCWDC	.EQU		7
 FDC_SMZ80	.EQU		8
 FDC_DYNO	.EQU		9
 FDC_EPFDC	.EQU		10
+FDC_MBC		.EQU		11
 ;
 ; FDC MODE
 ;
@@ -217,7 +219,7 @@ INIT5:
 	XOR	A
 	RET
 		
-STR_BANNER	.DB	"Floppy Disk Utility (FDU) v5.7, 24-Mar-2021$"
+STR_BANNER	.DB	"Floppy Disk Utility (FDU) v5.8, 26-Jul-2021$"
 STR_BANNER2	.DB	"Copyright (C) 2021, Wayne Warthen, GNU GPL v3","$"
 STR_HBIOS	.DB	" [HBIOS]$"
 STR_UBIOS	.DB	" [UBIOS]$"
@@ -289,6 +291,7 @@ FDCTBL:	;	LABEL		CONFIG DATA
 	.DW	STR_SMZ80,	CFG_SMZ80
 	.DW	STR_DYNO,	CFG_DYNO
 	.DW	STR_EPFDC,	CFG_EPFDC
+	.DW	STR_MBC,	CFG_MBC
 FDCCNT	.EQU	($-FDCTBL)/4	; FD CONTROLLER COUNT
 ;
 ; FDC LABEL STRINGS
@@ -304,6 +307,7 @@ STR_RCWDC	.TEXT	"RC-WDC$"
 STR_SMZ80	.TEXT	"SMZ80$"
 STR_DYNO	.TEXT	"DYNO$"
 STR_EPFDC	.TEXT	"EPFDC$"
+STR_MBC		.TEXT	"MBC$"
 ;
 ; FDC CONFIGURATION BLOCKS
 ;
@@ -436,6 +440,17 @@ CFG_EPFDC:
 	.DB	0FFH	; PSEUDO DMA DATA PORT
 	.DB	_PCAT	; MODE=
 ;
+CFG_MBC:
+	.DB	030H	; FDC MAIN STATUS REGISTER
+	.DB	031H	; FDC DATA PORT
+	.DB	0FFH	; DATA INPUT REGISTER
+	.DB	036H	; DIGITAL OUTPUT REGISTER (WHEN WRITTEN)
+	.DB	035H	; CONFIGURATION CONTROL REGISTER
+	.DB	036H	; DACK (WHEN READ)
+	.DB	037H	; TERMINAL COUNT (W/ DACK)
+	.DB	0FFH	; NOT USED BY ZETA SBC V2
+	.DB	_PCAT	; MODE=
+;
 FDCID	.DB	0			; FDC IDENTIFIER (0 INDEXED)
 FDCBM	.DB	0			; FDC ID BITMAP
 FDCLBL	.DW	0			; POINTER TO ACTIVE FDC LABEL STRING
@@ -455,6 +470,7 @@ FSS_MENU:
 	.TEXT	"  (I) SmallZ80 Expansion\r\n"
 	.TEXT	"  (J) Dyno-Card FDC, D1030\r\n"
 	.TEXT	"  (K) RC2014 EPFDC\r\n"
+	.TEXT	"  (L) Multi-Board Computer FDC\r\n"
 	.TEXT	"  (X) Exit\r\n"
 	.TEXT	"=== OPTION ===> $\r\n"
 ;	
@@ -1544,6 +1560,7 @@ MD_MAP:
 		.DB	%00000001	; SMZ80	POLL
 		.DB	%00000001	; DYNO	POLL
 		.DB	%00000001	; EPFDC	POLL
+		.DB	%00000001	; MBC	POLL
 ;
 ; MEDIA DESCRIPTION BLOCK
 ;
@@ -2004,7 +2021,7 @@ FM_DRAW0B:	; ZETA, DIO3
 	LD	A,(FST_DOR)
 	AND	00000010B
 	JR	FM_DRAW1
-FM_DRAW0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+FM_DRAW0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	LD	A,(FST_DOR)
 	AND	11110000B
 	JR	FM_DRAW1
@@ -2157,7 +2174,7 @@ FM_MOTOR0B:	; ZETA, DIO3
 	LD	A,(FST_DOR)
 	AND	00000010B
 	JR	FM_MOTOR1
-FM_MOTOR0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+FM_MOTOR0C:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	LD	A,(FST_DOR)
 	AND	11110000B
 	JR	FM_MOTOR1
@@ -2896,7 +2913,7 @@ FC_INIT1:	; DIO
 FC_INIT2:	; ZETA, DIO3
 	LD	A,(FCD_DORB)
 	JR	FC_INIT5
-FC_INIT3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+FC_INIT3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	LD	A,(FCD_DORC)
 	JR	FC_INIT5
 FC_INIT4:	; WDSMC
@@ -2940,7 +2957,7 @@ FC_RESETFDC1:	; ZETA, DIO3, RCSMC
 	POP	AF
 	OUT	(C),A
 	JR	FC_RESETFDC3
-FC_RESETFDC2:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+FC_RESETFDC2:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	LD	A,0
 	OUT	(C),A
 	LD	A,(FST_DOR)
@@ -2967,7 +2984,7 @@ FC_PULSETC:
 	;RES	0,A
 	;OUT	(C),A
 	;JR	FC_PULSETC2
-;FC_PULSETC1:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+;FC_PULSETC1:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	;LD	C,(IY+CFG_TC)
 	;IN	A,(C)
 	;JR	FC_PULSETC2
@@ -2999,7 +3016,7 @@ FC_MOTORON2:	; ZETA, DIO3
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	SET	1,(HL)
 	JR	FC_MOTORON5
-FC_MOTORON3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+FC_MOTORON3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	LD	A,(HL)			; START WITH CURRENT DOR
 	AND	11111100B		; GET RID OF ANY ACTIVE DS BITS
@@ -3063,7 +3080,7 @@ FC_MOTOROFF2:	; ZETA, DIO3
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	RES	1,(HL)
 	JR	FC_MOTOROFF5
-FC_MOTOROFF3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC
+FC_MOTOROFF3:	; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO, EPFDC, MBC
 	LD	HL,FST_DOR		; POINT TO FDC_DOR
 	LD	A,DORC_INIT
 	LD	(HL),A
@@ -3933,7 +3950,7 @@ DORB_BR500	.EQU	10100000B	; 500KBPS
 ;
 DORB_INIT	.EQU	DORB_BR250
 ;
-; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO/EPFDC ***
+; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO/EPFDC/MBC ***
 ;
 DORC_INIT	.EQU	00001100B	; SOFT RESET INACTIVE, DMA ENABLED
 ;

Source/Apps/FDU/fdu.txt

@@ -74,10 +74,10 @@ supported:
  - Zeta 2
  - N8
  - Mark IV
- - RC2014 w/ SMC
- - RC2014 w/ WDC
+ - RC2014
  - SmallZ80
  - Dyno
+ - MBC
 
 You must be using either a RomWBW or UBA based OS version.
 
@@ -91,6 +91,9 @@ You must have one of the following floppy disk controllers:
  - N8 SBC onboard FDC
  - RC2014 Scott Baker SMC-based Floppy Module
  - RC2014 Scott Baker WDC-based Floppy Module
+ - SmallZ80 FDC
+ - Dyno FDC
+ - MBC FDC
  
 Finally, you will need a floppy drive connected via an 
 appropriate cable:
@@ -152,12 +155,18 @@ The RC2014 Scott Baker WDC-based floppy module should be jumpered
 for I/O base address 0x50 (SV1: 11-12), JP1 (/DACK): 1-2,
 JP2 (TC): 2-3.
 
+The RC2014 FDC by Alan Cox (Etched Pixels) needs to be strapped
+for base I/O address 0x48.
+
 SmallZ80 does not have any relevant jumper settings.  The 
 hardwired I/O ranges are assumed in the code.
 
 Dyno does not have any relevant jumper settings.  The 
 hardwired I/O ranges are assumed in the code.
 
+The MBC FDC is expected to be strapped to use neither INT nor NMI.  It
+is also not expected to use DMA.
+
 Modes of Operation
 ------------------
 
@@ -520,4 +529,7 @@ WW 12/12/2020: v5.6
   - Updated SmallZ80 support for new I/O map
 
 WW 3/24/2021: v5.7
-  - Added support for a few single-sided formats
+  - Added support for a few single-sided formats
+
+WW 7/26/2021: v5.8
+  - Added support for MBC FDC

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.96"
+#DEFINE BIOSVER	"3.1.1-pre.97"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.96"
+	db	"3.1.1-pre.97"
 	endm