Driver debug standardization

2026-02-06 14:11:48 -06:00 · 2022-11-26 16:03:09 +08:00
parent bd0bb94c52
commit 6d1a9f5b7c
53 changed files with 161 additions and 43 deletions
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -49,6 +49,8 @@
 ;               1 0 - DIVIDE BY 64
 ;               1 1 - MASTER RESET
 ;
+THIS_DRV	.SET	DRV_ID_ACIA
+;
 ACIA_BUFSZ      .EQU    32              ; RECEIVE RING BUFFER SIZE
 ;
 ACIA_NONE       .EQU    0
@@ -373,7 +375,7 @@ ACIA_INITDEV:
 ;
 ACIA_INITDEVX:
 ;
-#IF (ACIADEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
        CALL    NEWLINE
        PRTS("ACIA$")
        LD      A,(IY+2)
@@ -395,7 +397,7 @@ ACIA_INITDEVX:
 ACIA_INITDEV1:
        LD      (ACIA_NEWCFG),DE        ; SAVE NEW CONFIG
 ;
-#IF (ACIADEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
        PUSH    DE
        POP     BC
        PRTS(" CFG=$")
@@ -409,7 +411,7 @@ ACIA_INITDEV1:
        LD      A,D                     ; GET CONFIG MSB
        AND     $1F                     ; ISOLATE ENCODED BAUD RATE
 ;
-#IF (ACIADEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
        PRTS(" ENC=$")
        CALL    PRTHEXBYTE
 #ENDIF
@@ -457,7 +459,7 @@ ACIA_INITDEV1:
 ;
 ACIA_INITFAIL:
 ;
-#IF (ACIADEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
        PRTS(" BAD CFG$")        
 #ENDIF
 ;
@@ -513,7 +515,7 @@ ACIA_INITGO:
 ;
        LD      (ACIA_CMD),A            ; SAVE SHADOW REGISTER
 ;
-#IF (ACIADEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
        PRTS(" CMD=$")
        CALL    PRTHEXBYTE
        LD      DE,65
--- a/Source/HBIOS/asci.asm
+++ b/Source/HBIOS/asci.asm
@@ -64,6 +64,8 @@
 ; | +-------------- DCD0 DISABLE
 ; +---------------- RDRF INT INHIBIT
 ;
+THIS_DRV	.SET	DRV_ID_ASCI
+;
 ASCI_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
 ASCI_NONE	.EQU	0		; NOT PRESENT
--- a/Source/HBIOS/audio.inc
+++ b/Source/HBIOS/audio.inc
@@ -1,4 +1,4 @@
-#IF AUDIOTRACE
+#IF (DEBUG_DRV==THIS_DRV)
 #DEFINE	AUDTRACE(STR)	PUSH DE \ LD DE, STR \ CALL WRITESTR \ POP DE
 #DEFINE AUDTRACE_A	CALL PRTHEXBYTE
 #DEFINE AUDTRACE_B	PUSH AF \ LD A, B \ CALL PRTHEXBYTE \ POP AF
@@ -46,7 +46,7 @@ AUD_NOTE:
 	LD	DE, 48
 	CALL	DIV16
 					; BC IS OCTAVE COUNT
-					; HL is NOTE WITIN OCTAVE
+					; HL is NOTE WITHIN OCTAVE
 	ADD	HL, HL
 	pop	de
 	ADD	HL, DE
--- a/Source/HBIOS/ay38910.asm
+++ b/Source/HBIOS/ay38910.asm
@@ -4,6 +4,9 @@
 ;
 ;======================================================================
 ;
+;
+THIS_DRV	.SET	DRV_ID_AY38910
+;
 ; @3.579545 OCTAVE RANGE IS 2 - 7 (Bb2/A#2 .. A7)
 ; @4.000000 OCTAVE RANGE IS 2 - 7 (B2 .. A7)
 ;
@@ -598,7 +601,7 @@ AY_PENDING_DURATION	.DW	0	; PENDING DURATION (16 BITS)
 AY_READY		.DB	0	; BIT 0 -> NZ DRIVER IS READY TO RECEIVE PLAY COMMAND
 					; BIT 1 -> NZ EXECUTING WITHIN TIMER HANDLER = DO NOT DIS/ENABLE INT
 ;
-#IF AUDIOTRACE
+#IF (DEBUG_DRV==THIS_DRV)
 AYT_INIT		.DB	"\r\nAY_INIT\r\n$"
 AYT_VOLOFF		.DB	"\r\nAY_VOLUME OFF\r\n$"
 AYT_VOL			.DB	"\r\nAY_VOLUME: $"
--- a/Source/HBIOS/bqrtc.asm
+++ b/Source/HBIOS/bqrtc.asm
@@ -54,7 +54,9 @@
 ;  Day-Of-Week coded as Sunday = 1 through Saturday = 7.
 ;  BVF = 1 for valid battery.
 ;  STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode.
-
+;
+THIS_DRV	.SET	DRV_ID_BQRTC
+;
 ; Constants

 BQRTC_SEC	.EQU	BQRTC_BASE + $00
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -135,7 +135,6 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_STD	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -190,7 +190,6 @@ ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -128,7 +128,6 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -142,7 +142,6 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -157,7 +157,6 @@ ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -146,7 +146,6 @@ ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
 ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -128,7 +128,6 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -137,7 +137,6 @@ Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
 SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
--- a/Source/HBIOS/ctc.asm
+++ b/Source/HBIOS/ctc.asm
@@ -5,6 +5,8 @@
 ;   DISPLAY CONFIGURATION DETAILS
 ;______________________________________________________________________________________________________________________
 ;
+THIS_DRV	.SET	DRV_ID_CTC
+;
 CTC_DEFCFG	.EQU	%01010011	; CTC DEFAULT CONFIG
 CTC_CTRCFG	.EQU	%01010111	; CTC COUNTER MODE CONFIG
 CTC_TIM16CFG	.EQU	%00010111	; CTC TIMER/16 MODE CONFIG
--- a/Source/HBIOS/cvdu.asm
+++ b/Source/HBIOS/cvdu.asm
@@ -16,6 +16,8 @@
 ; CVDU DRIVER - CONSTANTS
 ;======================================================================
 ;
+THIS_DRV	.SET	DRV_ID_CVDU
+;
 CVDU_BASE	.EQU	$E0
 ;
 #IF (CVDUMODE == CVDUMODE_ECB)
--- a/Source/HBIOS/dma.asm
+++ b/Source/HBIOS/dma.asm
@@ -2,6 +2,7 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+THIS_DRV			.set	DRV_ID_DMA
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
 DMA_BURST 			.equ	%11011101	; + Pulse
@@ -314,7 +315,7 @@ DMAIn_Len 	.equ	$-DMAInCode
 ; DEBUG - READ START, DESTINATION AND COUNT REGISTERS
 ;==================================================================================================
 ;
-#IF (0)
+#IF (DEBUG_DRV==THIS_DRV)
 ;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
--- a/Source/HBIOS/ds1501rtc.asm
+++ b/Source/HBIOS/ds1501rtc.asm
@@ -60,7 +60,9 @@
 ;  Day-Of-Week coded as Sunday = 1 through Saturday = 7.

 ; Constants
-
+;
+THIS_DRV		.SET	DRV_ID_DS1501RTC
+;
 ;By defining 2 bases, this allows some flexibility for address decoding
 DS1501NVM_BASE      .EQU    DS1501RTC_BASE + $10

--- a/Source/HBIOS/ds7rtc.asm
+++ b/Source/HBIOS/ds7rtc.asm
@@ -5,6 +5,8 @@
 ;
 ;==================================================================================================
 ;
+THIS_DRV	.SET	DRV_ID_DS7RTC
+;
 DS7_OUT		.EQU	10000000B		; SELECT SQUARE WAVE FUNCTION
 DS7_SQWE	.EQU	00010000B		; ENABLE SQUARE WAVE OUTPUT
 DS7_RATE	.EQU	00000000B		; SET 1HZ OUPUT
@@ -133,7 +135,7 @@ DS7_GT0:LD	A,(HL)
 	RES	7,(HL)				; REMOVE OSCILLATOR BIT
 	POP	DE				; HL POINT TO SOURCE
 ;						; DE POINT TO DESTINATION
-#IF (0)
+#IF (DEBUG_DRV==THIS_DRV)
 	PUSH	HL
 	PUSH	DE
 	EX	DE,HL
@@ -323,9 +325,9 @@ DS7_RL1:CALL	PCF_READI2C
 	INC	HL
 	DJNZ    DS7_RL1
 ;
-#IF (0)
+#IF (DEBUG_DRV==THIS_DRV)
 	LD	A,8
-	LD	DE,DS7_BUF	; DISLAY DATA READ
+	LD	DE,DS7_BUF	; DISPLAY DATA READ
 	CALL	PRTHEXBUF	; 
 	CALL   	NEWLINE
 #ENDIF
--- a/Source/HBIOS/dsky.asm
+++ b/Source/HBIOS/dsky.asm
@@ -27,6 +27,8 @@
 ; PB0 |	 $01 [FW]   $41 [0]    $81 [BK]	  $C1 [CL]
 ;
 ;
+THIS_DRV	.SET	DRV_ID_DSKY
+;
 PPIA		.EQU 	DSKYPPIBASE + 0	; PORT A
 PPIB		.EQU 	DSKYPPIBASE + 1	; PORT B
 PPIC		.EQU 	DSKYPPIBASE + 2	; PORT C
--- a/Source/HBIOS/dskyng.asm
+++ b/Source/HBIOS/dskyng.asm
@@ -39,6 +39,9 @@
 ;	10      10      10      10	10
 ;	20      20      20      20	20	L1	L2 	BUZZ
 ;
+;
+THIS_DRV	.SET	DRV_ID_DSKYNG
+;
 PPIA		.EQU 	DSKYPPIBASE + 0	; PORT A
 PPIB		.EQU 	DSKYPPIBASE + 1	; PORT B
 PPIC		.EQU 	DSKYPPIBASE + 2	; PORT C
--- a/Source/HBIOS/dsrtc.asm
+++ b/Source/HBIOS/dsrtc.asm
@@ -89,6 +89,9 @@
 ; D1	----	--	--	--	--	--	--	--	--		CLKSEL	--
 ; D0	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	RTC_IN	--	--	RTC_IN		RTC_IN	RTC_IN
 ;
+;
+THIS_DRV	.SET	DRV_ID_DSRTC
+;
 #IF (DSRTCMODE == DSRTCMODE_STD)
 ;
 DSRTC_IO	.EQU	RTCIO		; RTC PORT
--- a/Source/HBIOS/duart.asm
+++ b/Source/HBIOS/duart.asm
@@ -70,7 +70,7 @@
 ;		8-F = LENGTHS OF 0-7 PLUS ONE
 ;		IF BITS/CHAR = 5 THEN ADD AN ADDITIONAL HALF BIT
 ;
-DUART_DEBUG		.EQU	FALSE
+THIS_DRV		.SET	DRV_ID_DUART
 ;
 DUART_NONE		.EQU	0		; UNKNOWN OR NOT PRESENT
 DUART_2681		.EQU	1		; OLD '681 WITHOUT IVR/GPR
--- a/Source/HBIOS/fd.asm
+++ b/Source/HBIOS/fd.asm
@@ -5,6 +5,7 @@
 ;
 ; TODO:
 ;
+THIS_DRV	.SET	DRV_ID_FD
 ;
 ; PORTS
 ;
--- a/Source/HBIOS/gdc.asm
+++ b/Source/HBIOS/gdc.asm
@@ -6,6 +6,8 @@
 ; GDC DRIVER - CONSTANTS
 ;======================================================================
 ;
+THIS_DRV	.SET	DRV_ID_GDC
+;
 #IF (GDCMODE == GDCMODE_ECB)
 GDC_BASE	.EQU	$??		; GDC BASE I/O PORT
 GDC_DAC_BASE	.EQU	$??		; RAMDAC BASE I/O PORT
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -156,6 +156,56 @@ ERR_TIMEOUT		.EQU	-11	; DEVICE TIMEOUT
 ERR_BADCFG		.EQU	-12	; INVALID CONFIGURATION
 ERR_INTERNAL		.EQU	-13	; INTERNAL ERROR
 ;
+; DEBUG DRIVER IDENTIFIERS
+;
+DRV_ID_NONE		.EQU	0
+DRV_ID_ACIA		.EQU	1
+DRV_ID_ASCI		.EQU	2
+DRV_ID_AY38910		.EQU	3
+DRV_ID_BQRTC		.EQU	4
+DRV_ID_CTC		.EQU	5
+DRV_ID_CVDU		.EQU	6
+DRV_ID_DMA		.EQU	7
+DRV_ID_DS7RTC		.EQU	8
+DRV_ID_DS1501RTC	.EQU	9
+DRV_ID_DSKY		.EQU	10
+DRV_ID_DSKYNG		.EQU	11
+DRV_ID_DSRTC		.EQU	12
+DRV_ID_DUART		.EQU	13
+DRV_ID_FD		.EQU	14
+DRV_ID_GDC		.EQU	15
+DRV_ID_HDSK		.EQU	16
+DRV_ID_IDE		.EQU	17
+DRV_ID_INTRTC		.EQU	18
+DRV_ID_KBD		.EQU	19
+DRV_ID_KIO		.EQU	20
+DRV_ID_LPT		.EQU	21
+DRV_ID_MD		.EQU	22
+DRV_ID_MKY		.EQU	23
+DRV_ID_PCF8584		.EQU	24
+DRV_ID_PIO		.EQU	25
+DRV_ID_PPIDE		.EQU	26
+DRV_ID_PPK		.EQU	27
+DRV_ID_PPP		.EQU	28
+DRV_ID_PRP		.EQU	29
+DRV_ID_RF		.EQU	30
+DRV_ID_RP5RTC		.EQU	31
+DRV_ID_SD		.EQU	32
+DRV_ID_SIMRTC		.EQU	33
+DRV_ID_SIO		.EQU	34
+DRV_ID_SN76489		.EQU	35
+DRV_ID_SPK		.EQU	36
+DRV_ID_TMS		.EQU	37
+DRV_ID_UART		.EQU	38
+DRV_ID_UF		.EQU	39
+DRV_ID_VDU		.EQU	40
+DRV_ID_VGA		.EQU	41
+DRV_ID_YM2612		.EQU	42
+DRV_ID_Z2U		.EQU	43
+;
+DEBUG_DRV		.EQU	DRV_ID_NONE
+THIS_DRV		.EQU	-DEBUG_DRV
+;
 ; HBIOS DIAG OPTIONS
 ;
 DIAG_PROG	.EQU	0		; PROGRESS BAR
--- a/Source/HBIOS/hdsk.asm
+++ b/Source/HBIOS/hdsk.asm
@@ -3,6 +3,8 @@
 ;   HDSK DISK DRIVER
 ;==================================================================================================
 ;
+THIS_DRV		.SET	DRV_ID_HDSK
+;
 ; IO PORT ADDRESSES
 ;
 HDSK_IO		.EQU	$FD
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@@ -105,6 +105,8 @@
 ;	SRST:	SOFTWARE RESET
 ;	~IEN:	INTERRUPT ENABLE
 ;
+THIS_DRV		.SET	DRV_ID_IDE
+;
 IDE_REG_DATA	.EQU	$00	; DATA 	/OUTPUT (R/W)
 IDE_REG_ERR	.EQU	$01	; ERROR REGISTER (R)
 IDE_REG_FEAT	.EQU	$01	; FEATURES REGISTER (W)
--- a/Source/HBIOS/intrtc.asm
+++ b/Source/HBIOS/intrtc.asm
@@ -3,6 +3,8 @@
 ; SYSTEM TIMER BASED CLOCK DRIVER
 ;==================================================================================================
 ;
+THIS_DRV		.SET	DRV_ID_INTRTC
+;
 INTRTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
--- a/Source/HBIOS/kbd.asm
+++ b/Source/HBIOS/kbd.asm
@@ -11,6 +11,8 @@
 ;__________________________________________________________________________________________________
 ; DATA CONSTANTS
 ;__________________________________________________________________________________________________
+
+THIS_DRV		.SET	DRV_ID_KBD
 ;
 ; DRIVER DATA OFFSETS (FROM IY)
 ;
--- a/Source/HBIOS/kio.asm
+++ b/Source/HBIOS/kio.asm
@@ -5,7 +5,7 @@
 ;   DISPLAY CONFIGURATION DETAILS
 ;______________________________________________________________________________________________________________________
 ;
-;
+THIS_DRV	.SET	DRV_ID_KIO
 ;
 KIO_PIOADAT	.EQU	KIOBASE + $00
 KIO_PIOACMD	.EQU	KIOBASE + $01
--- a/Source/HBIOS/lpt.asm
+++ b/Source/HBIOS/lpt.asm
@@ -30,6 +30,8 @@
 ;     | STAT1 | STAT0 | ENBL  | PINT  | SEL   | RES   | LF    | STB   |
 ;     +-------+-------+-------+-------+-------+-------+-------+-------+
 ;
+THIS_DRV	.SET	DRV_ID_LPT
+;
 LPT_NONE	.EQU	0		; NOT PRESENT
 LPT_IBM		.EQU	1		; IBM PC STYLE INTERFACE
 ;
--- a/Source/HBIOS/md.asm
+++ b/Source/HBIOS/md.asm
@@ -12,6 +12,8 @@
 ;	0x00 MEMORY DISK	0x01 ROM DRIVE		%00100000 HD STYLE, NON-REMOVABLE, TYPE-ROM
 ;	0x00 MEMORY DISK	0x01 ROM DRIVE		%00111000 HD STYLE, NON-REMOVABLE, TYPE-FLASH
 ;
+THIS_DRV	.SET	DRV_ID_MD
+;
 ;MD_DEVCNT	.EQU	2		; NUMBER OF MD DEVICES SUPPORTED
 MD_CFGSIZ	.EQU	8		; SIZE OF CFG TBL ENTRIES
 ;
--- a/Source/HBIOS/mky.asm
+++ b/Source/HBIOS/mky.asm
@@ -27,6 +27,8 @@
 ; DRIVER - CONSTANTS
 ;======================================================================
 ;
+THIS_DRV		.SET	DRV_ID_MKY
+;
 MKY_REGA		.EQU	$A8
 MKY_REGB		.EQU	$A9
 MKY_REGC		.EQU	$AA
--- a/Source/HBIOS/pcf8584.asm
+++ b/Source/HBIOS/pcf8584.asm
@@ -2,6 +2,8 @@
 ; PCF8584 I2C CLOCK DRIVER
 ;==================================================================================================
 ;
+THIS_DRV	.SET	DRV_ID_PCF8584
+;
 PCF_BASE  	.EQU  0F0H
 PCF_ID   	.EQU  0AAH
 CPU_CLK	  	.EQU  12
@@ -470,7 +472,7 @@ PCF_PRTERR:
 ;-----------------------------------------------------------------------------
 ; DEBUG HELPER
 ;
-#IF (1)
+#IF (DEBUG_DRV==THIS_DRV)
 PCF_DBG:
 	PUSH	AF
 	PUSH 	DE
--- a/Source/HBIOS/pio.asm
+++ b/Source/HBIOS/pio.asm
@@ -14,6 +14,8 @@
 ; IF IT EXISTS.  FOR NOW, IT DOES NOT REGISTER ANY OF THE PIO CHANNELS
 ; AS CHARCTER DEVICE UNITS.
 ;
+THIS_DRV		.SET	DRV_ID_PIO
+;
 PIO_NONE	.EQU	0
 PIO_PIO		.EQU	1
 ;
--- a/Source/HBIOS/ppide.asm
+++ b/Source/HBIOS/ppide.asm
@@ -20,6 +20,8 @@
 ; IT IS DRIVING THE ADDRESS BUS AND CONTROL SIGNALS.  PORTS A & B WILL BE
 ; PLACED IN READ OR WRITE MODE DEPENDING ON THE DIRECTION OF THE DATA BUS.
 ;
+THIS_DRV	.SET	DRV_ID_PPIDE
+;
 PPIDE_DIR_READ	.EQU	%10010010	; IDE BUS DATA INPUT MODE
 PPIDE_DIR_WRITE	.EQU	%10000000	; IDE BUS DATA OUTPUT MODE
 ;
--- a/Source/HBIOS/ppk.asm
+++ b/Source/HBIOS/ppk.asm
@@ -12,6 +12,8 @@
 ; DATA CONSTANTS
 ;__________________________________________________________________________________________________
 ;
+THIS_DRV	.SET	DRV_ID_PPK
+;
 ; DRIVER DATA OFFSETS (FROM IY)
 ;
 PPK_PPIA	.EQU	0	; PPI PORT A
--- a/Source/HBIOS/ppp.asm
+++ b/Source/HBIOS/ppp.asm
@@ -6,6 +6,8 @@
 ; TODO:
 ;   1) ADD SUPPORT FOR DSKY
 ;
+THIS_DRV	.SET	DRV_ID_PPP
+;
 PPP_IO		.EQU	PPPBASE + 0	; PPP DATA I/O (PPI PORT A)
 PPP_CTL		.EQU	PPPBASE + 2	; PPP CTL LINES (PPI PORT C)
 PPP_PPICTL	.EQU	PPPBASE + 3	; PPI CONTROL PORT
--- a/Source/HBIOS/prp.asm
+++ b/Source/HBIOS/prp.asm
@@ -6,6 +6,8 @@
 ; TODO:
 ;   1) ADD SUPPORT FOR DSKY
 ;
+THIS_DRV	.SET	DRV_ID_PRP
+;
 PRP_IOBASE	.EQU	$A8
 ;
 ; GLOBAL PROPIO INITIALIZATION
--- a/Source/HBIOS/rf.asm
+++ b/Source/HBIOS/rf.asm
@@ -3,7 +3,7 @@
 ;   RAM FLOPPY DISK DRIVER
 ;==================================================================================================
 ;
-;
+THIS_DRV	.SET	DRV_ID_RF
 ;
 RF_U0IO		.EQU	$A0		; BASED ADDRESS OF RAMFLOPPY 1
 RF_U1IO		.EQU	$A4		; BASED ADDRESS OF RAMFLOPPY 2
--- a/Source/HBIOS/rp5rtc.asm
+++ b/Source/HBIOS/rp5rtc.asm
@@ -3,6 +3,8 @@
 ; RP5C01 CLOCK DRIVER
 ;==================================================================================================
 ;
+THIS_DRV		.SET	DRV_ID_RP5RTC
+;
 RP5RTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
 ;
 ; RTC DEVICE INITIALIZATION ENTRY
--- a/Source/HBIOS/sd.asm
+++ b/Source/HBIOS/sd.asm
@@ -81,6 +81,8 @@
 ;
 ;------------------------------------------------------------------------------
 ;
+THIS_DRV	.SET	DRV_ID_SD
+;
 ; *** HACK FOR MISSING PULLUP RESISTORS ***
 ;
 ; THERE IS A RECENT TREND FOR SD ADAPTER BOARDS (SUCH AS THOSE USED TO ATTACH AN
--- a/Source/HBIOS/simrtc.asm
+++ b/Source/HBIOS/simrtc.asm
@@ -3,6 +3,8 @@
 ; SIMH RTC DRIVER
 ;==================================================================================================
 ;
+THIS_DRV		.SET	DRV_ID_SIMRTC
+;
 SIMRTC_IO	.EQU	$FE	; SIMH IO PORT
 SIMRTC_CLKREAD	.EQU	7	; READ CLOCK COMMAND
 SIMRTC_CLKWRITE	.EQU	8	; WRITE CLOCK COMMAND
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -16,6 +16,8 @@
 ; 
 ; SIO PORT A (COM1:) and SIO PORT B (COM2:) ARE MAPPED TO DEVICE UC1: AND UL1: IN CP/M.
 ;
+THIS_DRV	.SET	DRV_ID_SIO
+;
 SIO_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
 SIO_NONE	.EQU	0
@@ -472,7 +474,7 @@ SIO_INITDEVX:
 ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
 ; PREINIT ABOVE.  PREINIT IS NOT ALLOWED TO ENABLE INTS!
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	CALL	NEWLINE
 	PRTS("SIO$")
 	LD	A,(IY+2)
@@ -497,7 +499,7 @@ SIO_INITDEVX:
 ;
 SIO_INITDEV1:
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PUSH	DE
 	POP	BC
 	PRTS(" CFG=$")
@@ -522,7 +524,7 @@ SIO_INITDEV1:
 	LD	C,75			; DIVIDE BY 75 LIKE BAUD RATE
 	CALL	DIV32X8			; HL NOW HAS (CLK / 75)
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" CLK75=$")
 	CALL	PRTHEX32
 #ENDIF
@@ -542,7 +544,7 @@ SIO_INITDEV1A:
 	JR	SIO_INITDEV1A		; AND LOOP
 SIO_INITDEV1B:
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" CLK=$")
 	CALL	PRTHEX32
 #ENDIF
@@ -561,7 +563,7 @@ SIO_INITDEV1B:
 	LD	DE,1			; USE 1 FOR ENCODING CONSTANT
 	CALL	DECODE			; DE:HL := BAUD RATE, ERRORS IGNORED
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" BAUD75=$")
 	CALL	PRTHEX32
 #ENDIF
@@ -579,7 +581,7 @@ SIO_INITDEV1C:
 	DJNZ	SIO_INITDEV1C		; LOOP UNTIL DONE SHIFTING
 SIO_INITDEV1D:
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" BAUD=$")
 	CALL	PRTHEX32
 #ENDIF
@@ -589,7 +591,7 @@ SIO_INITDEV1D:
 	; *** HANDLE DIVIDE BY ZERO??? ***
 	CALL	DIV16			; BC := HL/DE == TARGET DIVISOR
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" DIV=$")
 	CALL	PRTHEXWORD
 #ENDIF
@@ -634,7 +636,7 @@ SIO_INITDEV1D:
 	
 	; *** CHECK FOR CARRY??? ***
 ;
-  #IF (SIODEBUG)
+  #IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" DIV=$")
 	CALL	PRTHEXWORD
  #ENDIF
@@ -689,7 +691,7 @@ SIO_INITDEV4:
 ;
 	POP	DE			; RESTORE DE = SERIAL CONFIG
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PUSH	BC
 	PUSH	HL
 	POP	BC
@@ -717,7 +719,7 @@ SIO_INITDEV4:
 	; ALL GOOD.  PROGRAM THE CTC CHANNEL
 	LD	A,(IY+13)		; GET CTC CHANNEL
 	ADD	A,CTCBASE		; ADD TO CTC BASE PORT ADR
-  #IF (SIODEBUG)
+  #IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" CTC=$")
 	CALL	PRTHEXBYTE
  #ENDIF
@@ -746,7 +748,7 @@ SIO_NOCTC:
 ;
 SIO_INITFAIL:
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" BAD CFG$")	
 #ENDIF
 ;
@@ -851,7 +853,7 @@ SIO_INITIVT:
 ;
 #ENDIF
 ;
-#IF (SIODEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	LD	HL,SIO_INITVALS
 	LD	B,SIO_INITLEN/2
 SIO_INITPRT:
--- a/Source/HBIOS/sn76489.asm
+++ b/Source/HBIOS/sn76489.asm
@@ -12,6 +12,8 @@
 ; CONSTANTS
 ;======================================================================
 ;
+THIS_DRV		.SET	DRV_ID_SN76489
+;
 #IF (PLATFORM == PLT_SBC) & (SNMODE == SNMODE_VGM)
 SN76489_PORT_LEFT	.EQU	$C6	; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT)
 SN76489_PORT_RIGHT	.EQU	$C7	; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT)
@@ -399,7 +401,7 @@ SN7_PENDING_DURATION
 STR_MESSAGELT	.DB	"\r\nSN76489: LEFT IO=0x$"
 STR_MESSAGERT	.DB	", RIGHT IO=0x$"

-#IF AUDIOTRACE
+#IF (DEBUG_DRV==THIS_DRV)
 SNT_INIT		.DB	"\r\nSN7_INIT\r\n$"
 SNT_VOLOFF		.DB	"\r\nSN7_VOLUME OFF\r\n$"
 SNT_VOL			.DB	"\r\nSN7_VOLUME: $"
--- a/Source/HBIOS/spk.asm
+++ b/Source/HBIOS/spk.asm
@@ -10,6 +10,8 @@
 ;			NO VOLUME ADJUSTMENT DUE TO HARDWARE LIMITATION
 ;======================================================================
 ;
+THIS_DRV		.SET	DRV_ID_SPK
+;
 ;	DRIVER FUNCTION TABLE AND INSTANCE DATA
 ;
 SP_FNTBL:
--- a/Source/HBIOS/tms.asm
+++ b/Source/HBIOS/tms.asm
@@ -15,7 +15,8 @@
 ; TMS DRIVER - CONSTANTS
 ;======================================================================
 ;
-
+THIS_DRV	.SET	DRV_ID_TMS
+;
 TMSCTRL1:       .EQU   1               ; CONTROL BITS
 TMSINTEN:       .EQU   5               ; INTERRUPT ENABLE BIT

--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@@ -18,7 +18,7 @@
 ;              -- MCR --                        -- LCR --
 ;
 ;
-UART_DEBUG		.EQU	FALSE
+THIS_DRV		.SET	DRV_ID_UART
 ;
 UART_BUFSZ		.EQU	32	; RECEIVE RING BUFFER SIZE
 ;
@@ -640,7 +640,7 @@ UART_INITDEV5:
 #ENDIF
 ;
 ;
-#IF (UART_DEBUG)
+#IF (DEBUG_DRV==THIS_DRV)
 	PRTS(" [$")
 	
 	; DEBUG: DUMP UART TYPE
--- a/Source/HBIOS/uf.asm
+++ b/Source/HBIOS/uf.asm
@@ -13,6 +13,8 @@
 ;	UF_PREINIT	SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE	
 ;	UF_INIT		ANNOUNCE DEVICE DESCRIPTION AND PORT
 ;
+THIS_DRV	.SET	DRV_ID_UF
+;
 FIFO_DATA       .EQU	(UFBASE+0)	; READ/WRITE DATA
 FIFO_STATUS     .EQU	(UFBASE+1)	; READ/WRITE STATUS
 FIFO_SEND_IMM   .EQU	(UFBASE+2)	; WRITE PORT TO FORCE BUFFER FLUSH
--- a/Source/HBIOS/vdu.asm
+++ b/Source/HBIOS/vdu.asm
@@ -21,6 +21,8 @@
 ; VDU DRIVER - CONSTANTS
 ;======================================================================
 ;
+THIS_DRV	.SET	DRV_ID_VDU
+;
 VDU_BASE	.EQU	$F0
 ;
 VDU_RAMRD	.EQU	VDU_BASE + $00	; READ VDU
--- a/Source/HBIOS/vga.asm
+++ b/Source/HBIOS/vga.asm
@@ -10,6 +10,8 @@
 ; VGA DRIVER - CONSTANTS
 ;======================================================================
 ;
+THIS_DRV	.SET	DRV_ID_VGA
+;
 VGA_BASE	.EQU	$E0
 ;
 VGA_KBDDATA	.EQU	VGA_BASE + $00	; KBD CTLR DATA PORT
--- a/Source/HBIOS/ym2612.asm
+++ b/Source/HBIOS/ym2612.asm
@@ -10,6 +10,8 @@
 ; 
 ;======================================================================
 ;
+THIS_DRV	.SET	DRV_ID_YM2612
+;
 YMSEL		.EQU	VGMBASE+00H		; Primary YM2162 11000000 a1=0 a0=0
 YMDAT		.EQU	VGMBASE+01H		; Primary YM2162 11000001 a1=0 a0=1
 YM2SEL		.EQU	VGMBASE+02H		; Secondary YM2162 11000010 a1=1 a0=0
--- a/Source/HBIOS/z2u.asm
+++ b/Source/HBIOS/z2u.asm
@@ -56,7 +56,7 @@
 ; UNLESS FULL BLOWN INTERRUPT MODE 3 W/ NATIVE MEMORY MANAGEMENT
 ; IS BEING USED.
 ;
-;
+THIS_DRV	.SET	DRV_ID_Z2U
 ;
 #IF (Z2U0HFC)
 Z2U_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE