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Support Coleco AY-3-8910 Ports

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This commit is contained in:
Wayne Warthen
2026-02-05 17:04:42 -08:00
parent 8d8dc4c16f
commit 71a1bfbe81
28 changed files with 99 additions and 203 deletions
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8
Source/Apps/Tune/cli.inc
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@@ -51,6 +51,13 @@ CLI_PORTS1:
LD A,PORTS_RC LD A,PORTS_RC
JR CLI_PORTS_Z JR CLI_PORTS_Z
CLI_PORTS2: CLI_PORTS2:
LD HL, CLIARGS ; TEST FOR -COLECO ON COMMAND LINE
LD DE, OPT_COLECO
CALL STRINDEX
JR NZ, CLI_PORTS3
LD A,PORTS_COLECO
JR CLI_PORTS_Z
CLI_PORTS3:
LD A,PORTS_AUTO ; USE AUTO PORT SELECTION LD A,PORTS_AUTO ; USE AUTO PORT SELECTION
CLI_PORTS_Z: CLI_PORTS_Z:
LD (USEPORTS),A ; SAVE PORTS SELECTION LD (USEPORTS),A ; SAVE PORTS SELECTION
@@ -114,6 +121,7 @@ CLI_OCTAVE_ADJST5:
OPT_MSX .DB "-MSX", 0 ; USE MSX PORTS OPT_MSX .DB "-MSX", 0 ; USE MSX PORTS
OPT_RC .DB "-RC", 0 ; USE RC PORTS OPT_RC .DB "-RC", 0 ; USE RC PORTS
OPT_COLECO .DB "-COLECO", 0 ; USE COLECO PORTS
HBIOSOPT: .DB "--HBIOS", 0 ; USE HBIOS API FOR PLAYBACK HBIOSOPT: .DB "--HBIOS", 0 ; USE HBIOS API FOR PLAYBACK
DELAYOPT: .DB "-DELAY",0 ; FORCE DELAY MODE DELAYOPT: .DB "-DELAY",0 ; FORCE DELAY MODE
DOWN1 .DB "-t1", 0 ; DOWN AN OCTAVE DOWN1 .DB "-t1", 0 ; DOWN AN OCTAVE

43
Source/Apps/Tune/tune.asm
View File

@@ -56,6 +56,7 @@
; 2025-05-28 [WBW] Add option to force delay mode ; 2025-05-28 [WBW] Add option to force delay mode
; 2026-01-24 [WBW] Support RC2014 platform id ; 2026-01-24 [WBW] Support RC2014 platform id
; 2026-01-31 [WBW] Update MUTE funtion to zero all PSG registers ; 2026-01-31 [WBW] Update MUTE funtion to zero all PSG registers
; 2026-02-03 [JMD] Add Coleco (50H/51H/52H) auto-detect
;_______________________________________________________________________________ ;_______________________________________________________________________________
; ;
; ToDo: ; ToDo:
@@ -80,6 +81,7 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file
PORTS_AUTO .EQU 0 ; AUTO select audio chip ports PORTS_AUTO .EQU 0 ; AUTO select audio chip ports
PORTS_MSX .EQU 1 ; force MSX audio chip ports PORTS_MSX .EQU 1 ; force MSX audio chip ports
PORTS_RC .EQU 2 ; force RCBUS audio chip ports PORTS_RC .EQU 2 ; force RCBUS audio chip ports
PORTS_COLECO .EQU 3 ; force Coleco-style ports (50H/51H)
; ;
; HIGH SPEED CPU CONTROL ; HIGH SPEED CPU CONTROL
; ;
@@ -133,15 +135,18 @@ CONTINUE:
LD A, (HBIOSMD) LD A, (HBIOSMD)
OR A OR A
JR NZ, TSTTIMER ; skip hardware check if using hbios JP NZ, TSTTIMER ; skip hardware check if using hbios
LD A, (USEPORTS) ; get ports option LD A, (USEPORTS) ; get ports option
LD HL,MSXPORTS ; assume MSX LD HL,MSXPORTS ; assume MSX
CP PORTS_MSX ; use MSX? CP PORTS_MSX ; use MSX?
JR Z,FORCE JR Z,FORCE
LD HL,RCPORTS ; asssume RC LD HL,RCPORTS ; assume RC
CP PORTS_RC ; use RC? CP PORTS_RC ; use RC?
JR Z,FORCE JR Z,FORCE
LD HL,COLECOPORTS ; assume Coleco ports
CP PORTS_COLECO ; use Coleco?
JR Z,FORCE
JR AUTOSEL ; otherwise do auto select JR AUTOSEL ; otherwise do auto select
FORCE: FORCE:
@@ -609,6 +614,9 @@ CFGSIZ .EQU $ - CFGTBL
; ;
.DB $07, $33, $32, $32, $FF, $FF, $FF ; RCZ80 W/ LINC SOUND MODULE .DB $07, $33, $32, $32, $FF, $FF, $FF ; RCZ80 W/ LINC SOUND MODULE
.DW HWSTR_LINC .DW HWSTR_LINC
;
.DB $07, $50, $51, $52, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (COLECO)
.DW HWSTR_COLECO
; ;
.DB $08, $68, $60, $68, $C0, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (EB) .DB $08, $68, $60, $68, $C0, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB .DW HWSTR_RCEB
@@ -621,6 +629,9 @@ CFGSIZ .EQU $ - CFGTBL
; ;
.DB $08, $33, $32, $32, $C0, $FF, $FF ; RCZ180 W/ LINC SOUND MODULE .DB $08, $33, $32, $32, $C0, $FF, $FF ; RCZ180 W/ LINC SOUND MODULE
.DW HWSTR_LINC .DW HWSTR_LINC
;
.DB $08, $50, $51, $52, $FF, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (COLECO)
.DW HWSTR_COLECO
; ;
.DB $09, $D8, $D0, $D8, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (EB) .DB $09, $D8, $D0, $D8, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB .DW HWSTR_RCEB
@@ -633,6 +644,9 @@ CFGSIZ .EQU $ - CFGTBL
; ;
.DB $09, $33, $32, $32, $FF, $FF, $FF ; EZZ80 W/ LINC SOUND MODULE .DB $09, $33, $32, $32, $FF, $FF, $FF ; EZZ80 W/ LINC SOUND MODULE
.DW HWSTR_LINC .DW HWSTR_LINC
;
.DB $09, $50, $51, $52, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (COLECO)
.DW HWSTR_COLECO
; ;
.DB $0A, $68, $60, $68, $C0, $FF, $FF ; SCZ180 W/ RC SOUND MODULE (EB) .DB $0A, $68, $60, $68, $C0, $FF, $FF ; SCZ180 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB .DW HWSTR_RCEB
@@ -645,6 +659,9 @@ CFGSIZ .EQU $ - CFGTBL
; ;
.DB $0A, $33, $32, $32, $C0, $FF, $FF ; SCZ180 W/ LINC SOUND MODULE .DB $0A, $33, $32, $32, $C0, $FF, $FF ; SCZ180 W/ LINC SOUND MODULE
.DW HWSTR_LINC .DW HWSTR_LINC
;
.DB $0A, $50, $51, $52, $FF, $FF, $FF ; SCZ80 W/ RC SOUND MODULE (COLECO)
.DW HWSTR_COLECO
; ;
.DB $0B, $D8, $D0, $D8, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB) .DB $0B, $D8, $D0, $D8, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB .DW HWSTR_RCEB
@@ -657,6 +674,9 @@ CFGSIZ .EQU $ - CFGTBL
; ;
.DB $0B, $33, $32, $32, $FF, $FF, $FF ; RCZ280 W/ LINC SOUND MODULE .DB $0B, $33, $32, $32, $FF, $FF, $FF ; RCZ280 W/ LINC SOUND MODULE
.DW HWSTR_LINC .DW HWSTR_LINC
;
.DB $0B, $50, $51, $52, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (COLECO)
.DW HWSTR_COLECO
; ;
.DB 13, $A0, $A1, $A0, $FF, $A2, $FE ; MBC .DB 13, $A0, $A1, $A0, $FF, $A2, $FE ; MBC
.DW HWSTR_MBC .DW HWSTR_MBC
@@ -670,17 +690,17 @@ CFGSIZ .EQU $ - CFGTBL
.DB 22, $41, $40, $40, $FF, $FF, $FF ; NABU .DB 22, $41, $40, $40, $FF, $FF, $FF ; NABU
.DW HWSTR_NABU .DW HWSTR_NABU
; ;
.DB 27, $D8, $D0, $D8, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (EB) .DB 27, $D8, $D0, $D8, $FF, $FF, $FF ; RC2014 W/ RC SOUND MODULE (EB)
.DW HWSTR_RCEB .DW HWSTR_RCEB
; ;
.DB 27, $A0, $A1, $A2, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (MSX) .DB 27, $A0, $A1, $A2, $FF, $FF, $FF ; RC2014 W/ RC SOUND MODULE (MSX)
.DW HWSTR_RCMSX .DW HWSTR_RCMSX
; ;
.DB 27, $D1, $D0, $D0, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (MF) .DB 27, $D1, $D0, $D0, $FF, $FF, $FF ; RC2014 W/ RC SOUND MODULE (MF)
.DW HWSTR_RCMF .DW HWSTR_RCMF
; ;
.DB 27, $33, $32, $32, $FF, $FF, $FF ; RCZ80 W/ LINC SOUND MODULE .DB 27, $50, $51, $52, $FF, $FF, $FF ; RC2014 W/ RC SOUND MODULE (COLECO)
.DW HWSTR_LINC .DW HWSTR_COLECO
; ;
.DB $FF ; END OF TABLE MARKER .DB $FF ; END OF TABLE MARKER
; ;
@@ -695,6 +715,10 @@ RCPORTS:
.DB $FF, $D8, $D0, $FF, $FF, $FF, $FF ; GENERIC RC .DB $FF, $D8, $D0, $FF, $FF, $FF, $FF ; GENERIC RC
.DW HWSTR_RC .DW HWSTR_RC
; ;
COLECOPORTS:
.DB $FF, $50, $51, $52, $FF, $FF, $FF ; GENERIC COLECO AY PORTS (50H/51H, READ AT 52H)
.DW HWSTR_COLECO
;
CFG: ; ACTIVE CONFIG VALUES (FROM SELECTED CFGTBL ENTRY) CFG: ; ACTIVE CONFIG VALUES (FROM SELECTED CFGTBL ENTRY)
PLT .DB 0 ; RomWBW HBIOS platform id PLT .DB 0 ; RomWBW HBIOS platform id
PORTS: PORTS:
@@ -724,11 +748,11 @@ OCTAVEADJ .DB 0 ; AMOUNT TO ADJUST OCTAVE UP OR DOWN
USEPORTS .DB 0 ; AUDIO CHIP PORT SELECTION MODE USEPORTS .DB 0 ; AUDIO CHIP PORT SELECTION MODE
MSGBAN .DB "Tune Player for RomWBW v3.15, 31-Jan-2026",0 MSGBAN .DB "Tune Player for RomWBW v3.16, 5-fEB-2026",0
MSGUSE .DB "Copyright (C) 2026, Wayne Warthen, GNU GPL v3",13,10 MSGUSE .DB "Copyright (C) 2026, Wayne Warthen, GNU GPL v3",13,10
.DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10 .DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10
.DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10 .DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10
.DB "Usage: TUNE <filename>.[PT2|PT3|MYM] [-msx|-rc] [-delay] [--hbios] [+tn|-tn]",0 .DB "Usage: TUNE <filename>.[PT2|PT3|MYM] [-msx|-rc|-coleco] [-delay] [--hbios] [+tn|-tn]",0
MSGBIO .DB "Incompatible BIOS or version, " MSGBIO .DB "Incompatible BIOS or version, "
.DB "HBIOS v", '0' + RMJ, ".", '0' + RMN, " required",0 .DB "HBIOS v", '0' + RMJ, ".", '0' + RMN, " required",0
MSGPLT .DB "Hardware error, system not supported!",0 MSGPLT .DB "Hardware error, system not supported!",0
@@ -754,6 +778,7 @@ HWSTR_NABU .DB "NABU Onboard Sound",0
HWSTR_HEATH .DB "HEATH H8 MSX Module",0 HWSTR_HEATH .DB "HEATH H8 MSX Module",0
HWSTR_MSX .DB "MSX Standard Ports (A0H/A1H)",0 HWSTR_MSX .DB "MSX Standard Ports (A0H/A1H)",0
HWSTR_RC .DB "RCBus Standard Ports (D8H/D0H)",0 HWSTR_RC .DB "RCBus Standard Ports (D8H/D0H)",0
HWSTR_COLECO .DB "RCBus Coleco Ports (50H/51H)",0
MSGUNSUP .db "MYM files not supported with HBIOS yet!\r\n", 0 MSGUNSUP .db "MYM files not supported with HBIOS yet!\r\n", 0

9
Source/Apps/rtc/rtc.asm
View File

@@ -35,7 +35,7 @@
; ;
;[2024/09/02] v1.10 Support Genesis STD Z180 ;[2024/09/02] v1.10 Support Genesis STD Z180
; ;
;[2026/01/24] v1.11 Support rc2014 ;[2026/01/24] v1.11 Support RC2014
; ;
; Constants ; Constants
; ;
@@ -57,7 +57,7 @@ PORT_MBC .EQU $70 ; RTC port for MBC
PORT_RPH .EQU $84 ; RTC port for RHYOPHYRE PORT_RPH .EQU $84 ; RTC port for RHYOPHYRE
PORT_DUO .EQU $94 ; RTC port for DUODYNE PORT_DUO .EQU $94 ; RTC port for DUODYNE
PORT_STDZ180 .EQU $84 ; RTC Port for STD Bus Z180 board PORT_STDZ180 .EQU $84 ; RTC Port for STD Bus Z180 board
PORT_RC2014 .EQU $C0 ; RTC port for RC2014
BDOS .EQU 5 ; BDOS invocation vector BDOS .EQU 5 ; BDOS invocation vector
FCB .EQU 05CH ; Start of command line FCB .EQU 05CH ; Start of command line
@@ -1153,8 +1153,8 @@ HINIT:
CP 21 ; STD Z180 CP 21 ; STD Z180
JP Z,RTC_INIT2 JP Z,RTC_INIT2
; ;
LD C,PORT_STDZ180 LD C,PORT_RC2014
LD DE,PLT_STDZ180 LD DE,PLT_RC2014
CP 27 ; RC2014 CP 27 ; RC2014
JP Z,RTC_INIT2 JP Z,RTC_INIT2
; ;
@@ -1786,6 +1786,7 @@ PLT_MBC .TEXT ", MBC RTC Latch Port 0x70\r\n$"
PLT_RPH .TEXT ", RHYOPHYRE RTC Latch Port 0x84\r\n$" PLT_RPH .TEXT ", RHYOPHYRE RTC Latch Port 0x84\r\n$"
PLT_DUO .TEXT ", DUODYNE RTC Latch Port 0x70\r\n$" PLT_DUO .TEXT ", DUODYNE RTC Latch Port 0x70\r\n$"
PLT_STDZ180 .TEXT ", STD Z180 RTC Module latch port 0x84\r\n$" PLT_STDZ180 .TEXT ", STD Z180 RTC Module latch port 0x84\r\n$"
PLT_RC2014 .TEXT ", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
; ;
; Generic FOR-NEXT loop algorithm ; Generic FOR-NEXT loop algorithm

11
Source/HBIOS/ay38910.asm
View File

@@ -77,6 +77,13 @@ AY_RIN .EQU $A2
DEVECHO "MSX" DEVECHO "MSX"
#ENDIF #ENDIF
; ;
#IF (AYMODE == AYMODE_COLECO)
AY_RSEL .EQU $50
AY_RDAT .EQU $51
AY_RIN .EQU AY_RDAT
DEVECHO "COLECO"
#ENDIF
;
#IF (AYMODE == AYMODE_LINC) #IF (AYMODE == AYMODE_LINC)
AY_RSEL .EQU $33 AY_RSEL .EQU $33
AY_RDAT .EQU $32 AY_RDAT .EQU $32
@@ -212,6 +219,10 @@ AY38910_INIT:
PRTS(" MODE=MSX$") PRTS(" MODE=MSX$")
#ENDIF #ENDIF
; ;
#IF (AYMODE == AYMODE_COLECO)
PRTS(" MODE=COLECO$")
#ENDIF
;
#IF (AYMODE == AYMODE_MBC) #IF (AYMODE == AYMODE_MBC)
PRTS(" MODE=MBC$") PRTS(" MODE=MBC$")
#ENDIF #ENDIF

10
Source/HBIOS/cfg_DUO.asm
View File

@@ -45,7 +45,7 @@
#DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES #DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION #DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION
; ;
#INCLUDE "cfg_MASTER.asm" #INCLUDE "cfg_MASTER.asm"
; ;
@@ -87,7 +87,7 @@ RTCIO .SET $94 ; RTC LATCH REGISTER ADR
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
; ;
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
CTCBASE .SET $60 ; CTC BASE I/O ADDRESS CTCBASE .SET $60 ; CTC BASE I/O ADDRESS
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
@@ -155,10 +155,8 @@ DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
; ;
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
; ;
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
; ;
@@ -350,7 +348,7 @@ PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .SET $68 ; PIO 0: REGISTERS BASE ADR PIO0BASE .SET $68 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .SET $6C ; PIO 1: REGISTERS BASE ADR PIO1BASE .SET $6C ; PIO 1: REGISTERS BASE ADR
; ;
LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
@@ -401,7 +399,7 @@ SNMODE .SET SNMODE_DUO ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_DUO ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_DUO ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_DYNO.asm
View File

@@ -376,7 +376,7 @@ SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_EPITX.asm
View File

@@ -410,7 +410,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_EZZ80.asm
View File

@@ -451,7 +451,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_GMZ180.asm
View File

@@ -407,7 +407,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
; ;

2
Source/HBIOS/cfg_HEATH.asm
View File

@@ -401,7 +401,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
; ;

2
Source/HBIOS/cfg_MASTER.asm
View File

@@ -540,7 +540,7 @@ SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .EQU FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .EQU FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

27
Source/HBIOS/cfg_MBC.asm
View File

@@ -45,7 +45,7 @@
#DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES #DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE
#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED
#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION #DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION
; ;
#INCLUDE "cfg_MASTER.asm" #INCLUDE "cfg_MASTER.asm"
; ;
@@ -84,7 +84,7 @@ RTCIO .SET $70 ; RTC LATCH REGISTER ADR
KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .SET $80 ; KIO BASE I/O ADDRESS KIOBASE .SET $80 ; KIO BASE I/O ADDRESS
; ;
CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT
CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS
CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER
@@ -114,7 +114,7 @@ FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
; ;
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
; ;
LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED)
LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU]
LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS
LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
@@ -142,16 +142,15 @@ KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS
; ;
DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
; ;
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
; ;
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
; ;
@@ -161,7 +160,6 @@ HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
; ;
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
; ;
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
; ;
@@ -189,7 +187,7 @@ TSERCFG .SET SER_9600_8N1 ; TSER: SERIAL LINE CONFIG
; ;
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
; ;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .SET 3 ; UART: NUMBER OF CHIPS TO DETECT (1-8) UARTCNT .SET 3 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -218,7 +216,7 @@ Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
; ;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
; ;
SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
@@ -238,11 +236,11 @@ XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG
; ;
VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
CVDUMODE .SET CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] CVDUMODE .SET CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
TMSMODE .SET TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY|N8PC] TMSMODE .SET TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY|N8PC]
TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
@@ -269,7 +267,6 @@ FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
; ;
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
; ;
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEDETECTMEDIA .SET FALSE ; IDE: PROBE FOR MEDIA IN MASTER UNIT, IF NOT DETECTED THEN DON'T ENABLE DRIVER IDEDETECTMEDIA .SET FALSE ; IDE: PROBE FOR MEDIA IN MASTER UNIT, IF NOT DETECTED THEN DON'T ENABLE DRIVER
@@ -331,9 +328,8 @@ ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
ESPCONENABLE .SET TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT ESPCONENABLE .SET TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
; ;
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
; ;
PIOENABLE .SET TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
@@ -378,7 +374,6 @@ PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
; ;
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
; ;
CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER
; ;
@@ -390,7 +385,7 @@ SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
; ;
SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
SPKPORT .SET RTCIO ; SPK: THE PORT WITH THE SPEAKER IO BIT SPKPORT .SET RTCIO ; SPK: THE PORT WITH THE SPEAKER IO BIT

2
Source/HBIOS/cfg_MK4.asm
View File

@@ -367,7 +367,7 @@ SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_MON.asm
View File

@@ -408,7 +408,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_MSX.asm
View File

@@ -411,7 +411,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_N8.asm
View File

@@ -371,7 +371,7 @@ SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_N8PC.asm
View File

@@ -384,7 +384,7 @@ SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 3579545 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 3579545 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_N8PC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_N8PC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

125
Source/HBIOS/cfg_NABU.asm
View File

@@ -107,15 +107,9 @@ SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K
; ;
WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
WDOGIO .SET $6E ; WATCHDOG REGISTER ADR
; ;
FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS
FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS
FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED
FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES
FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES
FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED
; ;
DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING
; ;
@@ -167,7 +161,6 @@ HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
; ;
DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF]
; ;
DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
; ;
@@ -180,29 +173,14 @@ DS12RTCENABLE .SET FALSE ; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM) M6242RTCENABLE .SET FALSE ; M6242RTC: ENABLE M6242 CLOCK DRIVER (M6242.ASM)
; ;
SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
SSERSTATUS .SET $FF ; SSER: STATUS PORT
SSERDATA .SET $FF ; SSER: DATA PORT
SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK
SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED
SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK
SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED
; ;
DLPSERENABLE .SET FALSE ; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM) DLPSERENABLE .SET FALSE ; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM)
; ;
TSERENABLE .SET FALSE ; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM) TSERENABLE .SET FALSE ; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
TSERCFG .SET SER_9600_8N1 ; TSER: SERIAL LINE CONFIG
; ;
DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP
DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP
DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
; ;
UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
@@ -230,38 +208,8 @@ ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
; ;
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT
ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR
ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ
ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER
ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR
ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ
ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER
ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
; ;
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR
SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
; ;
SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
; ;
@@ -288,39 +236,12 @@ MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
; ;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
; ;
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
; ;
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEDETECTMEDIA .SET FALSE ; IDE: PROBE FOR MEDIA IN MASTER UNIT, IF NOT DETECTED THEN DON'T ENABLE DRIVER
IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS
IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER
IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER
IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS
IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER
IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER
IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS
IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
; ;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B] PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
@@ -339,16 +260,6 @@ PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
; ;
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2)
CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS
CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK
CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK
CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS
CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK
CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK
; ;
PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
; ;
@@ -359,37 +270,14 @@ ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
; ;
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
; ;
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35]
LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR
LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR
; ;
PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM) PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM)
PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
; ;
IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM) IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM)
IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
; ;
SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM) SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM)
SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
; ;
ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
; ;
@@ -404,21 +292,14 @@ UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER
; ;
SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER
SN76489CHNOUT .SET SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT]
AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_NABU ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_NABU ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
; ;
DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
; ;
YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

2
Source/HBIOS/cfg_RC2014.asm
View File

@@ -428,7 +428,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_RCEZ80.asm
View File

@@ -450,7 +450,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET CPUOSC/4 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET CPUOSC/4 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_RCZ180.asm
View File

@@ -442,7 +442,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_RCZ280.asm
View File

@@ -441,7 +441,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_RCZ80.asm
View File

@@ -451,7 +451,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RC2014 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

30
Source/HBIOS/cfg_RPH.asm
View File

@@ -154,10 +154,8 @@ DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W]
DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
; ;
DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS
; ;
BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS
; ;
INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
; ;
@@ -218,7 +216,7 @@ UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG
; ;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS
ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
@@ -262,15 +260,8 @@ MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
; ;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .SET FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
; ;
RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER
RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
; ;
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEDETECTMEDIA .SET FALSE ; IDE: PROBE FOR MEDIA IN MASTER UNIT, IF NOT DETECTED THEN DON'T ENABLE DRIVER IDEDETECTMEDIA .SET FALSE ; IDE: PROBE FOR MEDIA IN MASTER UNIT, IF NOT DETECTED THEN DON'T ENABLE DRIVER
@@ -295,7 +286,7 @@ IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER
IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER
; ;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B] PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B]
@@ -312,12 +303,6 @@ PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER
; ;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W]
SDPPIBASE .SET RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
; ;
CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT
; ;
@@ -330,9 +315,6 @@ ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
; ;
PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR
PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR
; ;
LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
; ;
@@ -347,14 +329,8 @@ ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
SCSIENABLE .SET FALSE ; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM) SCSIENABLE .SET FALSE ; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM)
; ;
PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
PIOSBASE .SET RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
; ;
UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
UFBASE .SET $0C ; UF: REGISTERS BASE ADR
; ;
CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER
; ;
@@ -366,7 +342,7 @@ SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_SBC.asm
View File

@@ -362,7 +362,7 @@ SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_SCZ180.asm
View File

@@ -442,7 +442,7 @@ SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

2
Source/HBIOS/cfg_TEMPLATE.asm
View File

@@ -540,7 +540,7 @@ SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
; ;
AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC] AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RC2014|RCZ180|MSX|LINC|MBC|DUO|NABU|N8PC|COLECO]
AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT
; ;
SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)

1
Source/HBIOS/std.asm
View File

@@ -286,6 +286,7 @@ AYMODE_MBC .EQU 7 ; MBC SOUND BOARD
AYMODE_DUO .EQU 8 ; MBC SOUND BOARD AYMODE_DUO .EQU 8 ; MBC SOUND BOARD
AYMODE_NABU .EQU 9 ; NABU BUILT-IN SOUND AYMODE_NABU .EQU 9 ; NABU BUILT-IN SOUND
AYMODE_N8PC .EQU 10 ; N8PC BUILT-IN SOUND AYMODE_N8PC .EQU 10 ; N8PC BUILT-IN SOUND
AYMODE_COLECO .EQU 11 ; AY ON COLECOVISION-LIKE PORTS ($50/$51)
; ;
; SN SOUND CHIP MODE SELECTIONS ; SN SOUND CHIP MODE SELECTIONS
; ;