diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index 14cd2bac..871502c2 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index 29e31709..cc6cd319 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Hardware.pdf b/Doc/RomWBW Hardware.pdf index 4f854087..771867fe 100644 Binary files a/Doc/RomWBW Hardware.pdf and b/Doc/RomWBW Hardware.pdf differ diff --git a/Doc/RomWBW Introduction.pdf b/Doc/RomWBW Introduction.pdf index 2fc0ee8a..4b9b7e1b 100644 Binary files a/Doc/RomWBW Introduction.pdf and b/Doc/RomWBW Introduction.pdf differ diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf index 21d9da0a..cb6aa239 100644 Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf index 5ac9fd3f..2875fcb5 100644 Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ diff --git a/ReadMe.md b/ReadMe.md index 9abfab7f..754a29c1 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -7,7 +7,7 @@ **RomWBW Introduction** \ Version 3.6 \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ -15 Oct 2025 +22 Oct 2025 # Overview diff --git a/ReadMe.txt b/ReadMe.txt index 83ede818..380ffe7b 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -1,6 +1,6 @@ RomWBW Introduction Wayne Warthen (wwarthen@gmail.com) -15 Oct 2025 +22 Oct 2025 diff --git a/Source/Doc/Hardware.md b/Source/Doc/Hardware.md index 8b3e5fe3..fea2c1ec 100644 --- a/Source/Doc/Hardware.md +++ b/Source/Doc/Hardware.md @@ -118,9 +118,9 @@ Others | [Heath H8 Z80 System]^5^ | H8 | HEATH_std.rom | 115200 | | [MSX]^9^ | MSX | MSX_std.rom | 115200 | | [NABU w/ RomWBW Option Board]^5^ | NABU | NABU_std.rom | 115200 | -| [S100 Computers Z180 SBC]^4^ | S100 | S100_std.rom | 57600 | +| [S100 Computers Z180 SBC]^4^ | S100 | SZ180_std.rom | 57600 | | [S100 Computers Z80 CPU]^4^ | S100 | SZ80_std.rom | 9600 | -| [S100 Computers FPGA Z80 SBC]^4^ | S100 | SZ80_fpga.rom | 9600 | +| [S100 Computers T35 FPGA Z80 SBC]^4^ | S100 | SZ80_t35.rom | 9600 | | [UNA Hardware BIOS]^1^ | - | UNA_std.rom | - | | [Z80-Retro SBC]^3^ | - | Z80RETRO_std.rom | 38400 | | [Z180 Mark IV SBC]^1^ | ECB | MK4_std.rom | 38400 | @@ -461,12 +461,12 @@ Z80-based S100 Modular System ### S100 Computers FPGA Z80 SBC -An FPGA Z80 based S100 SBC +A T35 FPGA Z80 based S100 SBC * Creator: John Monahan * Website: [S100 Computers FPGA Z80 SBC](http://www.s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm) -#### ROM Image File: SZ80_fpga.rom +#### ROM Image File: SZ80_t35.rom | | | |-------------------|---------------| @@ -484,7 +484,7 @@ An FPGA Z80 based S100 SBC - DS5RTC: RTCIO=104, IO=104 - SSER: IO=52 - LPT: MODE=S100, IO=199 -- FV: IO=192, KBD MODE=FV, KBD IO=3 +- TVGA: IO=192, KBD MODE=T35, KBD IO=3 - KBD: ENABLED - SCON: IO=0 - ESPSD: IO=128, PRIMARY @@ -496,10 +496,14 @@ An FPGA Z80 based S100 SBC - PPIDE: MODE=S100A, IO=56, SLAVE - PPIDE: MODE=S100B, IO=56, MASTER - PPIDE: MODE=S100B, IO=56, SLAVE -- SD: MODE=FZ80, IO=108, UNITS=2 +- SD: MODE=T35, IO=108, UNITS=2 #### Notes: +This RomWBW build is specifically for the Trion T35 based module on the +S100 Z80 FPGA board. The Waveshare FPGA module is not supported at this +time. + - Requires matching FPGA code, see [S100 Projects RomWBW T35 Project](https://github.com/s100projects/ROMWBW_T35). `\clearpage`{=latex} @@ -1871,7 +1875,7 @@ as defined by the IEEE-696 specs. * Creator: John Monahan | * Website: [S100 Computers Z180 SBC](http://www.s100computers.com/My%20System%20Pages/Z180%20SBC/Z180%20SBC.htm) -#### ROM Image File: S100_std.rom +#### ROM Image File: SZ180_std.rom | | | |-------------------|---------------| @@ -2408,10 +2412,10 @@ the active platform and configuration. |-----------|--------------------------------------------------------| | CVDU | MC8563-based Video Display Controller | | EF | EF9345 Video Display Controller | -| FV | S100 FPGA Z80 Onboard VGA/Keyboard | +| TVGA | S100 Trion FPGA Onboard VGA/Keyboard | | GDC | uPD7220 Video Display Controller | | TMS | TMS9918/38/58 Video Display Controller | -| VDU | MC6845 Family Video Display Controller (*) | +| VDU | MC6845 Family Video Display Controller (\*) | | VGA | HD6445CP4-based Video Display Controller | | VRC | VGARC Video Display Controller | | XOSERA | XOSERA FPGA-based Video Display Controller | diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md index ef780f7e..ee156f40 100644 --- a/Source/Doc/SystemGuide.md +++ b/Source/Doc/SystemGuide.md @@ -1787,7 +1787,7 @@ below enumerates their values. | VDADEV_VGA | 0x04 | HD6445CP4-based Video Display Controller | vga.asm | | VDADEV_VRC | 0x05 | VGARC | vrc.asm | | VDADEV_EF | 0x06 | EF9345 | ef.asm | -| VDADEV_FV | 0x07 | S100 FPGA VGA | fv.asm | +| VDADEV_TVGA | 0x07 | S100 TRION FPGA VGA | tvga.asm | | VDADEV_XOSERA | 0x08 | Xosera FPGA-based Video Display Controller | xosera.asm | Depending on the capabilities of the hardware, the use of colors and @@ -2594,14 +2594,14 @@ The hardware Platform (L) is identified as follows: | PLT_MBC | 13 | NHYODYNE MULTI-BOARD COMPUTER | | PLT_RPH | 14 | RHYOPHYRE GRAPHICS SBC | | PLT_Z80RETRO | 15 | Z80 RETRO COMPUTER | -| PLT_S100 | 16 | S100 COMPUTERS Z180 | +| PLT_SZ180 | 16 | S100 COMPUTERS Z180 | | PLT_DUO | 17 | DUODYNE Z80 SYSTEM | | PLT_HEATH | 18 | HEATHKIT H8 Z80 SYSTEM | | PLT_EPITX | 19 | Z180 MINI-ITX | | PLT_MON | 20 | MONSPUTER (DEPRECATED) | | PLT_GMZ180 | 21 | GENESIS Z180 SYSTEM | | PLT_NABU | 22 | NABU PC W/ ROMWBW OPTION BOARD | -| PLT_FZ80 | 23 | S100 FPGA Z80 | +| PLT_SZ80 | 23 | S100 COMPUTERS Z80 | | PLT_RCEZ80 | 24 | RCBUS W/ eZ80 | For more information on these platforms see $doc_hardware$ diff --git a/Source/HBIOS/Build.cmd b/Source/HBIOS/Build.cmd index 77918e43..52b923dc 100644 --- a/Source/HBIOS/Build.cmd +++ b/Source/HBIOS/Build.cmd @@ -108,10 +108,10 @@ tasm -t%CPUType% -g3 -fFF -dCPM sysconf.asm sysconf.com sysconf_com.lst || exit :: Create platform specific hardware monitor -if %Platform%==S100 ( - zxcc slr180 -s100mon/fh || exit /b - zxcc mload25 -s100mon || exit /b - set HwMon=s100mon.com +if %Platform%==SZ180 ( + zxcc slr180 -sz180mon/fh || exit /b + zxcc mload25 -sz180mon || exit /b + set HwMon=sz180mon.com ) else ( call :asm hwmon || exit /b set HwMon=hwmon.bin @@ -263,14 +263,14 @@ call Build GMZ180 std || exit /b call Build DYNO std || exit /b call Build RPH std || exit /b call Build Z80RETRO std || exit /b -call Build S100 std || exit /b +call Build SZ180 std || exit /b call Build DUO std || exit /b call Build HEATH std || exit /b call Build EPITX std || exit /b :: call Build MON std || exit /b call Build NABU std || exit /b call Build SZ80 std || exit /b -call Build SZ80 fpga || exit /b +call Build SZ80 t35 || exit /b call Build UNA std || exit /b call Build MSX std || exit /b diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index ce87e7ac..ac634515 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -28,7 +28,7 @@ $ErrorAction = 'Stop' # $PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "SZ80", "RCEZ80", "MSX" -$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180" +$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "SZ180", "EPITX", "GMZ180" $PlatformListZ280 = "RCZ280" # diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh index a9f724e0..d007ae81 100755 --- a/Source/HBIOS/Build.sh +++ b/Source/HBIOS/Build.sh @@ -47,14 +47,14 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="SZ180"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh # ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="SZ80"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="SZ80"; ROM_CONFIG="fpga"; bash Build.sh + ROM_PLATFORM="SZ80"; ROM_CONFIG="t35"; bash Build.sh ROM_PLATFORM="MSX"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh exit diff --git a/Source/HBIOS/Config/S100_std.asm b/Source/HBIOS/Config/SZ180_std.asm similarity index 95% rename from Source/HBIOS/Config/S100_std.asm rename to Source/HBIOS/Config/SZ180_std.asm index 33a0a98f..10b1b999 100644 --- a/Source/HBIOS/Config/S100_std.asm +++ b/Source/HBIOS/Config/SZ180_std.asm @@ -1,6 +1,6 @@ ; ;================================================================================================== -; ROMWBW DEFAULT BUILD SETTINGS FOR S100 +; ROMWBW DEFAULT BUILD SETTINGS FOR S100 Z180 ;================================================================================================== ; ; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM @@ -45,7 +45,7 @@ #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED #DEFINE DEFSERCFG SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION ; -#INCLUDE "cfg_S100.asm" +#INCLUDE "cfg_SZ180.asm" ; BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME diff --git a/Source/HBIOS/Config/SZ80_fpga.asm b/Source/HBIOS/Config/SZ80_t35.asm similarity index 94% rename from Source/HBIOS/Config/SZ80_fpga.asm rename to Source/HBIOS/Config/SZ80_t35.asm index f89c02d8..88cf1bf6 100644 --- a/Source/HBIOS/Config/SZ80_fpga.asm +++ b/Source/HBIOS/Config/SZ80_t35.asm @@ -1,6 +1,6 @@ ; ;================================================================================================== -; ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80 +; ROMWBW DEFAULT BUILD SETTINGS FOR S100 T35 FPGA Z80 ;================================================================================================== ; ; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM @@ -62,7 +62,7 @@ TSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) ; LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) ; -FVENABLE .SET TRUE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET TRUE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) ; diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile index 181cb0b2..a8ff13db 100644 --- a/Source/HBIOS/Makefile +++ b/Source/HBIOS/Makefile @@ -43,7 +43,7 @@ else endif ifeq ($(ROM_PLATFORM),S100) - HWMON=s100mon.bin + HWMON=sz180mon.bin else HWMON=hwmon.bin endif @@ -108,9 +108,9 @@ sysconf.com: @$(TASM) -dCPM sysconf.asm sysconf.com sysconf_com.lst cp $@ $(DEST)/Apps -s100mon.bin: - $(ZXCC) $(CPM)/SLR180 -s100mon/FH - $(ZXCC) $(CPM)/MLOAD25 -s100mon.bin=s100mon +sz180mon.bin: + $(ZXCC) $(CPM)/SLR180 -sz180mon/FH + $(ZXCC) $(CPM)/MLOAD25 -sz180mon.bin=sz180mon tastybasic.bin: cp ../TastyBasic/src/$@ . @@ -139,7 +139,7 @@ eastaegg.bin: build.inc updater.bin: build.inc romfonts.bin: build.inc hwmon.bin: build.inc -s100mon.bin: build.inc +sz180mon.bin: build.inc dumps: for i in $(MOREDIFF) ; do \ diff --git a/Source/HBIOS/Makefile.new b/Source/HBIOS/Makefile.new index 38ab8fef..b9f98a94 100644 --- a/Source/HBIOS/Makefile.new +++ b/Source/HBIOS/Makefile.new @@ -45,9 +45,9 @@ camel80.bin: tastybasic.bin: cp ../TastyBasic/src/$@ . -s100mon.bin: - $(ZXCC) $(CPM)/SLR180 -s100mon/FH - $(ZXCC) $(CPM)/MLOAD25 -s100mon.bin=s100mon +sz180mon.bin: + $(ZXCC) $(CPM)/SLR180 -sz180mon/FH + $(ZXCC) $(CPM)/MLOAD25 -sz180mon.bin=sz180mon %.build.inc: echo $@ @@ -117,7 +117,7 @@ DUO_%.osimg1.bin: NETBOOT=netboot-duo.mod cat camel80.bin $(*F).nascom.bin tastybasic.bin $(*F).game.bin $(*F).eastaegg.bin $(NETBOOT) $(*F).updater.bin $(*F).sysconf.bin $(*F).usrrom.bin >$@ srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary -S100_%.imgpad2.bin: s100mon.bin +S100_%.imgpad2.bin: sz180mon.bin cp $< $@ srec_cat $@ -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $@ -Binary diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm index 4913352f..642ef42b 100644 --- a/Source/HBIOS/cfg_DUO.asm +++ b/Source/HBIOS/cfg_DUO.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -246,7 +246,7 @@ VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -337,7 +337,7 @@ PIO0BASE .SET $68 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $6C ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $48 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm index 53d39dc3..83e5f6b4 100644 --- a/Source/HBIOS/cfg_DYNO.asm +++ b/Source/HBIOS/cfg_DYNO.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -261,7 +261,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm index cfe38175..cc0d9795 100644 --- a/Source/HBIOS/cfg_EPITX.asm +++ b/Source/HBIOS/cfg_EPITX.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -257,7 +257,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -347,7 +347,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm index a95ea208..e64f1e78 100644 --- a/Source/HBIOS/cfg_EZZ80.asm +++ b/Source/HBIOS/cfg_EZZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -266,7 +266,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -356,7 +356,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm index 7b336e5f..5f054879 100644 --- a/Source/HBIOS/cfg_GMZ180.asm +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -256,7 +256,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -346,7 +346,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index 8dd3817f..5e10cbd8 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -266,7 +266,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -346,7 +346,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm index b7746c9c..cc604c16 100644 --- a/Source/HBIOS/cfg_MASTER.asm +++ b/Source/HBIOS/cfg_MASTER.asm @@ -49,7 +49,7 @@ ; #INCLUDE "hbios.inc" ; -PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .EQU FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .EQU BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -321,7 +321,7 @@ VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .EQU FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) XOSENABLE .EQU FALSE ; XOSERA: ENABLE XOSERA VIDEO DRIVERS (XOSERA.ASM) XOS_BASE .EQU $20 ; XOSERA: I/O BASE ADDRESS (REQUIRES 32 BYTES) XOSSIZ .EQU V80X30 ; XOSERA: DISPLAY FORMAT [V80X30|V80X60] @@ -425,7 +425,7 @@ PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .EQU LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm index c259f791..c94574ed 100644 --- a/Source/HBIOS/cfg_MBC.asm +++ b/Source/HBIOS/cfg_MBC.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -239,7 +239,7 @@ VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -325,7 +325,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $E8 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm index e008dd1e..b1c424d7 100644 --- a/Source/HBIOS/cfg_MK4.asm +++ b/Source/HBIOS/cfg_MK4.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -250,7 +250,7 @@ VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm index 6056acc7..989fdecc 100644 --- a/Source/HBIOS/cfg_MON.asm +++ b/Source/HBIOS/cfg_MON.asm @@ -51,7 +51,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -263,7 +263,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -353,7 +353,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_MSX.asm b/Source/HBIOS/cfg_MSX.asm index 2daf181c..dc318ce8 100644 --- a/Source/HBIOS/cfg_MSX.asm +++ b/Source/HBIOS/cfg_MSX.asm @@ -269,7 +269,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET FALSE ; MD: ENABLE ROM DISK @@ -360,7 +360,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $90 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm index 8398e44e..3ffd3862 100644 --- a/Source/HBIOS/cfg_N8.asm +++ b/Source/HBIOS/cfg_N8.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -252,7 +252,7 @@ VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm index 23de765e..21262f6c 100644 --- a/Source/HBIOS/cfg_NABU.asm +++ b/Source/HBIOS/cfg_NABU.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -266,7 +266,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -356,7 +356,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm index 5211516d..57bff2e3 100644 --- a/Source/HBIOS/cfg_RCEZ80.asm +++ b/Source/HBIOS/cfg_RCEZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_RCEZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_EZ80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -264,7 +264,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -357,7 +357,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index ca339bcb..bc8080d7 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -261,7 +261,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -354,7 +354,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index b94b9a09..c92426c7 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -271,7 +271,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -364,7 +364,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm index a379d3ca..dcdc2d4c 100644 --- a/Source/HBIOS/cfg_RCZ80.asm +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -269,7 +269,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -359,7 +359,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm index bc024045..d90cd71a 100644 --- a/Source/HBIOS/cfg_RPH.asm +++ b/Source/HBIOS/cfg_RPH.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -240,7 +240,7 @@ VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm index 1ad50a8e..ea5ab104 100644 --- a/Source/HBIOS/cfg_SBC.asm +++ b/Source/HBIOS/cfg_SBC.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -240,7 +240,7 @@ VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm index 96b55a13..a6807315 100644 --- a/Source/HBIOS/cfg_SCZ180.asm +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -261,7 +261,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -351,7 +351,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_SZ180.asm similarity index 96% rename from Source/HBIOS/cfg_S100.asm rename to Source/HBIOS/cfg_SZ180.asm index 58279f07..c39bfa03 100644 --- a/Source/HBIOS/cfg_S100.asm +++ b/Source/HBIOS/cfg_SZ180.asm @@ -1,6 +1,6 @@ ; ;================================================================================================== -; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100 +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100 Z180 ;================================================================================================== ; ; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_SZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -261,7 +261,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK @@ -341,7 +341,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm index 2bdc2d78..b94bc4ca 100644 --- a/Source/HBIOS/cfg_SZ80.asm +++ b/Source/HBIOS/cfg_SZ80.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_SZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_SZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -266,7 +266,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET FALSE ; MD: ENABLE ROM DISK @@ -356,7 +356,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_S100 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTMODE .SET LPTMODE_T35 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $C7 ; LPT 0: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm index d9816680..ec3b8ded 100644 --- a/Source/HBIOS/cfg_Z80RETRO.asm +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -241,7 +241,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm index ca9ef5b5..8a472c66 100644 --- a/Source/HBIOS/cfg_ZETA.asm +++ b/Source/HBIOS/cfg_ZETA.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -210,7 +210,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm index adbed3da..85a0d067 100644 --- a/Source/HBIOS/cfg_ZETA2.asm +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -49,7 +49,7 @@ ; #INCLUDE "cfg_MASTER.asm" ; -PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] +PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80] CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] @@ -221,7 +221,7 @@ VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .SET TRUE ; MD: ENABLE ROM DISK diff --git a/Source/HBIOS/espsd.asm b/Source/HBIOS/espsd.asm index c8fe3b5f..5fef9aa7 100644 --- a/Source/HBIOS/espsd.asm +++ b/Source/HBIOS/espsd.asm @@ -712,8 +712,8 @@ ESPSD_BLKREAD2: ; READ BYTES FAST (NO TIMEOUT CHECK) DEC C ; BACK TO STATUS PORT ESPSD_BLKREAD2A: -#IF (PLATFORM == PLT_S100) - IN A,(C) ; EXTRA READ FOR S100 STABILITY +#IF (PLATFORM == PLT_SZ180) + IN A,(C) ; EXTRA READ FOR Z180 STABILITY #ENDIF IN A,(C) ; GET STATUS JP P,ESPSD_BLKREAD2A ; LOOP TILL DATA READY @@ -766,8 +766,8 @@ ESPSD_BLKWRITE2: ; WRITE BYTES FAST (NO TIMEOUT CHECK) DEC C ; BACK TO STATUS PORT ESPSD_BLKWRITE2A: -#IF (PLATFORM == PLT_S100) - IN A,(C) ; EXTRA READ FOR S100 STABILITY +#IF (PLATFORM == PLT_SZ180) + IN A,(C) ; EXTRA READ FOR Z180 STABILITY #ENDIF IN A,(C) ; GET STATUS RRA ; SEND RDY BIT TO CF @@ -811,8 +811,8 @@ ESPSD_PUTBYTE: LD B,0 LD C,(IY+ESPSD_IOBASE) ESPSD_PUTBYTE1: -#IF (PLATFORM == PLT_S100) - IN A,(C) ; EXTRA READ FOR S100 STABILITY +#IF (PLATFORM == PLT_SZ180) + IN A,(C) ; EXTRA READ FOR Z180 STABILITY #ENDIF IN A,(C) BIT 0,A @@ -867,8 +867,8 @@ ESPSD_GETBYTE: LD B,0 LD C,(IY+ESPSD_IOBASE) ESPSD_GETBYTE1: -#IF (PLATFORM == PLT_S100) - IN A,(C) ; EXTRA READ FOR S100 STABILITY +#IF (PLATFORM == PLT_SZ180) + IN A,(C) ; EXTRA READ FOR Z180 STABILITY #ENDIF IN A,(C) JP M,ESPSD_GETBYTE2 diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index f9286cca..ff750ad0 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -2017,23 +2017,23 @@ RAMSEG .EQU ((ROMSIZE + RAMSIZE) / 16) - 2 + (RAMBIAS * 2) ; S100 MONITOR LAUNCH ;-------------------------------------------------------------------------------------------------- ; -; S100 ROM CONTAINS A HARDWARE LEVEL MONITOR IN BANK ID 3 OF ROM. +; S100 Z180 ROM CONTAINS A HARDWARE LEVEL MONITOR IN BANK ID 3 OF ROM. ; IF PORT $75 BIT 1 IS SET (SET IS ZERO), THEN WE IMMEDIATELY ; TRANSITION TO THIS MONITOR. PRIOR TO THE TRANSITION, WE ALSO ; CHECK THE VALUE IN THE Z180 RELOAD REGISTER LOW. IF IT IS ASCII 'W', ; THEN IT MEANS THE S100 MONITOR IS ATTEMPTING TO REBOOT INTO ROMWBW ; HBIOS AND WE ABORT THE TRANSITION TO THE S100 MONITOR. ; -#IF ((PLATFORM == PLT_S100) & TRUE) +#IF ((PLATFORM == PLT_SZ180) & TRUE) ; CHECK S100 BOARD DIP SWITCH, BIT 1 IN A,($75) ; READ SWITCHES BIT 1,A ; CHECK BIT 1 - JR NZ,S100MON_SKIP ; IF NOT SET, CONT ROMWBW BOOT + JR NZ,SZ180MON_SKIP ; IF NOT SET, CONT ROMWBW BOOT ; ; CHECK RELOAD REGISTER LOW FOR SPECIAL VALUE IN0 A,(Z180_RLDR1L) ; GET RELOAD REG 1 LOW CP 'W' ; CHECK FOR SPECIAL VALUE - JR Z,S100MON_SKIP ; IF SO, DO ROMWBW BOOT + JR Z,SZ180MON_SKIP ; IF SO, DO ROMWBW BOOT ; ; LAUNCH S100 MONITOR FROM ROM BANK 3 LD A,BID_IMG2 ; S100 MONITOR BANK @@ -2041,7 +2041,7 @@ RAMSEG .EQU ((ROMSIZE + RAMSIZE) / 16) - 2 + (RAMBIAS * 2) CALL HBX_BNKCALL ; CONTINUE IN RAM BANK, DO NOT RETURN JR $ ; HALT WE SHOULD NOT COME BACK HERE! ; -S100MON_SKIP: +SZ180MON_SKIP: ; RESTORE DEFAULT RELOAD REGISTER VALUE (PROBABLY NOT NEEDED) XOR A OUT0 (Z180_RLDR1L),A @@ -3014,7 +3014,7 @@ HB_CONRDY: ; IS NO CRT DEVICE. ; ; -#IF ((PLATFORM == PLT_S100) & SCONENABLE) +#IF ((PLATFORM == PLT_SZ180) & SCONENABLE) IN A,($75) ; GET IO BYTE AND %00000001 ; ISOLATE CONSOLE BIT JR NZ,HB_CONRDY_Z ; NOT SET, BYPASS CONSOLE SWITCH @@ -3746,13 +3746,13 @@ HB_CRTACT: ; #ENDIF ; -#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_Z2) & FVENABLE) +#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_Z2) & TVGAENABLE) ; IOBYTE: XXXXXVVC - ; 00- FORCE ONBOARD VGA/PS2 KBD (FV) + ; 00- FORCE ONBOARD VGA/PS2 KBD (T35) ; --1 FORCE PROPELLER CONSOLE (SCON) ; 110 NORMAL USB SERIAL BOOT ; - ;;;; WE ASSUME THAT THE ONBOARD VGA (FV) IS ALWAYS DETECTED AND + ;;;; WE ASSUME THAT THE ONBOARD VGA (TVGA) IS ALWAYS DETECTED AND ;;;; WILL BE THE CURRENT CRTDEV. SCON IS ASSUMED TO BE THE ;;;; DEVICE AT CRTDEV + 1. THESE ARE REASONABLE ASSUMPTIONS ;;;; UNLESS THE DRIVER DETECTION OR DRIVER ORDER IS CHANGED. @@ -3763,14 +3763,14 @@ HB_CRTACT: ;;;AND %00000001 ; ISOLATE BIT ;;;JR Z,INITSYS3 ; NORMAL USB SERIAL BOOT ;;;LD A,(CB_CRTDEV) ; GET CRT DEV - ;;;INC A ; SWITCH FROM FV -> SCON + ;;;INC A ; SWITCH FROM TVGA -> SCON ;;;LD (CB_CRTDEV),A ; SAVE IT AND DO CONSOLE SWITCH ; IF ONBOARD VGA/PS2 KBD IS REQUESTED, SETUP FOR CONSOLE SWITCH IN A,($36) ; GET IO BYTE AND %00000110 ; ISOLATE BITS JR NZ,INITSYS3 ; BIT(S) NOT ZERO, BYPASS SWITCH - LD A,(FV_UNIT) ; GET FV UNIT NUMBER + LD A,(TVGA_UNIT) ; GET TVGA UNIT NUMBER CP $FF ; IS HARDWARE THERE? JR Z,INITSYS3 ; IF NOT, BYPASS SWITCH LD (HB_NEWCON),A ; ELSE QUEUE TO SWITCH @@ -4292,8 +4292,8 @@ HB_INITTBL: #IF (VRCENABLE) .DW VRC_INIT #ENDIF -#IF (FVENABLE) - .DW FV_INIT +#IF (TVGAENABLE) + .DW TVGA_INIT #ENDIF #IF (SCONENABLE) .DW SCON_INIT @@ -9061,12 +9061,12 @@ SIZ_VRC .EQU $ - ORG_VRC MEMECHO " bytes.\n" #ENDIF ; -#IF (FVENABLE) -ORG_FV .EQU $ - #INCLUDE "fv.asm" -SIZ_FV .EQU $ - ORG_FV - MEMECHO "FV occupies " - MEMECHO SIZ_FV +#IF (TVGAENABLE) +ORG_TVGA .EQU $ + #INCLUDE "tvga.asm" +SIZ_TVGA .EQU $ - ORG_TVGA + MEMECHO "TVGA occupies " + MEMECHO SIZ_TVGA MEMECHO " bytes.\n" #ENDIF ; diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index 4170e291..b139e3fd 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -200,14 +200,14 @@ PLT_RCZ280 .EQU 12 ; RCBUS W/ Z280 PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER PLT_RPH .EQU 14 ; RHYOPHYRE GRAPHICS COMPUTER PLT_Z80RETRO .EQU 15 ; Z80 RETRO COMPUTER -PLT_S100 .EQU 16 ; S100 COMPUTERS Z180 SYSTEM +PLT_SZ180 .EQU 16 ; S100 COMPUTERS Z180 SYSTEM PLT_DUO .EQU 17 ; DUODYNE Z80 SYSTEM PLT_HEATH .EQU 18 ; HEATHKIT H8 Z80 SYSTEM PLT_EPITX .EQU 19 ; Z180 MINI-ITX PLT_MON .EQU 20 ; MONSPUTER (DEPRECATED) PLT_GMZ180 .EQU 21 ; GENESIS Z180 SYSTEM PLT_NABU .EQU 22 ; NABU PC W/ ROMWBW OPTION BOARD -PLT_SZ80 .EQU 23 ; S100 Z80 +PLT_SZ80 .EQU 23 ; S100 COMPUTERS Z80 SYSTEM PLT_RCEZ80 .EQU 24 ; RCBUS W/ eZ80 PLT_MSX .EQU 25 ; MSX COMPUTER ; @@ -455,7 +455,7 @@ VDADEV_TMS .EQU $03 ; N8 ONBOARD VDA SUBSYSTEM - TMS 9918 VDADEV_VGA .EQU $04 ; ECB VGA3 - HITACHI HD6445 VDADEV_VRC .EQU $05 ; VGARC VDADEV_EF .EQU $06 ; EF9345 -VDADEV_FV .EQU $07 ; S100 FPGA VGA +VDADEV_TVGA .EQU $07 ; S100 TRION FPGA VGA VDADEV_XOSERA .EQU $08 ; XOSERA RCBUS ; ; SOUND DEVICE IDS diff --git a/Source/HBIOS/kbd.asm b/Source/HBIOS/kbd.asm index 94fbd93b..3d4fd345 100644 --- a/Source/HBIOS/kbd.asm +++ b/Source/HBIOS/kbd.asm @@ -153,7 +153,7 @@ KBD_INIT: LD A,(IY+KBD_MODE) ; GET KBD MODE BYTE CP KBDMODE_VRC ; VRC? JR Z,KBD_INIT1 ; IF SO, MUST ASSUME PRESENT - CP KBDMODE_FV ; FV? + CP KBDMODE_T35 ; S100 T35 FPGA? JR Z,KBD_INIT1 ; IF SO, MUST ASSUME PRESENT ; ; HB_DI ; DISABLE INTERRUPTS WHILE WE PROBE @@ -182,15 +182,15 @@ KBD_INIT1: LD DE,KBD_STR_MODEVRC CP KBDMODE_VRC JR Z,KBD_INIT2 - LD DE,KBD_STR_MODEFV - CP KBDMODE_FV + LD DE,KBD_STR_MODET35 + CP KBDMODE_T35 JR Z,KBD_INIT2 LD DE,KBD_STR_MODEUNK KBD_INIT2: CALL WRITESTR ; LD A,(IY+KBD_MODE) ; GET MODE VALUE - CP KBDMODE_FV ; FV KEYBOARD? + CP KBDMODE_T35 ; S100 T35 FPGA KEYBOARD? RET Z ; IF SO, CANNOT SEND, RET FROM INIT ; LD A,KBD_CON_WCR ; SET COMMAND REGISTER @@ -812,7 +812,7 @@ KBD_DECNEW: ; START NEW KEYPRESS (CLEAR ALL STATUS BITS) ; KBD_STR_MODEPS2 .TEXT "PS2$" KBD_STR_MODEVRC .TEXT "VRC$" -KBD_STR_MODEFV .TEXT "FV$" +KBD_STR_MODET35 .TEXT "T35$" KBD_STR_MODEUNK .TEXT "???$" ; #IF ((INTMODE == 2) & KBDINTS) diff --git a/Source/HBIOS/lpt.asm b/Source/HBIOS/lpt.asm index 795a28ac..efa3b658 100644 --- a/Source/HBIOS/lpt.asm +++ b/Source/HBIOS/lpt.asm @@ -62,8 +62,8 @@ ; ;================================================================================================== ; -; S100 STYLE INTERFACE: -; - S100 FPGA Z80 +; S100 T35 STYLE INTERFACE: +; - S100 T35 FPGA Z80 ; ; DATA (BASE PORT + 0, OUTPUT): ; @@ -184,14 +184,14 @@ LPT_OUT: #IF (LPTMODE == LPTMODE_MG014) LD A,%00000100 ; SELECT & STROBE, LED OFF #ENDIF -#IF (LPTMODE == LPTMODE_S100) +#IF (LPTMODE == LPTMODE_T35) LD A,%00000000 ; STROBE #ENDIF #IF ((LPTMODE == LPTMODE_SPP) | (LPTMODE == LPTMODE_MG014)) INC C ; PUT CONTROL PORT IN C INC C #ENDIF -#IF (LPTMODE == LPTMODE_S100) +#IF (LPTMODE == LPTMODE_T35) DEC C ; PUT CONTROL PORT IN C #ENDIF EZ80_IO @@ -205,7 +205,7 @@ LPT_OUT: #IF (LPTMODE == LPTMODE_MG014) LD A,%00000101 ; SELECT, LED OFF #ENDIF -#IF (LPTMODE == LPTMODE_S100) +#IF (LPTMODE == LPTMODE_T35) LD A,%11111111 ; CLEAR STROBE #ENDIF EZ80_IO @@ -235,7 +235,7 @@ LPT_OST: #IF (LPTMODE == LPTMODE_SPP) AND %10000000 ; ISOLATE /BUSY #ENDIF -#IF ((LPTMODE == LPTMODE_MG014) | (LPTMODE == LPTMODE_S100)) +#IF ((LPTMODE == LPTMODE_MG014) | (LPTMODE == LPTMODE_T35)) AND %00000010 ; ISOLATE BUSY XOR %00000010 ; INVERT TO READY #ENDIF @@ -295,7 +295,7 @@ LPT_INITDEV0: RET ; RETURN #ENDIF ; -#IF (LPTMODE == LPTMODE_S100) +#IF (LPTMODE == LPTMODE_T35) LD C,(IY+3) ; BASE PORT DEC C ; DEC TO CONTROL PORT LD A,$FF ; INIT VALUE @@ -401,7 +401,7 @@ LPT_DETECT: RET ; ZF SET IF DETECTED #ENDIF ; -#IF (LPTMODE == LPTMODE_S100) +#IF (LPTMODE == LPTMODE_T35) LPT_DETECT: ; PORT ALWAYS EXISTS ON FPGA XOR A ; SIGNAL SUCCESS @@ -447,12 +447,12 @@ LPT_TYPE_MAP: .DW LPT_STR_NONE .DW LPT_STR_SPP .DW LPT_STR_MG014 - .DW LPT_STR_S100 + .DW LPT_STR_T35 ; LPT_STR_NONE .DB "???$" LPT_STR_SPP .DB "SPP$" LPT_STR_MG014 .DB "MG014$" -LPT_STR_S100 .DB "S100$" +LPT_STR_T35 .DB "T35$" ; LPT_STR_NOLPT .DB "NOT PRESENT$" ; @@ -479,8 +479,8 @@ LPT0_CFG: #IF (LPTMODE == LPTMODE_MG014) DEVECHO "MG014" #ENDIF - #IF (LPTMODE == LPTMODE_S100) - DEVECHO "S100" + #IF (LPTMODE == LPTMODE_T35) + DEVECHO "T35" #ENDIF DEVECHO ", IO=" DEVECHO LPT0BASE @@ -505,8 +505,8 @@ LPT1_CFG: #IF (LPTMODE == LPTMODE_MG014) DEVECHO "MG014" #ENDIF - #IF (LPTMODE == LPTMODE_S100) - DEVECHO "S100" + #IF (LPTMODE == LPTMODE_T35) + DEVECHO "T35" #ENDIF DEVECHO ", IO=" DEVECHO LPT1BASE diff --git a/Source/HBIOS/plt_pretty.inc b/Source/HBIOS/plt_pretty.inc index 664a81ce..d0514df2 100644 --- a/Source/HBIOS/plt_pretty.inc +++ b/Source/HBIOS/plt_pretty.inc @@ -135,7 +135,7 @@ STR_PLT_PRETTY: .DB " / / / _ \\ | () | | / | _| | | | / | (_) |",10,13 .DB "/___| \\___/ \\__/ |_|_\\ |___| |_| |_|_\\ \\___/",10,13 #ENDIF -#IF (PLATFORM == PLT_S100) +#IF (PLATFORM == PLT_SZ180) .DB " ___ _ __ __ ____ _ ___ __",10,13 .DB "/ __| / | / \\ / \\ |_ / / | ( _ ) / \\ ",10,13 .DB "\\__ \\ | | | () | | () | / / | | / _ \\ | () |",10,13 diff --git a/Source/HBIOS/romldr.asm b/Source/HBIOS/romldr.asm index a9462053..b309eef9 100644 --- a/Source/HBIOS/romldr.asm +++ b/Source/HBIOS/romldr.asm @@ -1120,15 +1120,16 @@ romload: ld c,DSKY_MSG_LDR_LOAD ; point to load message call dsky_msg ; display message ; + call pdot ; show progress call romcopy ; Copy ROM App into working memory - ld a,'.' ; dot character - call cout ; show progress + call pdot ; show progress ; ld c,DSKY_MSG_LDR_GO ; point to go message call dsky_msg ; display message ; ld l,(ix+ra_ent) ; HL := app entry address ld h,(ix+ra_ent+1) ; ... + call pdot ; show progress jp (hl) ; go ; ;======================================================================= @@ -1601,18 +1602,18 @@ diskread: ; This bit of code just launches the monitor directly from that bank. ; #if (BIOS == BIOS_WBW) - #if (PLATFORM == PLT_S100) + #if (PLATFORM == PLT_SZ180) ; -s100mon: +sz180mon: ; Warn user that console is being directed to the S100 bus ; if the IOBYTE bit 0 is 0 (%xxxxxxx0). in a,($75) ; get IO byte and %00000001 ; isolate console bit - jr nz,s100mon1 ; if 0, bypass msg + jr nz,sz180mon1 ; if 0, bypass msg ld hl,str_s100con ; console msg string call pstr ; display it ; -s100mon1: +sz180mon1: ; Launch S100 Monitor from ROM Bank 3 call ldelay ; wait for UART buf to empty di ; suspend interrupts @@ -2720,8 +2721,8 @@ ra_tbl: ra_ent(str_mon, 'M', KY_CL, MON_BNK, MON_IMGLOC, MON_LOC, MON_SIZ, MON_SERIAL) ra_entsiz .equ $ - ra_tbl #if (BIOS == BIOS_WBW) - #if (PLATFORM == PLT_S100) -ra_ent(str_smon, 'O', $FF, bid_cur, $8000, $8000, $0001, s100mon) + #if (PLATFORM == PLT_SZ180) +ra_ent(str_smon, 'O', $FF, bid_cur, $8000, $8000, $0001, sz180mon) #endif #endif ra_ent(str_cpm22, 'C', KY_BK, CPM22_BNK, CPM22_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT) diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index d6ef4a49..a06977df 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -17,14 +17,14 @@ ; 13. MBC Andrew Lynch's Multi Board Computer ; 14. RPH Andrew Lynch's RHYOPHYRE Graphics Computer ; 15. Z80RETRO Peter Wilson's Z80-Retro Computer -; 16. S100 S100 Computers Z180-based System +; 16. SZ180 S100 Computers Z180-based System ; 17. DUO Andrew Lynch's Duodyne Computer ; 18. HEATH Les Bird's Heath Z80 Board ; 19. EPITX Alan Cox' Mini-ITX System ; 20. MON Jacques Pelletier's Monsputer (deprecated) ; 21. GMZ180 Doug Jacksons' Genesis Z180 System ; 22. NABU NABU w/ Les Bird's RomWBW Option Board -; 23. SZ80 S100 Computers Z80 +; 23. SZ80 S100 Computers Z80-based System ; 24. RCEZ80 RCBus eZ80 ; 25. MSX MSX Computers ; @@ -245,7 +245,7 @@ SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE) SDMODE_PIO .EQU 11 ; Z80 PIO bitbang SDMODE_Z80R .EQU 12 ; Z80 Retro SDMODE_EPITX .EQU 13 ; Mini ITX Z180 -SDMODE_T35 .EQU 14 ; S100 FPGA Z80 +SDMODE_T35 .EQU 14 ; S100 TRION T35 FPGA Z80 SDMODE_GM .EQU 15 ; Genesis SD Driver SDMODE_EZ512 .EQU 16 ; EZ512 SD SDMODE_K80W .EQU 17 ; K80W SD @@ -313,7 +313,7 @@ GDCMODE_RPH .EQU 2 ; RPH GDC LPTMODE_NONE .EQU 0 ; NONE LPTMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP) LPTMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE -LPTMODE_S100 .EQU 3 ; S100 Z80 FPGA BUILT-IN PRINTER PORT +LPTMODE_T35 .EQU 3 ; S100 Z80 TRION T35 FPGA BUILT-IN PRINTER PORT ; ; PPA DRIVER MODE SELECTIONS ; @@ -370,7 +370,7 @@ DMAMODE_VDG .EQU 7 ; VELESOFT DATAGEAR KBDMODE_NONE .EQU 0 KBDMODE_PS2 .EQU 1 ; PS/2 KEYBOARD CONTROLLER KBDMODE_VRC .EQU 2 ; VGARC KEYBOARD CONTROLLER -KBDMODE_FV .EQU 3 ; FPGA VGA KEYBOARD CONTROLLER +KBDMODE_T35 .EQU 3 ; S100 T35 FPGA KEYBOARD CONTROLLER ; ; SERIAL DEVICE CONFIGURATION CONSTANTS ; @@ -542,7 +542,6 @@ KBDENABLE .EQU FALSE ; PS/2 KEYBOARD DRIVER PPKENABLE .EQU FALSE ; PPK KEYBOARD DRIVER MKYENABLE .EQU FALSE ; MSX KEYBOARD DRIVER NABUKBENABLE .EQU FALSE ; NABU KEYBOARD DRIVER -FVKBDENABLE .EQU FALSE ; FPGA KEYBOARD DRIVER USBKYBENABLE .EQU FALSE ; USB KEYBOARD DRIVER ; ; VIDEO MODES diff --git a/Source/HBIOS/s100mon.z80 b/Source/HBIOS/sz180mon.z80 similarity index 100% rename from Source/HBIOS/s100mon.z80 rename to Source/HBIOS/sz180mon.z80 diff --git a/Source/HBIOS/tser.asm b/Source/HBIOS/tser.asm index 1313580c..1d6eec68 100644 --- a/Source/HBIOS/tser.asm +++ b/Source/HBIOS/tser.asm @@ -1,9 +1,9 @@ ; ;================================================================================================== -; S100 Z80 FPGA T35 SERIAL DRIVER +; S100 TRION SERIAL DRIVER ;================================================================================================== ; -; THIS SERIAL DRIVER SUPPORTS THE SERIAL INTERFACE OF THE T35 FPGA. +; THIS SERIAL DRIVER SUPPORTS THE SERIAL INTERFACE OF THE TRION FPGA. ; ; TODO: ; diff --git a/Source/HBIOS/fv.asm b/Source/HBIOS/tvga.asm similarity index 58% rename from Source/HBIOS/fv.asm rename to Source/HBIOS/tvga.asm index d045350d..99413cf6 100644 --- a/Source/HBIOS/fv.asm +++ b/Source/HBIOS/tvga.asm @@ -1,11 +1,11 @@ ;====================================================================== -; VIDEO DRIVER FOR FPGA VGA +; VIDEO DRIVER FOR TRION VGA ; http://s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm ; ; WRITTEN BY: WAYNE WARTHEN -- 9/2/2024 ;====================================================================== ; -; FPGA VGA EXPOSES A FRAME BUFFER STARTING AT $E000. +; TRION VGA EXPOSES A FRAME BUFFER STARTING AT $E000. ; PORT $08 CONTROLS ACCESS TO THE FRAME BUFFER. ; - WHEN $01, FRAME BUFFER APPEARS AT $E000 IN CPU ADDRESS SPACE ; - WHEN $00, FRAME BUFFER IS INACCESSIBLE BY CPU @@ -25,226 +25,226 @@ ; TODO: ; ;====================================================================== -; FPGA VGA DRIVER - CONSTANTS +; TRION VGA DRIVER - CONSTANTS ;====================================================================== ; -FV_FBUF .EQU $E000 ; ADDRESS OF FRAME BUFFER -FV_BASE .EQU $C0 ; BASE I/O ADDRESS -FV_CCOL .EQU FV_BASE+0 ; CUR COL PORT -FV_CROW .EQU FV_BASE+1 ; CUR ROW PORT -FV_CTL .EQU FV_BASE+2 ; VGA CONTROL PORT +TVGA_FBUF .EQU $E000 ; ADDRESS OF FRAME BUFFER +TVGA_BASE .EQU $C0 ; BASE I/O ADDRESS +TVGA_CCOL .EQU TVGA_BASE+0 ; CUR COL PORT +TVGA_CROW .EQU TVGA_BASE+1 ; CUR ROW PORT +TVGA_CTL .EQU TVGA_BASE+2 ; VGA CONTROL PORT ; -FV_BUFCTL .EQU $08 +TVGA_BUFCTL .EQU $08 ; -FV_KBDDATA .EQU $03 ; KBD CTLR DATA PORT -FV_KBDST .EQU $02 ; KBD CTLR STATUS/CMD PORT +TVGA_KBDDATA .EQU $03 ; KBD CTLR DATA PORT +TVGA_KBDST .EQU $02 ; KBD CTLR STATUS/CMD PORT ; -FV_ROWS .EQU 40 -FV_COLS .EQU 80 +TVGA_ROWS .EQU 40 +TVGA_COLS .EQU 80 ; TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER KBDENABLE .SET TRUE ; INCLUDE KBD KEYBOARD SUPPORT ; - DEVECHO "FV: IO=" - DEVECHO FV_BASE - DEVECHO ", KBD MODE=FV" + DEVECHO "TVGA: IO=" + DEVECHO TVGA_BASE + DEVECHO ", KBD MODE=T35" DEVECHO ", KBD IO=" - DEVECHO FV_KBDDATA + DEVECHO TVGA_KBDDATA DEVECHO "\n" ; ;====================================================================== -; FPGA VGA DRIVER - INITIALIZATION +; TRION VGA DRIVER - INITIALIZATION ;====================================================================== ; -FV_INIT: - LD IY,FV_IDAT ; POINTER TO INSTANCE DATA +TVGA_INIT: + LD IY,TVGA_IDAT ; POINTER TO INSTANCE DATA ; OR $FF ; CLEAR THE - LD (FV_UNIT),A ; ... UNIT NUMBER + LD (TVGA_UNIT),A ; ... UNIT NUMBER ; CALL NEWLINE ; FORMATTING - PRTS("FV: IO=0x$") - LD A,FV_BASE + PRTS("TVGA: IO=0x$") + LD A,TVGA_BASE CALL PRTHEXBYTE - CALL FV_PROBE ; CHECK FOR HW PRESENCE - JR Z,FV_INIT1 ; CONTINUE IF HW PRESENT + CALL TVGA_PROBE ; CHECK FOR HW PRESENCE + JR Z,TVGA_INIT1 ; CONTINUE IF HW PRESENT ; ; HARDWARE NOT PRESENT PRTS(" NOT PRESENT$") OR $FF ; SIGNAL FAILURE RET ; -FV_INIT1: +TVGA_INIT1: ;;; ; RECORD DRIVER ACTIVE ;;; OR $FF -;;; LD (FV_ACTIVE),A +;;; LD (TVGA_ACTIVE),A ; DISPLAY CONSOLE DIMENSIONS - LD A,FV_COLS + LD A,TVGA_COLS CALL PC_SPACE CALL PRTDECB LD A,'X' CALL COUT - LD A,FV_ROWS + LD A,TVGA_ROWS CALL PRTDECB PRTS(" TEXT$") ; HARDWARE INITIALIZATION - CALL FV_CRTINIT ; SETUP THE FPGA VGA CHIP REGISTERS - CALL FV_VDAINI ; INITIALIZE + CALL TVGA_CRTINIT ; SETUP THE TRION VGA REGISTERS + CALL TVGA_VDAINI ; INITIALIZE CALL KBD_INIT ; INITIALIZE KEYBOARD DRIVER ; ADD OURSELVES TO VDA DISPATCH TABLE - LD BC,FV_FNTBL ; BC := FUNCTION TABLE ADDRESS - LD DE,FV_IDAT ; DE := FPGA VGA INSTANCE DATA PTR + LD BC,TVGA_FNTBL ; BC := FUNCTION TABLE ADDRESS + LD DE,TVGA_IDAT ; DE := TRION VGA INSTANCE DATA PTR CALL VDA_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED ; INITIALIZE EMULATION LD C,A ; C := ASSIGNED VIDEO DEVICE NUM - LD DE,FV_FNTBL ; DE := FUNCTION TABLE ADDRESS - LD HL,FV_IDAT ; HL := FPGA VGA INSTANCE DATA PTR + LD DE,TVGA_FNTBL ; DE := FUNCTION TABLE ADDRESS + LD HL,TVGA_IDAT ; HL := TRION VGA INSTANCE DATA PTR CALL TERM_ATTACH ; DO IT CP $FF ; ERROR? - JR NZ,FV_INIT2 ; CONTINUE IF ALL GOOD + JR NZ,TVGA_INIT2 ; CONTINUE IF ALL GOOD OR A ; IF ERROR, SET FLAGS RET ; AND RETURN -FV_INIT2: - LD (FV_UNIT),A ; RECORD OUR UNIT NUMBER +TVGA_INIT2: + LD (TVGA_UNIT),A ; RECORD OUR UNIT NUMBER XOR A ; SIGNAL SUCCESS RET ; ;====================================================================== -; FPGA VGA DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS +; TRION VGA DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS ;====================================================================== ; -FV_FNTBL: - .DW FV_VDAINI - .DW FV_VDAQRY - .DW FV_VDARES - .DW FV_VDADEV - .DW FV_VDASCS - .DW FV_VDASCP - .DW FV_VDASAT - .DW FV_VDASCO - .DW FV_VDAWRC - .DW FV_VDAFIL - .DW FV_VDACPY - .DW FV_VDASCR - .DW FV_STAT - .DW FV_FLUSH - .DW FV_READ - .DW FV_VDARDC -#IF (($ - FV_FNTBL) != (VDA_FNCNT * 2)) - .ECHO "*** INVALID FV FUNCTION TABLE ***\n" +TVGA_FNTBL: + .DW TVGA_VDAINI + .DW TVGA_VDAQRY + .DW TVGA_VDARES + .DW TVGA_VDADEV + .DW TVGA_VDASCS + .DW TVGA_VDASCP + .DW TVGA_VDASAT + .DW TVGA_VDASCO + .DW TVGA_VDAWRC + .DW TVGA_VDAFIL + .DW TVGA_VDACPY + .DW TVGA_VDASCR + .DW TVGA_STAT + .DW TVGA_FLUSH + .DW TVGA_READ + .DW TVGA_VDARDC +#IF (($ - TVGA_FNTBL) != (VDA_FNCNT * 2)) + .ECHO "*** INVALID TVGA FUNCTION TABLE ***\n" !!!!! #ENDIF -FV_VDAINI: +TVGA_VDAINI: ; RESET VDA - CALL FV_VDARES ; RESET VDA + CALL TVGA_VDARES ; RESET VDA LD HL,0 ; ZERO - LD (FV_POS),HL ; ... TO POSITION + LD (TVGA_POS),HL ; ... TO POSITION LD A,' ' ; BLANK THE SCREEN - LD DE,FV_ROWS*FV_COLS ; FILL ENTIRE BUFFER - CALL FV_FILL ; DO IT + LD DE,TVGA_ROWS*TVGA_COLS ; FILL ENTIRE BUFFER + CALL TVGA_FILL ; DO IT LD DE,0 ; ROW = 0, COL = 0 - CALL FV_XY ; SEND CURSOR TO TOP LEFT - CALL FV_SHOWCUR ; NOW SHOW THE CURSOR + CALL TVGA_XY ; SEND CURSOR TO TOP LEFT + CALL TVGA_SHOWCUR ; NOW SHOW THE CURSOR XOR A ; SIGNAL SUCCESS RET -FV_VDAQRY: +TVGA_VDAQRY: LD C,$00 ; MODE ZERO IS ALL WE KNOW - LD D,FV_ROWS ; ROWS - LD E,FV_COLS ; COLS + LD D,TVGA_ROWS ; ROWS + LD E,TVGA_COLS ; COLS LD HL,0 ; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED XOR A ; SIGNAL SUCCESS RET -FV_VDARES: - CALL FV_CRTINIT +TVGA_VDARES: + CALL TVGA_CRTINIT XOR A ; SIGNAL SUCCESS RET -FV_VDADEV: - LD D,VDADEV_FV ; D := DEVICE TYPE +TVGA_VDADEV: + LD D,VDADEV_TVGA ; D := DEVICE TYPE LD E,0 ; E := PHYSICAL UNIT IS ALWAYS ZERO LD H,0 ; H := 0, DRIVER HAS NO MODES - LD L,FV_BASE ; L := BASE I/O ADDRESS + LD L,TVGA_BASE ; L := BASE I/O ADDRESS XOR A ; SIGNAL SUCCESS RET -FV_VDASCS: +TVGA_VDASCS: SYSCHKERR(ERR_NOTIMPL) ; NOT IMPLEMENTED (YET) RET -FV_VDASCP: - CALL FV_XY ; SET CURSOR POSITION +TVGA_VDASCP: + CALL TVGA_XY ; SET CURSOR POSITION XOR A ; SIGNAL SUCCESS RET -FV_VDASAT: +TVGA_VDASAT: ; ATTRIBUTES NOT SUPPORTED BY HARDWARE XOR A RET -FV_VDASCO: +TVGA_VDASCO: ; CHARACTER COLOR NOT SUPPORT BY HARDWARE XOR A ; SIGNAL SUCCESS RET ; DONE -FV_VDAWRC: +TVGA_VDAWRC: LD A,E ; CHARACTER TO WRITE GOES IN A - CALL FV_PUTCHAR ; PUT IT ON THE SCREEN + CALL TVGA_PUTCHAR ; PUT IT ON THE SCREEN XOR A ; SIGNAL SUCCESS RET -FV_VDAFIL: +TVGA_VDAFIL: LD A,E ; FILL CHARACTER GOES IN A EX DE,HL ; FILL LENGTH GOES IN DE - CALL FV_FILL ; DO THE FILL + CALL TVGA_FILL ; DO THE FILL XOR A ; SIGNAL SUCCESS RET -FV_VDACPY: - ; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS FV_POS +TVGA_VDACPY: + ; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS TVGA_POS ; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT PUSH HL ; SAVE LENGTH - CALL FV_XY2IDX ; ROW/COL IN DE -> SOURCE ADR IN HL + CALL TVGA_XY2IDX ; ROW/COL IN DE -> SOURCE ADR IN HL POP BC ; RECOVER LENGTH IN BC - LD DE,(FV_POS) ; PUT DEST IN DE - JP FV_BLKCPY ; DO A BLOCK COPY + LD DE,(TVGA_POS) ; PUT DEST IN DE + JP TVGA_BLKCPY ; DO A BLOCK COPY -FV_VDASCR: +TVGA_VDASCR: LD A,E ; LOAD E INTO A OR A ; SET FLAGS RET Z ; IF ZERO, WE ARE DONE PUSH DE ; SAVE E - JP M,FV_VDASCR1 ; E IS NEGATIVE, REVERSE SCROLL - CALL FV_SCROLL ; SCROLL FORWARD ONE LINE + JP M,TVGA_VDASCR1 ; E IS NEGATIVE, REVERSE SCROLL + CALL TVGA_SCROLL ; SCROLL FORWARD ONE LINE POP DE ; RECOVER E DEC E ; DECREMENT IT - JR FV_VDASCR ; LOOP -FV_VDASCR1: - CALL FV_RSCROLL ; SCROLL REVERSE ONE LINE + JR TVGA_VDASCR ; LOOP +TVGA_VDASCR1: + CALL TVGA_RSCROLL ; SCROLL REVERSE ONE LINE POP DE ; RECOVER E INC E ; INCREMENT IT - JR FV_VDASCR ; LOOP + JR TVGA_VDASCR ; LOOP -FV_STAT: - IN A,(FV_KBDST) ; GET STATUS +TVGA_STAT: + IN A,(TVGA_KBDST) ; GET STATUS AND $01 ; ISOLATE DATA WAITING BIT JP Z,CIO_IDLE ; NO DATA, EXIT VIA IDLE PROCESS RET -FV_FLUSH: +TVGA_FLUSH: XOR A ; SIGNAL SUCCESS RET -FV_READ: - CALL FV_STAT ; GET STATUS - JR Z,FV_READ ; LOOP TILL DATA READY - IN A,(FV_KBDDATA) ; GET BYTE +TVGA_READ: + CALL TVGA_STAT ; GET STATUS + JR Z,TVGA_READ ; LOOP TILL DATA READY + IN A,(TVGA_KBDDATA) ; GET BYTE LD E,A ; PUT IN E FOR RETURN XOR A ; SIGNAL SUCCESS RET ; DONE @@ -254,25 +254,25 @@ FV_READ: ; RETURN E = CHARACTER, B = COLOUR, C = ATTRIBUTES ;---------------------------------------------------------------------- -FV_VDARDC: - CALL FV_GETCHAR ; GET THE CHARACTER AT CUR CUR POS +TVGA_VDARDC: + CALL TVGA_GETCHAR ; GET THE CHARACTER AT CUR CUR POS LD E,A ; PUT IN E LD BC,0 ; COLOR AND ATTR NOT SUPPORTED XOR A ; SIGNAL SUCCESS RET ; ;====================================================================== -; FPGA VGA DRIVER - PRIVATE DRIVER FUNCTIONS +; TRION VGA DRIVER - PRIVATE DRIVER FUNCTIONS ;====================================================================== ; ; ;---------------------------------------------------------------------- -; PROBE FOR FPGA VGA HARDWARE +; PROBE FOR TRION VGA HARDWARE ;---------------------------------------------------------------------- ; ; ON RETURN, ZF SET INDICATES HARDWARE FOUND ; -FV_PROBE: +TVGA_PROBE: XOR A ; ASSUME H/W EXISTS RET ; @@ -280,9 +280,9 @@ FV_PROBE: ; CRTC DISPLAY CONTROLLER CHIP INITIALIZATION ;---------------------------------------------------------------------- ; -FV_CRTINIT: +TVGA_CRTINIT: LD A,%11001111 ; WHITE ON BLACK, CURSOR ON, ENABLE OUTPUT - OUT (FV_CTL),A ; WRITE TO CONTROL PORT + OUT (TVGA_CTL),A ; WRITE TO CONTROL PORT XOR A ; ZERO ACCUM RET ; DONE ; @@ -290,32 +290,32 @@ FV_CRTINIT: ; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E ;---------------------------------------------------------------------- ; -FV_XY: - CALL FV_HIDECUR ; HIDE THE CURSOR +TVGA_XY: + CALL TVGA_HIDECUR ; HIDE THE CURSOR PUSH DE ; SAVE NEW POSITION FOR NOW - CALL FV_XY2IDX ; CONVERT ROW/COL TO BUF IDX - LD (FV_POS),HL ; SAVE THE RESULT (DISPLAY POSITION) + CALL TVGA_XY2IDX ; CONVERT ROW/COL TO BUF IDX + LD (TVGA_POS),HL ; SAVE THE RESULT (DISPLAY POSITION) POP DE ; RECOVER INCOMING ROW/COL LD A,D ; GET ROW - OUT (FV_CROW),A ; SET ROW REGISTER + OUT (TVGA_CROW),A ; SET ROW REGISTER LD A,E ; GET COL INC A ; 1..79,0 (WHY???) CP 80 ; COL 80? - JR NZ, FV_XY1 ; SKIP IF NOT + JR NZ, TVGA_XY1 ; SKIP IF NOT XOR A ; ELSE MAKE IT ZERO! -FV_XY1: - OUT (FV_CCOL),A ; SET COL REGISTER - JP FV_SHOWCUR ; SHOW THE CURSOR AND EXIT +TVGA_XY1: + OUT (TVGA_CCOL),A ; SET COL REGISTER + JP TVGA_SHOWCUR ; SHOW THE CURSOR AND EXIT ; ;---------------------------------------------------------------------- ; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL ; D=ROW, E=COL ;---------------------------------------------------------------------- ; -FV_XY2IDX: +TVGA_XY2IDX: LD A,E ; SAVE COLUMN NUMBER IN A LD H,D ; SET H TO ROW NUMBER - LD E,FV_COLS ; SET E TO ROW LENGTH + LD E,TVGA_COLS ; SET E TO ROW LENGTH CALL MULT8 ; MULTIPLY TO GET ROW OFFSET, H * E = HL, E=0, B=0 LD E,A ; GET COLUMN BACK ADD HL,DE ; ADD IT IN @@ -325,17 +325,17 @@ FV_XY2IDX: ; SHOW OR HIDE CURSOR ;---------------------------------------------------------------------- ; -FV_SHOWCUR: +TVGA_SHOWCUR: LD A,%11001111 ; CONTROL PORT VALUE ;;;LD A,%11111111 ; CONTROL PORT VALUE - OUT (FV_CTL),A ; SET REGISTER + OUT (TVGA_CTL),A ; SET REGISTER XOR A ; SIGNAL SUCCESS RET ; DONE ; -FV_HIDECUR: +TVGA_HIDECUR: LD A,%11001111 ; CONTROL PORT VALUE ;;;LD A,%11111111 ; CONTROL PORT VALUE - OUT (FV_CTL),A ; SET REGISTER + OUT (TVGA_CTL),A ; SET REGISTER XOR A ; SIGNAL SUCCESS RET ; DONE ; @@ -343,17 +343,17 @@ FV_HIDECUR: ; (DE)SELECT FRAME BUFFER ;---------------------------------------------------------------------- ; -FV_BUFSEL: +TVGA_BUFSEL: PUSH AF LD A,$01 - OUT (FV_BUFCTL),A + OUT (TVGA_BUFCTL),A POP AF RET ; -FV_BUFDESEL: +TVGA_BUFDESEL: PUSH AF XOR A - OUT (FV_BUFCTL),A + OUT (TVGA_BUFCTL),A POP AF RET ; @@ -361,36 +361,36 @@ FV_BUFDESEL: ; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR ;---------------------------------------------------------------------- ; -FV_PUTCHAR: +TVGA_PUTCHAR: ; WRITE CHAR AT CURRENT CURSOR POSITION. PUSH AF ; SAVE INCOMING CHAR - CALL FV_HIDECUR ; HIDE CURSOR - CALL FV_BUFSEL ; SELECT FRAME BUFFER + CALL TVGA_HIDECUR ; HIDE CURSOR + CALL TVGA_BUFSEL ; SELECT FRAME BUFFER POP AF - LD HL,(FV_POS) ; GET CUR BUF POSITION - LD DE,FV_FBUF ; START OF FRAME BUF + LD HL,(TVGA_POS) ; GET CUR BUF POSITION + LD DE,TVGA_FBUF ; START OF FRAME BUF ADD HL,DE ; ADD IT IN LD (HL),A ; PUT THE CHAR ; ; SET NEW POSITION - LD HL,(FV_POS) ; GET POSITION + LD HL,(TVGA_POS) ; GET POSITION INC HL ; BUMP POSITION - LD (FV_POS),HL ; SAVE NEW POSITION + LD (TVGA_POS),HL ; SAVE NEW POSITION ; ; PUT CUROR IN PLACE - LD DE,FV_COLS ; COLS PER LINE + LD DE,TVGA_COLS ; COLS PER LINE CALL DIV16 ; BC=ROW, HL=COL LD D,C LD E,L - CALL FV_XY - CALL FV_BUFDESEL ; DESELECT FRAME BUFFER - JP FV_SHOWCUR ; SHOW IT AND RETURN + CALL TVGA_XY + CALL TVGA_BUFDESEL ; DESELECT FRAME BUFFER + JP TVGA_SHOWCUR ; SHOW IT AND RETURN ; ;---------------------------------------------------------------------- ; GET CHAR VALUE TO A FROM CURRENT VDU BUFFER POSITION ;---------------------------------------------------------------------- ; -FV_GETCHAR: +TVGA_GETCHAR: XOR A RET ; @@ -401,107 +401,107 @@ FV_GETCHAR: ; DE: NUMBER OF CHARACTERS TO FILL ;---------------------------------------------------------------------- ; -FV_FILL: +TVGA_FILL: PUSH AF ; SAVE INCOMING FILL CHAR - CALL FV_HIDECUR ; HIDE CURSOR - CALL FV_BUFSEL ; SELECT BUFFER - LD HL,(FV_POS) ; CUR POS TO HL - LD BC,FV_FBUF ; ADR OF FRAME + CALL TVGA_HIDECUR ; HIDE CURSOR + CALL TVGA_BUFSEL ; SELECT BUFFER + LD HL,(TVGA_POS) ; CUR POS TO HL + LD BC,TVGA_FBUF ; ADR OF FRAME ADD HL,BC ; ADD IT IN POP AF LD C,A ; FILL CHAR TO C -FV_FILL1: +TVGA_FILL1: LD A,D ; CHECK FILL OR E ; ... COUNTER - JR Z,FV_FILL2 ; DONE IF ZERO + JR Z,TVGA_FILL2 ; DONE IF ZERO LD (HL),C ; FILL ONE CHAR INC HL ; BUMP BUF PTR DEC DE ; DEC FILL COUNTER - JR FV_FILL1 ; LOOP + JR TVGA_FILL1 ; LOOP ; -FV_FILL2: - CALL FV_BUFDESEL ; DESELECT BUFFER - JP FV_SHOWCUR ; EXIT VIA SHOW CURSOR +TVGA_FILL2: + CALL TVGA_BUFDESEL ; DESELECT BUFFER + JP TVGA_SHOWCUR ; EXIT VIA SHOW CURSOR ; ;---------------------------------------------------------------------- ; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED) ;---------------------------------------------------------------------- ; -FV_SCROLL: - CALL FV_BUFSEL ; SELECT FRAME BUFFER +TVGA_SCROLL: + CALL TVGA_BUFSEL ; SELECT FRAME BUFFER ; ; COPY "UP" ONE LINE - LD HL,FV_FBUF + FV_COLS ; FROM SECOND LINE - LD DE,FV_FBUF ; TO FIRST LINE - LD BC,+(FV_ROWS - 1) * FV_COLS ; ALL BUT ONE LINE + LD HL,TVGA_FBUF + TVGA_COLS ; FROM SECOND LINE + LD DE,TVGA_FBUF ; TO FIRST LINE + LD BC,+(TVGA_ROWS - 1) * TVGA_COLS ; ALL BUT ONE LINE LDIR ; DO IT ; ; FILL LAST LINE OF SCREEN - LD HL,FV_FBUF + ((FV_ROWS - 1) * FV_COLS) ; LAST LINE + LD HL,TVGA_FBUF + ((TVGA_ROWS - 1) * TVGA_COLS) ; LAST LINE LD A,' ' ; FILL CHAR LD (HL),A ; COPY 1 CHAR - LD DE,FV_FBUF + ((FV_ROWS - 1) * FV_COLS) + 1 ; SECOND POS IN LAST LINE - LD BC,FV_COLS - 1 ; COLS PER LINE - 1 + LD DE,TVGA_FBUF + ((TVGA_ROWS - 1) * TVGA_COLS) + 1 ; SECOND POS IN LAST LINE + LD BC,TVGA_COLS - 1 ; COLS PER LINE - 1 LDIR ; FILL IT ; - CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + CALL TVGA_BUFDESEL ; DESELECT FRAME BUFFER RET ; DONE ; ;---------------------------------------------------------------------- ; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED) ;---------------------------------------------------------------------- ; -FV_RSCROLL: - CALL FV_BUFSEL ; SELECT FRAME BUFFER +TVGA_RSCROLL: + CALL TVGA_BUFSEL ; SELECT FRAME BUFFER ; ; COPY "DOWN" ONE LINE - LD HL,FV_FBUF + (FV_COLS * (FV_ROWS - 1)) - 1 ; FROM END OF SECOND TO LAST LINE - LD DE,FV_FBUF + (FV_COLS * FV_ROWS) - 1 ; TO END OF LAST LINE - LD BC,+(FV_ROWS - 1) * FV_COLS ; ALL BUT ONE LINE + LD HL,TVGA_FBUF + (TVGA_COLS * (TVGA_ROWS - 1)) - 1 ; FROM END OF SECOND TO LAST LINE + LD DE,TVGA_FBUF + (TVGA_COLS * TVGA_ROWS) - 1 ; TO END OF LAST LINE + LD BC,+(TVGA_ROWS - 1) * TVGA_COLS ; ALL BUT ONE LINE LDDR ; DO IT IN REVERSE ; ; FILL FIRST LINE OF SCREEN - LD HL,FV_FBUF ; FIRST LINE + LD HL,TVGA_FBUF ; FIRST LINE LD A,' ' ; FILL CHAR LD (HL),A ; COPY 1 CHAR - LD DE,FV_FBUF + 1 ; SECOND POS IN FIRST LINE - LD BC,FV_COLS - 1 ; COLS PER LINE - 1 + LD DE,TVGA_FBUF + 1 ; SECOND POS IN FIRST LINE + LD BC,TVGA_COLS - 1 ; COLS PER LINE - 1 LDIR ; FILL IT ; - CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + CALL TVGA_BUFDESEL ; DESELECT FRAME BUFFER RET ; DONE ; ;---------------------------------------------------------------------- ; BLOCK COPY BC BYTES FROM HL TO DE ;---------------------------------------------------------------------- ; -FV_BLKCPY: +TVGA_BLKCPY: - CALL FV_BUFSEL ; SELECT FRAME BUFFER + CALL TVGA_BUFSEL ; SELECT FRAME BUFFER PUSH BC ; SAVE LENGTH - LD BC,FV_FBUF ; FRAME BUFFER ADR + LD BC,TVGA_FBUF ; FRAME BUFFER ADR ADD HL,BC ; ADD TO SOURCE EX DE,HL ; EXCHANGE ADD HL,BC ; ADD TO DEST EX DE,HL ; EXCHANGE POP BC ; RECOVER LENGTH LDIR ; LDIR DOES THE COPY - CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + CALL TVGA_BUFDESEL ; DESELECT FRAME BUFFER RET ; DONE ; ;================================================================================================== -; FPGA VGA DRIVER - DATA +; TRION VGA DRIVER - DATA ;================================================================================================== ; -FV_POS .DW 0 ; CURRENT DISPLAY POSITION -;;;FV_ACTIVE .DB FALSE ; FLAG FOR DRIVER ACTIVE -FV_UNIT .DB $FF ; ASSIGNED UNIT NUMBER +TVGA_POS .DW 0 ; CURRENT DISPLAY POSITION +;;;TVGA_ACTIVE .DB FALSE ; FLAG FOR DRIVER ACTIVE +TVGA_UNIT .DB $FF ; ASSIGNED UNIT NUMBER ; ;================================================================================================== ; VGA DRIVER - INSTANCE DATA ;================================================================================================== ; -FV_IDAT: - .DB KBDMODE_FV ; FPGA VGA KEYBOARD CONTROLLER - .DB FV_KBDST - .DB FV_KBDDATA +TVGA_IDAT: + .DB KBDMODE_T35 ; S100 T35 KEYBOARD CONTROLLER + .DB TVGA_KBDST + .DB TVGA_KBDDATA diff --git a/Source/ver.inc b/Source/ver.inc index 3fed1e83..ef52cc31 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 6 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.6.0-dev.36" +#DEFINE BIOSVER "3.6.0-dev.37" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index 918ebbac..404271b9 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 6 rup equ 0 rtp equ 0 biosver macro - db "3.6.0-dev.36" + db "3.6.0-dev.37" endm