diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index 76bc9953..921b0ad5 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index 0e1c8ac6..a344f3b9 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Errata.pdf b/Doc/RomWBW Errata.pdf index 60a3dc49..af896eaa 100644 Binary files a/Doc/RomWBW Errata.pdf and b/Doc/RomWBW Errata.pdf differ diff --git a/Doc/RomWBW ROM Applications.pdf b/Doc/RomWBW ROM Applications.pdf index 115d2b47..1ea4364e 100644 Binary files a/Doc/RomWBW ROM Applications.pdf and b/Doc/RomWBW ROM Applications.pdf differ diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf index 716a6a19..77d98374 100644 Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf index dc5d3ed6..e9a69b50 100644 Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ diff --git a/ReadMe.md b/ReadMe.md index 8d169dc7..83d241c6 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -3,7 +3,7 @@ **RomWBW ReadMe** \ Version 3.4 \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ -27 Nov 2023 +29 Nov 2023 # Overview diff --git a/ReadMe.txt b/ReadMe.txt index 26cb1bba..91858946 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -1,6 +1,6 @@ RomWBW ReadMe Wayne Warthen (wwarthen@gmail.com) -27 Nov 2023 +29 Nov 2023 diff --git a/Source/Doc/UserGuide.md b/Source/Doc/UserGuide.md index 5715524a..a3b6d493 100644 --- a/Source/Doc/UserGuide.md +++ b/Source/Doc/UserGuide.md @@ -3966,21 +3966,33 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- VGA -- CVDU -- PRP -- MD -- FD -- IDE -- PPIDE +- DSRTC: MODE=STD, IO=112 +- UART: MODE=SBC, IO=104 +- UART: MODE=CAS, IO=128 +- UART: MODE=MFP, IO=104 +- UART: MODE=4UART, IO=192 +- UART: MODE=4UART, IO=200 +- UART: MODE=4UART, IO=208 +- UART: MODE=4UART, IO=216 +- SIO MODE=ZP, IO=176, CHANNEL A +- SIO MODE=ZP, IO=176, CHANNEL B +- VGA: IO=224, KBD MODE=PS/2, KBD IO=224 +- CVDU: MODE=ECB, IO=224, KBD MODE=PS/2, KBD IO=226 +- CVDU occupies 905 bytes. +- KBD: ENABLED +- PRP: IO=168 +- PRPCON: ENABLED +- PRPSD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=DIO, IO=54, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DIO, IO=54, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=96, MASTER +- PPIDE: IO=96, SLAVE ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4000,11 +4012,20 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- SIMRTC -- UART -- SIO -- MD -- HDSK +- SIMRTC: IO=254 +- UART: MODE=SBC, IO=104 +- UART: MODE=CAS, IO=128 +- UART: MODE=MFP, IO=104 +- UART: MODE=4UART, IO=192 +- UART: MODE=4UART, IO=200 +- UART: MODE=4UART, IO=208 +- UART: MODE=4UART, IO=216 +- SIO MODE=ZP, IO=176, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=ZP, IO=176, CHANNEL B, INTERRUPTS ENABLED +- FONTS occupy 0 bytes. +- MD: TYPE=RAM +- MD: TYPE=ROM +- HDSK: IO=253, DEVICE COUNT=2 ##### Notes: @@ -4029,20 +4050,26 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- ASCI -- UART -- TMS -- PPK -- MD -- FD -- SD -- AY38910 +- DSRTC: MODE=STD, IO=136 +- ASCI: IO=64, INTERRUPTS ENABLED +- ASCI: IO=65, INTERRUPTS ENABLED +- UART: MODE=CAS, IO=128 +- UART: MODE=4UART, IO=192 +- UART: MODE=4UART, IO=200 +- UART: MODE=4UART, IO=208 +- UART: MODE=4UART, IO=216 +- TMS: MODE=N8, IO=152 +- PPK: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=N8, IO=140, DRIVE 0, TYPE=3.5" HD +- FD: MODE=N8, IO=140, DRIVE 1, TYPE=3.5" HD +- SD: MODE=CSIO, IO=136, UNITS=1 +- AY38910: MODE=N8, IO=156, CLOCK=1789772 HZ ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives - SD Card interface is configured for CSIO (N8 date code >= 2312) `\clearpage`{=latex} @@ -4063,16 +4090,18 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- PPP -- MD -- FD +- DSRTC: MODE=STD, IO=112 +- UART: MODE=SBC, IO=104 +- PPP: IO=96 +- PPPCON: ENABLED +- PPPSD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=DIO, IO=54, DRIVE 0, TYPE=3.5" HD ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives - If ParPortProp is installed, initial console output is determined by JP1: - Shorted: console to on-board serial port @@ -4096,17 +4125,19 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- PPP -- MD -- FD -- CTC +- DSRTC: MODE=STD, IO=112 +- UART: MODE=SBC, IO=104 +- PPP: IO=96 +- PPPCON: ENABLED +- PPPSD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=ZETA2, IO=48, DRIVE 0, TYPE=3.5" HD +- CTC: IO=32, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives - If ParPortProp is installed, initial console output is determined by JP1: - Shorted: console to on-board serial port @@ -4130,22 +4161,32 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- ASCI -- UART -- VGA -- CVDU -- KBD -- PRP -- MD -- FD -- IDE -- SD +- DSRTC: MODE=STD, IO=138 +- ASCI: IO=64, INTERRUPTS ENABLED +- ASCI: IO=65, INTERRUPTS ENABLED +- UART: MODE=CAS, IO=128 +- UART: MODE=MFP, IO=104 +- UART: MODE=4UART, IO=192 +- UART: MODE=4UART, IO=200 +- UART: MODE=4UART, IO=208 +- UART: MODE=4UART, IO=216 +- VGA: IO=224, KBD MODE=PS/2, KBD IO=224 +- CVDU: MODE=ECB, IO=224, KBD MODE=PS/2, KBD IO=226 +- KBD: ENABLED +- PRP: IO=168 +- PRPCON: ENABLED +- PRPSD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=DIDE, IO=42, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DIDE, IO=42, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=MK4, IO=128, MASTER +- IDE: MODE=MK4, IO=128, SLAVE +- SD: MODE=MK4, IO=137, UNITS=1 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4165,20 +4206,28 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- ACIA -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=136 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4196,20 +4245,25 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- KIO -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=132, TIMER MODE=TIMER/16, DIVISOR=9216, HI=256, LO=36, INTERRUPTS ENABLED ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives - SIO Serial baud rate managed by CTC `\clearpage`{=latex} @@ -4230,21 +4284,30 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: - For use with Z2 bank switched memory board (Z2 external memory management) - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4262,21 +4325,30 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: - For use with linear memory board (Z180 native memory management) - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4296,20 +4368,30 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- Z2U -- UART -- SIO -- ACIA -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- Z2U: IO=16 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: -- For use with linear memory board (Z280 native memory management) -- FD configured for 3.5" HD floppy drives +- For use with Z2 bank switched memory board (Z2 external memory management) + +`\clearpage`{=latex} #### ROM Image File: RCZ280_nat.rom @@ -4325,19 +4407,27 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- Z2U -- UART -- SIO -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- Z2U: IO=16, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: -- For use with Z2 bank switched memory board (Z2 external memory management) -- FD configured for 3.5" HD floppy drives +- For use with linear memory board (Z280 native memory management) `\clearpage`{=latex} @@ -4357,26 +4447,34 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- INTRTC: ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=STD, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=136, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} ### Tiny Z80 SBC -#### ROM Image File: RCZ80_easy.rom +#### ROM Image File: RCZ80_tiny.rom | | | |-------------------|---------------| @@ -4390,19 +4488,27 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=STD, IO=24, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=24, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=144, MASTER +- IDE: MODE=RC, IO=144, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=16, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4422,20 +4528,28 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- ACIA -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=136 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4455,22 +4569,31 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- SD -- AY38910 +- FP: LEDIO=13, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 +- AY38910: MODE=RCZ180, IO=104, CLOCK=1789772 HZ ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4490,22 +4613,31 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- SD -- AY38910 +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 +- AY38910: MODE=RCZ180, IO=104, CLOCK=1789772 HZ ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4525,10 +4657,12 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- INTRTC -- ASCI -- MD -- SD +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- SD: MODE=SC, IO=12, UNITS=1 ##### Notes: @@ -4550,21 +4684,30 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- SD +- FP: LEDIO=160, SWIO=160 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=144, MASTER +- IDE: MODE=RC, IO=144, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4584,21 +4727,30 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- SD +- FP: LEDIO=160, SWIO=160 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=144, MASTER +- IDE: MODE=RC, IO=144, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4618,21 +4770,31 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE -- SD +- FP: LEDIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 +- AY38910: MODE=RCZ180, IO=104, CLOCK=1789772 HZ ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4652,16 +4814,18 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- BQRTC -- ASCI -- MD -- FD -- PPIDE +- BQRTC: IO=80 +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=DYNO, IO=132, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DYNO, IO=132, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=76, MASTER +- PPIDE: IO=76, SLAVE ##### Notes: -- FD configured for 3.5" HD floppy drives - `\clearpage`{=latex} ### Nhyodyne Z80 MBC @@ -4680,25 +4844,37 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- PKD -- DSRTC -- UART -- SIO -- PIO -- LPT -- CVDU -- TMS -- KBD -- ESP -- MD -- FD -- PPIDE -- SPK +- PKD: IO=96 +- DSRTC: MODE=STD, IO=112 +- UART: MODE=SBC, IO=104 +- UART: MODE=DUAL, IO=128 +- UART: MODE=DUAL, IO=136 +- SIO MODE=ZP, IO=176, CHANNEL A +- SIO MODE=ZP, IO=176, CHANNEL B +- PIO: IO=184, CHANNEL A +- PIO: IO=184, CHANNEL B +- PIO: IO=188, CHANNEL A +- PIO: IO=188, CHANNEL B +- LPT: MODE=SPP, IO=232 +- CVDU: MODE=MBC, IO=224, KBD MODE=PS/2, KBD IO=226 +- TMS: MODE=MBC, IO=152 +- KBD: ENABLED +- ESP: IO=156 +- ESPCON: ENABLED +- ESPSER: DEVICE=0 +- ESPSER: DEVICE=1 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=MBC, IO=48, DRIVE 0, TYPE=3.5" HD +- FD: MODE=MBC, IO=48, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=96, MASTER +- PPIDE: IO=96, SLAVE +- SPK: IO=112 +- CTC: IO=176 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4718,12 +4894,15 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- ASCI -- GDC -- KBD -- MD -- PPIDE +- DSRTC: MODE=STD, IO=132 +- ASCI: IO=64 +- ASCI: IO=65 +- GDC: MODE=RPH, DISPLAY=EGA, IO=144 +- KBD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- PPIDE: IO=136, MASTER +- PPIDE: IO=136, SLAVE ##### Notes: @@ -4747,24 +4926,32 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- ACIA -- VRC -- KBD -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- VRC: IO=0, KBD MODE=VRC, KBD IO=244 +- KBD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=136 ##### Notes: - ZRC is actually contains no ROM and 2MB of RAM. The first 512KB of RAM is loaded from disk and then handled like ROM. - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4782,23 +4969,30 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- ACIA -- VRC -- KBD -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- VRC: IO=0, KBD MODE=VRC, KBD IO=244 +- KBD: ENABLED +- MD: TYPE=RAM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=136 ##### Notes: - ROMless boot -- HBIOS is loaded from disk at boot - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4818,21 +5012,29 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- INTRTC -- ASCI -- UART -- SIO -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: - ROMless boot -- HBIOS is loaded from disk at boot - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4852,23 +5054,31 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- Z2U -- UART -- SIO -- VRC -- KBD -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- Z2U: IO=16, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- VRC: IO=0, KBD MODE=VRC, KBD IO=244 +- KBD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: - ZZRCC actually contains no ROM and 512KB of RAM. The first 256KB of RAM is loaded from disk and then handled like ROM. - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4886,22 +5096,29 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- Z2U -- UART -- SIO -- VRC -- KBD -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- Z2U: IO=16, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- VRC: IO=0, KBD MODE=VRC, KBD IO=244 +- KBD: ENABLED +- MD: TYPE=RAM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: - ROMless boot -- HBIOS is loaded from disk at boot - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4921,21 +5138,29 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- Z2U -- UART -- SIO -- VRC -- KBD -- MD -- FD -- IDE -- PPIDE +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- Z2U: IO=16, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- VRC: IO=0, KBD MODE=VRC, KBD IO=244 +- KBD: ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -4955,10 +5180,12 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- SIO -- MD -- SD -- CTC +- SIO MODE=Z80R, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=Z80R, IO=128, CHANNEL B, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- SD: MODE=, IO=104, UNITS=1 +- CTC: IO=64 ##### Notes: @@ -4980,11 +5207,15 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- INTRTC -- ASCI -- SCON -- MD -- SD +- FP: LEDIO=0 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- SCON: IO=0 +- MD: TYPE=RAM +- MD: TYPE=ROM +- SD: MODE=SC, IO=12, UNITS=1 + ##### Notes: @@ -5006,17 +5237,31 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- PCF -- UART -- SIO -- PIO -- LPT -- DMA -- CH -- ESP -- MD -- SPK +- DSRTC: MODE=STD, IO=148 +- PCF: IO=86 +- UART: MODE=SBC, IO=88 +- UART: MODE=AUX, IO=168 +- UART: MODE=DUAL, IO=112 +- UART: MODE=DUAL, IO=120 +- SIO MODE=ZP, IO=96, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=ZP, IO=96, CHANNEL B, INTERRUPTS ENABLED +- PIO: IO=104, CHANNEL A +- PIO: IO=104, CHANNEL B +- PIO: IO=108, CHANNEL A +- PIO: IO=108, CHANNEL B +- LPT: MODE=SPP, IO=72 +- DMA: MODE=DUO, IO=64 +- CH: IO=78 +- CHUSB: IO=78 +- CHSD: IO=78 +- ESP: IO=156 +- ESPCON: ENABLED +- ESPSER: DEVICE=0 +- ESPSER: DEVICE=1 +- MD: TYPE=RAM +- MD: TYPE=ROM +- SPK: IO=148 +- CTC: IO=96, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED ##### Notes: @@ -5040,20 +5285,28 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- DSRTC -- UART -- SIO -- ACIA -- MD -- FD -- IDE -- PPIDE -- CTC +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=192 +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- CTC: IO=136 ##### Notes: - CPU speed will be dynamically measured at startup if DSRTC is present -- FD configured for 3.5" HD floppy drives `\clearpage`{=latex} @@ -5073,18 +5326,20 @@ the RomWBW HBIOS configuration. ##### Supported Hardware (see [Appendix B - Device Summary]): -- INTRTC -- ASCI -- UART -- TMS -- MD -- FD -- SD +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: MODE=RC, IO=160 +- UART: MODE=RC, IO=168 +- TMS: MODE=MSX, IO=152 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=EPFDC, IO=72, DRIVE 0, TYPE=3.5" HD +- FD: MODE=EPFDC, IO=72, DRIVE 1, TYPE=3.5" HD +- SD: MODE=, IO=66, UNITS=1 ##### Notes: -- FD configured for 3.5" HD floppy drives - `\clearpage`{=latex} ## Appendix B - Device Summary @@ -5113,27 +5368,30 @@ may be discovered by RomWBW in your system. | FP | System | Simple LED & Switch Front Panel | | GDC | Video | uPD7220 Video Display Controller | | HDSK | Disk | SIMH Simulator Hard Disk | -| I2C | System | I2C Interface | | ICM | DsKy | ICM7218-based Display/Keypad on PPI | | IDE | Disk | IDE/ATA/ATAPI Hard Disk Interface | | IMM | Disk | IMM Zip Drive on PPI | | INTRTC | RTC | Interrupt-based Real Time Clock | -| KBD | Kbd | 8242 PS/2 Keyboard Controller | +| KBD | Keyboard | 8242 PS/2 Keyboard Controller | | KIO | System | Zilog Serial/ Parallel Counter/Timer | | LPT | Char | Parallel I/O Controller | | MD | Disk | ROM/RAM Disk | -| MSXKYB | Kbd | MSX Compliant Matrix Keyboard | -| PKD | DsKy | P8279-based Display/Keypad on PPI | +| MSXKYB | Keyboard | MSX Compliant Matrix Keyboard | +| PCF | RTC | PCF8584-based I2C Real-Time Clock | | PIO | Char | Zilog Parallel Interface Controller | +| PKD | DsKy | P8279-based Display/Keypad on PPI | | PPA | Disk | PPA Zip Drive on PPI | | PPIDE | Disk | 8255 IDE/ATA/ATAPI Hard Disk Interface | -| PPK | Kbd | Matrix Keyboard | +| PPK | Keyboard | Matrix Keyboard | +| PPP | System | ParPortProp Host Interface Controller | | PPPCON | Serial | ParPortProp Serial Console Interface | | PPPSD | Disk | ParPortProp SD Card Interface | +| PRP | System | PropIO Host Interface Controller | | PRPCON | Serial | PropIO Serial Console Interface | | PRPSD | Disk | PropIO SD Card Interface | | RF | Disk | RAM Floppy Disk Interface | | RP5C01 | RTC | Ricoh RPC01A Real-Time Clock w/ NVRAM | +| SCON | Char | S100 Console | | SD | Disk | SD Card Interface | | SIMRTC | RTC | SIMH Simulator Real-Time Clock | | SIO | Char | Zilog Serial Port Interface | diff --git a/Source/HBIOS/Build.cmd b/Source/HBIOS/Build.cmd index c5447e6a..d52455a0 100644 --- a/Source/HBIOS/Build.cmd +++ b/Source/HBIOS/Build.cmd @@ -33,6 +33,16 @@ PowerShell -ExecutionPolicy Unrestricted .\Build.ps1 %* || exit /b call build_env.cmd +:: +:: Start of the actual build process for a given ROM. +:: + +echo. +echo ============================================================ +echo %ROMName% for Z%CPUType% CPU +echo ============================================================ +echo. + :: :: Create a small app that is used to export key build variables of the build. :: Then run the app to output a file with the variables. Finally, read the @@ -43,12 +53,6 @@ tasm -t80 -g3 -dCMD hbios_env.asm hbios_env.com hbios_env.lst || exit /b zxcc hbios_env >hbios_env.cmd call hbios_env.cmd -:: -:: Start of the actual build process for a given ROM. -:: - -echo Building %ROMSize%K ROM %ROMName% for Z%CPUType% CPU... - :: :: UNA is a special case, check for it and jump if needed. :: diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm index dd1900a8..8c24da9e 100644 --- a/Source/HBIOS/acia.asm +++ b/Source/HBIOS/acia.asm @@ -717,6 +717,13 @@ ACIA0_CFG: .DW ACIA0_INT ; INT HANDLER POINTER .DW (ACIA0CLK / ACIA0DIV) & $FFFF ; CLOCK FREQ AS .DW (ACIA0CLK / ACIA0DIV) >> 16 ; ... DWORD VALUE +; + .ECHO "ACIA: IO=" + .ECHO ACIA0BASE +#IF (INTMODE == 1) + .ECHO ", INTERRUPTS ENABLED" +#ENDIF + .ECHO "\n" ; ACIA_CFGSIZ .EQU $ - ACIA_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -733,6 +740,13 @@ ACIA1_CFG: .DW ACIA1_INT ; INT HANDLER POINTER .DW (ACIA1CLK / ACIA1DIV) & $FFFF ; CLOCK FREQ AS .DW (ACIA1CLK / ACIA1DIV) >> 16 ; ... DWORD VALUE +; + .ECHO "ACIA: IO=" + .ECHO ACIA1BASE +#IF (INTMODE == 1) + .ECHO ", INTERRUPTS ENABLED" +#ENDIF + .ECHO "\n" ; #ENDIF ; diff --git a/Source/HBIOS/asci.asm b/Source/HBIOS/asci.asm index aa6cb090..eb5d737f 100644 --- a/Source/HBIOS/asci.asm +++ b/Source/HBIOS/asci.asm @@ -836,6 +836,13 @@ ASCI1_CFG: .DB ASCI1_BASE ; BASE PORT .DW ASCI1CFG ; LINE CONFIGURATION .DW ASCI1_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "ASCI: IO=" + .ECHO ASCI1_BASE +#IF ((ASCIINTS) & (INTMODE >0)) + .ECHO ", INTERRUPTS ENABLED" +#ENDIF + .ECHO "\n" ; ASCI_CFGSIZ .EQU $ - ASCI_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -847,6 +854,13 @@ ASCI0_CFG: .DB ASCI0_BASE ; BASE PORT .DW ASCI0CFG ; LINE CONFIGURATION .DW ASCI0_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "ASCI: IO=" + .ECHO ASCI0_BASE +#IF ((ASCIINTS) & (INTMODE >0)) + .ECHO ", INTERRUPTS ENABLED" +#ENDIF + .ECHO "\n" ; #ELSE ; @@ -858,6 +872,13 @@ ASCI0_CFG: .DB ASCI0_BASE ; BASE PORT .DW ASCI0CFG ; LINE CONFIGURATION .DW ASCI0_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "ASCI: IO=" + .ECHO ASCI0_BASE +#IF ((ASCIINTS) & (INTMODE >0)) + .ECHO ", INTERRUPTS ENABLED" +#ENDIF + .ECHO "\n" ; ASCI_CFGSIZ .EQU $ - ASCI_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -870,7 +891,13 @@ ASCI1_CFG: .DW ASCI1CFG ; LINE CONFIGURATION .DW ASCI1_RCVBUF ; POINTER TO RCV BUFFER STRUCT ; + .ECHO "ASCI: IO=" + .ECHO ASCI1_BASE +#IF ((ASCIINTS) & (INTMODE > 0)) + .ECHO ", INTERRUPTS ENABLED" #ENDIF + .ECHO "\n" ; +#ENDIF ; ASCI_CFGCNT .EQU ($ - ASCI_CFG) / ASCI_CFGSIZ diff --git a/Source/HBIOS/ay38910.asm b/Source/HBIOS/ay38910.asm index 45b97f00..4188fa17 100644 --- a/Source/HBIOS/ay38910.asm +++ b/Source/HBIOS/ay38910.asm @@ -19,12 +19,15 @@ ; VOLTAGE LEVEL OUTPUT ON A AY-3-8910 IS LOW AND AROUND 2V ON YM2149. ; AY_RCSND .EQU 0 ; 0 = EB MODULE, 1=MF MODULE +; + .ECHO "AY38910: MODE=" ; #IF (AYMODE == AYMODE_SCG) AY_RSEL .EQU $9A AY_RDAT .EQU $9B AY_RIN .EQU AY_RSEL AY_ACR .EQU $9C + .ECHO "SCG" #ENDIF ; #IF (AYMODE == AYMODE_N8) @@ -32,30 +35,35 @@ AY_RSEL .EQU $9C AY_RDAT .EQU $9D AY_RIN .EQU AY_RSEL AY_ACR .EQU N8_DEFACR + .ECHO "N8" #ENDIF ; #IF (AYMODE == AYMODE_RCZ80) AY_RSEL .EQU $D8 AY_RDAT .EQU $D0 AY_RIN .EQU AY_RSEL+AY_RCSND + .ECHO "RCZ80" #ENDIF ; #IF (AYMODE == AYMODE_RCZ180) AY_RSEL .EQU $68 AY_RDAT .EQU $60 AY_RIN .EQU AY_RSEL+AY_RCSND + .ECHO "RCZ180" #ENDIF ; #IF (AYMODE == AYMODE_MSX) AY_RSEL .EQU $A0 AY_RDAT .EQU $A1 AY_RIN .EQU $A2 + .ECHO "MSX" #ENDIF ; #IF (AYMODE == AYMODE_LINC) AY_RSEL .EQU $33 AY_RDAT .EQU $32 AY_RIN .EQU $32 + .ECHO "LINC" #ENDIF ; #IF (AYMODE == AYMODE_MBC) @@ -63,7 +71,14 @@ AY_RSEL .EQU $A0 AY_RDAT .EQU $A1 AY_RIN .EQU AY_RSEL AY_ACR .EQU $A2 + .ECHO "MBC" #ENDIF +; + .ECHO ", IO=" + .ECHO AY_RSEL + .ECHO ", CLOCK=" + .ECHO AY_CLK + .ECHO " HZ\n" ; ;====================================================================== ; @@ -107,10 +122,6 @@ AY_NOISECNT .EQU 1 ; COUNT NUMBER OF NOISE CHANNELS ;#ELSE ; PRESCALE THE TONE PERIOD ;AY_SCALE .EQU 3 ; DATA TO MAINTAIN MAXIMUM ;#ENDIF ; RANGE AND ACCURACY -; - .ECHO "AY38910 CLOCK: " - .ECHO AY_CLK - .ECHO "\n" ; #INCLUDE "audio.inc" ; diff --git a/Source/HBIOS/bqrtc.asm b/Source/HBIOS/bqrtc.asm index ce0daeb5..51fd677f 100644 --- a/Source/HBIOS/bqrtc.asm +++ b/Source/HBIOS/bqrtc.asm @@ -91,6 +91,10 @@ BQRTC_UTI .EQU %00001000 BQRTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS) + .ECHO "BQRTC: IO=" + .ECHO BQRTC_BASE + .ECHO "\n" + ; RTC Device Initialization Entry BQRTC_INIT: diff --git a/Source/HBIOS/ch.asm b/Source/HBIOS/ch.asm index 68c8fe87..84fb6def 100644 --- a/Source/HBIOS/ch.asm +++ b/Source/HBIOS/ch.asm @@ -102,6 +102,10 @@ CH_CFG0: ; DEVICE 0 .DW CHUSB_CFG0 ; USB SUB-DRIVER INIT ADR .DB CH0SDENABLE ; ENABLE SD CARD SUB-DRIVER .DW CHSD_CFG0 ; SD CARD SUB-DRIVER INIT ADR +; + .ECHO "CH: IO=" + .ECHO CH0BASE + .ECHO "\n" #ENDIF ; #IF (CHCNT >= 2) @@ -113,6 +117,10 @@ CH_CFG1: ; DEVICE 1 .DW CHUSB_CFG1 ; USB SUB-DRIVER INIT ADR .DB CH1SDENABLE ; ENABLE SD CARD SUB-DRIVER .DW CHSD_CFG1 ; SD CARD SUB-DRIVER INIT ADR +; + .ECHO "CH: IO=" + .ECHO CH1BASE + .ECHO "\n" #ENDIF ; #IF ($ - CH_CFGTBL) != (CHCNT * CH_CFGSIZ) @@ -451,6 +459,12 @@ CHUSB_CFG0: .DB 0 ; DEVICE STATUS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + #IF (CH0USBENABLE) + .ECHO "CHUSB: IO=" + .ECHO CH0BASE + .ECHO "\n" + #ENDIF #ENDIF ; #IF (CHCNT >= 2) @@ -461,6 +475,12 @@ CHUSB_CFG1: .DB 0 ; DEVICE STATUS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + #IF (CH1USBENABLE) + .ECHO "CHUSB: IO=" + .ECHO CH1BASE + .ECHO "\n" + #ENDIF #ENDIF ; #IF ($ - CHUSB_CFGTBL) != (CHCNT * CHUSB_CFGSIZ) @@ -1203,6 +1223,12 @@ CHSD_CFG0: .DB 0 ; DEVICE STATUS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + #IF (CH0SDENABLE) + .ECHO "CHSD: IO=" + .ECHO CH0BASE + .ECHO "\n" + #ENDIF #ENDIF ; #IF (CHCNT >= 2) @@ -1213,6 +1239,12 @@ CHSD_CFG1: .DB 0 ; DEVICE STATUS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + #IF (CH1SDENABLE) + .ECHO "CHSD: IO=" + .ECHO CH1BASE + .ECHO "\n" + #ENDIF #ENDIF ; #IF ($ - CHSD_CFGTBL) != (CHCNT * CHSD_CFGSIZ) diff --git a/Source/HBIOS/ctc.asm b/Source/HBIOS/ctc.asm index d7e6e8f1..364b849b 100644 --- a/Source/HBIOS/ctc.asm +++ b/Source/HBIOS/ctc.asm @@ -28,6 +28,8 @@ CTC_TIM256CFG .EQU %00110111 ; CTC TIMER/256 MODE CONFIG #IF (CTCTIMER & (INTMODE != 2)) .ECHO "*** WARNING: CTC TIMER DISABLED -- INTMODE 2 REQUIRED!!!\n" #ENDIF + .ECHO "CTC: IO=" + .ECHO CTCBASE ; #IF (CTCTIMER & (INTMODE == 2)) ; @@ -109,13 +111,24 @@ CTC_DIV .EQU CTCOSC / CTC_PRESCL / TICKFREQ CTC_DIVHI .EQU CTCPRE CTC_DIVLO .EQU (CTC_DIV / CTC_DIVHI) ; - .ECHO "CTC DIVISOR: " + + .ECHO ", TIMER MODE=" + #IF (CTCMODE == CTCMODE_CTR) + .ECHO "COUNTER" + #ENDIF + #IF (CTCMODE == CTCMODE_TIM16) + .ECHO "TIMER/16" + #ENDIF + #IF (CTCMODE == CTCMODE_TIM256) + .ECHO "TIMER/256" + #ENDIF + .ECHO ", DIVISOR=" .ECHO CTC_DIV - .ECHO ", HI: " + .ECHO ", HI=" .ECHO CTC_DIVHI - .ECHO ", LO: " + .ECHO ", LO=" .ECHO CTC_DIVLO - .ECHO "\n" + .ECHO ", INTERRUPTS ENABLED" ; #IF ((CTC_DIV == 0) | (CTC_DIV > $FFFF)) .ECHO "COMPUTED CTC DIVISOR IS UNUSABLE!\n" @@ -134,6 +147,8 @@ CTC_DIVLO .EQU (CTC_DIV / CTC_DIVHI) CTCTIVT .EQU INT_CTC0A + CTCTIMCH ; #ENDIF +; + .ECHO "\n" ; ;================================================================================================== ; CTC PRE-INITIALIZATION diff --git a/Source/HBIOS/cvdu.asm b/Source/HBIOS/cvdu.asm index b5daa791..4bb78210 100644 --- a/Source/HBIOS/cvdu.asm +++ b/Source/HBIOS/cvdu.asm @@ -17,6 +17,8 @@ ;====================================================================== ; CVDU_BASE .EQU $E0 +; + .ECHO "CVDU: MODE=" ; #IF (CVDUMODE == CVDUMODE_ECB) CVDU_KBDDATA .EQU CVDU_BASE + $02 ; KBD CTLR DATA PORT @@ -24,6 +26,7 @@ CVDU_KBDST .EQU CVDU_BASE + $0A ; KBD CTLR STATUS/CMD PORT CVDU_STAT .EQU CVDU_BASE + $04 ; READ M8563 STATUS CVDU_REG .EQU CVDU_BASE + $04 ; SELECT M8563 REGISTER CVDU_DATA .EQU CVDU_BASE + $0C ; READ/WRITE M8563 DATA + .ECHO "ECB" #ENDIF ; #IF (CVDUMODE == CVDUMODE_MBC) @@ -32,7 +35,15 @@ CVDU_KBDST .EQU CVDU_BASE + $03 ; KBD CTLR STATUS/CMD PORT CVDU_STAT .EQU CVDU_BASE + $04 ; READ M8563 STATUS CVDU_REG .EQU CVDU_BASE + $04 ; SELECT M8563 REGISTER CVDU_DATA .EQU CVDU_BASE + $05 ; READ/WRITE M8563 DATA + .ECHO "MBC" #ENDIF +; + .ECHO ", IO=" + .ECHO CVDU_BASE + .ECHO ", KBD MODE=PS/2" + .ECHO ", KBD IO=" + .ECHO CVDU_KBDDATA + .ECHO "\n" ; CVDU_ROWS .EQU 25 CVDU_COLS .EQU 80 diff --git a/Source/HBIOS/dma.asm b/Source/HBIOS/dma.asm index 04ab8e5d..18d0ff8c 100644 --- a/Source/HBIOS/dma.asm +++ b/Source/HBIOS/dma.asm @@ -2,17 +2,31 @@ ; Z80 DMA DRIVER ;================================================================================================== ; +; + .ECHO "DMA: MODE=" +; #IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC)) DMA_IO .EQU DMABASE DMA_CTL .EQU DMABASE + 1 DMA_USEHALF .EQU TRUE + #IF (DMAMODE == DMAMODE_ECB) + .ECHO "ECB" + #ENDIF + #IF (DMAMODE == DMAMODE_MBC) + .ECHO "MBC" + #ENDIF #ENDIF ; #IF (DMAMODE == DMAMODE_DUO) DMA_IO .EQU DMABASE DMA_CTL .EQU DMABASE + 3 DMA_USEHALF .EQU FALSE + .ECHO "DUO" #ENDIF +;S + .ECHO ", IO=" + .ECHO DMA_IO + .ECHO "\n" ; DMA_CONTINUOUS .equ %10111101 ; + Pulse DMA_BYTE .equ %10011101 ; + Pulse diff --git a/Source/HBIOS/ds1501rtc.asm b/Source/HBIOS/ds1501rtc.asm index 4121ebad..5880193d 100644 --- a/Source/HBIOS/ds1501rtc.asm +++ b/Source/HBIOS/ds1501rtc.asm @@ -111,6 +111,12 @@ DS1501RTC_TE .EQU %10000000 DS1501RTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS) + .ECHO "DS1501RTC: RTCIO=" + .ECHO DS1501RTC_BASE + .ECHO ", NVMIO=" + .ECHO DS1501NVM_BASE + .ECHO "\n" + ; RTC Device Initialization Entry DS1501RTC_INIT: diff --git a/Source/HBIOS/ds7rtc.asm b/Source/HBIOS/ds7rtc.asm index 5a0c2c6f..7dd6970c 100644 --- a/Source/HBIOS/ds7rtc.asm +++ b/Source/HBIOS/ds7rtc.asm @@ -22,6 +22,8 @@ DS7_READ .EQU (DS7_DS1307 | DS7_R) ; READ DS7_WRITE .EQU (DS7_DS1307 | DS7_W) ; WRITE ; DS7_CTL .EQU (DS7_OUT | DS7_SQWE | DS7_RATE) +; + .ECHO "DS1307: ENABLED\n" ; ;----------------------------------------------------------------------------- ; DS1307 INITIALIZATION diff --git a/Source/HBIOS/dsrtc.asm b/Source/HBIOS/dsrtc.asm index d3afd65e..7df87f28 100644 --- a/Source/HBIOS/dsrtc.asm +++ b/Source/HBIOS/dsrtc.asm @@ -88,6 +88,8 @@ ; D2 -- -- -- -- -- -- -- -- -- -- -- ; D1 ---- -- -- -- -- -- -- -- -- CLKSEL -- ; D0 RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN -- -- RTC_IN RTC_IN RTC_IN +; + .ECHO "DSRTC: MODE=" ; #IF (DSRTCMODE == DSRTCMODE_STD) ; @@ -113,6 +115,8 @@ DS1d8k .EQU %10100111 ; 1 DOIDE 8K RESISTOR DS2d2k .EQU %10101001 ; 2 DIODES 2K RESISTOR DS2d4k .EQU %10101010 ; 2 DIODES 4K RESISTOR DS2d8k .EQU %10101011 ; 2 DIODES 8K RESISTOR +; + .ECHO "STD" ; #ENDIF ; @@ -129,8 +133,14 @@ DSRTC_MASK .EQU %00001111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT DSRTC_IDLE .EQU %00001000 ; QUIESCENT STATE ; #DEFINE DSRTC_OPRVAL DSRTC_RTCVAL +; + .ECHO "MFPIC" ; #ENDIF +; + .ECHO ", IO=" + .ECHO DSRTC_IO + .ECHO "\n" ; DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW) ; diff --git a/Source/HBIOS/duart.asm b/Source/HBIOS/duart.asm index f49182be..91213874 100644 --- a/Source/HBIOS/duart.asm +++ b/Source/HBIOS/duart.asm @@ -822,6 +822,10 @@ DUART0A_CFG: .DW DUART0_ACR ; IY+6 POINTER TO SHADOW ACR FOR THIS CHIP .DW DUART0ACFG ; IY+8 LINE CONFIGURATION .DB 1 ; IY+10 MULTIPLIER WRT 3.6864MHZ CLOCK +; + .ECHO "DUART: IO=" + .ECHO DUART0BASE + $00 + .ECHO ", CHANNEL A\n" ; DUART_CFGSIZ .EQU $ - DUART_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -835,6 +839,10 @@ DUART0B_CFG: .DW DUART0_ACR ; POINTER TO SHADOW ACR FOR THIS CHIP .DW DUART0BCFG ; LINE CONFIGURATION .DB 1 ; MULTIPLIER WRT 3.6864MHZ CLOCK +; + .ECHO "DUART: IO=" + .ECHO DUART0BASE + $08 + .ECHO ", CHANNEL B\n" ; #IF (DUARTCNT >= 2) ; @@ -848,6 +856,10 @@ DUART1A_CFG: .DW DUART1_ACR ; POINTER TO SHADOW ACR FOR THIS CHIP .DW DUART1ACFG ; LINE CONFIGURATION .DB 1 ; MULTIPLIER WRT 3.6864MHZ CLOCK +; + .ECHO "DUART: IO=" + .ECHO DUART1BASE + $00 + .ECHO ", CHANNEL A\n" ; DUART1B_CFG: ; 2ND DUART MODULE CHANNEL B @@ -859,6 +871,10 @@ DUART1B_CFG: .DW DUART1_ACR ; POINTER TO SHADOW ACR FOR THIS CHIP .DW DUART1BCFG ; LINE CONFIGURATION .DB 1 ; MULTIPLIER WRT 3.6864MHZ CLOCK +; + .ECHO "DUART: IO=" + .ECHO DUART1BASE + $08 + .ECHO ", CHANNEL B\n" ; #ENDIF ; diff --git a/Source/HBIOS/esp.asm b/Source/HBIOS/esp.asm index 0f8d429a..75b4d58b 100644 --- a/Source/HBIOS/esp.asm +++ b/Source/HBIOS/esp.asm @@ -53,6 +53,10 @@ ESP_CFG_IO .EQU 1 ; ESP I/O PORT ESP_CFG_ST .EQU 2 ; ESP STATUS PORT ESP_CFG_RDYMSK .EQU 3 ; ESP READY MASK ESP_CFG_BSYMSK .EQU 4 ; ESP BUSY MASK +; + .ECHO "ESP: IO=" + .ECHO ESP_IOBASE + .ECHO "\n" ; ; GLOBAL ESP INITIALIZATION ; @@ -343,6 +347,8 @@ ESP_STR_UPGRADE .TEXT "!!!UPGRADE REQUIRED!!!$" ; ESPCON_ROWS .EQU 25 ; VGA DISPLAY ROWS ESPCON_COLS .EQU 80 ; VGA DISPLAY COLS +; + .ECHO "ESPCON: ENABLED\n" ; ; ; @@ -685,7 +691,8 @@ ESPSER0_CFG: .DB ESP_0_RDY ; ESP READY BIT MASK .DB ESP_0_BUSY ; ESP BUSY BIT MASK .DW ESPSER_LINECFG ; LINE CONFIGURATION - +; + .ECHO "ESPSER: DEVICE=0\n" ; ESPSER1_CFG: .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) @@ -694,6 +701,8 @@ ESPSER1_CFG: .DB ESP_1_RDY ; ESP READY BIT MASK .DB ESP_1_BUSY ; ESP BUSY BIT MASK .DW ESPSER_LINECFG ; LINE CONFIGURATION +; + .ECHO "ESPSER: DEVICE=1\n" ; ; ; diff --git a/Source/HBIOS/fd.asm b/Source/HBIOS/fd.asm index 84933714..8512dd71 100644 --- a/Source/HBIOS/fd.asm +++ b/Source/HBIOS/fd.asm @@ -14,6 +14,7 @@ FDC_DATA .EQU $37 ; 8272 DATA PORT FDC_DIR .EQU $38 ; DATA INPUT REGISTER FDC_DOR .EQU $3A ; DIGITAL OUTPUT REGISTER (LATCH) FDC_DMA .EQU $3C ; PSEUDO DMA DATA PORT + #DEFINE FDMODE_STR "DIO" #ENDIF #IF (FDMODE = FDMODE_ZETA2) FDC_MSR .EQU $30 ; 8272 MAIN STATUS REGISTER @@ -21,6 +22,7 @@ FDC_DATA .EQU $31 ; 8272 DATA PORT FDC_DOR .EQU $38 ; DIGITAL OUTPUT REGISTER FDC_DCR .EQU $28 ; CONFIGURATION CONTROL REGISTER FDC_TC .EQU $38 ; TERMINAL COUNT (W/ DACK) + #DEFINE FDMODE_STR "ZETA2" #ENDIF #IF (FDMODE == FDMODE_DIDE) FDC_BID .EQU $20 ; IO RANGE 20H-3FH @@ -31,6 +33,7 @@ FDC_DCR .EQU $2D ; DCR FDC_DACK .EQU $3C ; DACK FDC_TC .EQU $3D ; TERMINAL COUNT (W/ DACK) FDC_DMA .EQU $3C ; NOT USED BY DIDE + #DEFINE FDMODE_STR "DIDE" #ENDIF #IF (FDMODE == FDMODE_N8) FDC_MSR .EQU $8C ; 8272 MAIN STATUS REGISTER @@ -40,11 +43,13 @@ FDC_DCR .EQU $91 ; DCR FDC_DACK .EQU $90 ; DACK FDC_TC .EQU $93 ; TERMINAL COUNT (W/ DACK) FDC_DMA .EQU $3C ; NOT USED BY N8 + #DEFINE FDMODE_STR "N8" #ENDIF #IF (FDMODE == FDMODE_RCSMC) FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER FDC_DATA .EQU $51 ; 8272 DATA PORT FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER (LATCH) + #DEFINE FDMODE_STR "RCSMC" #ENDIF #IF (FDMODE == FDMODE_RCWDC) FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER @@ -52,6 +57,7 @@ FDC_DATA .EQU $51 ; 8272 DATA PORT FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER FDC_DCR .EQU $48 ; CONFIGURATION CONTROL REGISTER FDC_TC .EQU $58 ; TERMINAL COUNT (W/ DACK) + #DEFINE FDMODE_STR "RCWDC" #ENDIF #IF (FDMODE == FDMODE_DYNO) FDC_BASE .EQU $84 @@ -60,6 +66,7 @@ FDC_DATA .EQU FDC_BASE + $01 ; 8272 DATA PORT FDC_DOR .EQU FDC_BASE + $02 ; DIGITAL OUTPUT REGISTER FDC_DCR .EQU FDC_BASE + $03 ; CONFIGURATION CONTROL REGISTER FDC_TC .EQU FDC_BASE + $02 ; TERMINAL COUNT (W/ DACK) + #DEFINE FDMODE_STR "DYNO" #ENDIF #IF (FDMODE == FDMODE_EPFDC) FDC_MSR .EQU $48 ; 8272 MAIN STATUS REGISTER @@ -67,6 +74,7 @@ FDC_DATA .EQU $49 ; 8272 DATA PORT FDC_DOR .EQU $4A ; DIGITAL OUTPUT REGISTER FDC_DCR .EQU $4B ; CONFIGURATION CONTROL REGISTER FDC_TC .EQU $4C ; TERMINAL COUNT (W/ DACK) + #DEFINE FDMODE_STR "EPFDC" #ENDIF #IF (FDMODE == FDMODE_MBC) FDC_MSR .EQU $30 ; 8272 MAIN STATUS REGISTER @@ -74,8 +82,10 @@ FDC_DATA .EQU $31 ; 8272 DATA PORT FDC_DOR .EQU $36 ; DIGITAL OUTPUT REGISTER FDC_DCR .EQU $35 ; CONFIGURATION CONTROL REGISTER FDC_TC .EQU $37 ; TERMINAL COUNT (W/ DACK) + #DEFINE FDMODE_STR "MBC" #ENDIF ; +; ; DISK OPERATIONS ; DOP_READ .EQU 0 ; READ OPERATION @@ -133,6 +143,33 @@ FD_CFGTBL: .DB 0 ; HOST SECTOR .DB 0 ; HOST HEAD .DB FD0TYPE ; DRIVE TYPE +; + .ECHO "FD: MODE=" + .ECHO FDMODE_STR + .ECHO ", IO=" + .ECHO FDC_MSR + .ECHO ", DRIVE 0" + .ECHO ", TYPE=" + #IF (FD0TYPE == FDT_NONE + .ECHO "NONE" + #ENDIF + #IF (FD0TYPE == FDT_3DD + .ECHO "3.5\" DD" + #ENDIF + #IF (FD0TYPE == FDT_3HD + .ECHO "3.5\" HD" + #ENDIF + #IF (FD0TYPE == FDT_5DD + .ECHO "5.25\" DD" + #ENDIF + #IF (FD0TYPE == FDT_5HD + .ECHO "5.25\" HD" + #ENDIF + #IF (FD0TYPE == FDT_8 + .ECHO "8\" DD" + #ENDIF + .ECHO "\n" +; #IF (FD_DEVCNT >= 2) ; DEVICE 1, PRIMARY SLAVE .DB 1 ; DRIVER DEVICE NUMBER @@ -143,6 +180,32 @@ FD_CFGTBL: .DB 0 ; HOST SECTOR .DB 0 ; HOST HEAD .DB FD1TYPE ; DRIVE TYPE +; + .ECHO "FD: MODE=" + .ECHO FDMODE_STR + .ECHO ", IO=" + .ECHO FDC_MSR + .ECHO ", DRIVE 1" + .ECHO ", TYPE=" + #IF (FD1TYPE == FDT_NONE + .ECHO "NONE" + #ENDIF + #IF (FD1TYPE == FDT_3DD + .ECHO "3.5\" DD" + #ENDIF + #IF (FD1TYPE == FDT_3HD + .ECHO "3.5\" HD" + #ENDIF + #IF (FD1TYPE == FDT_5DD + .ECHO "5.25\" DD" + #ENDIF + #IF (FD1TYPE == FDT_5HD + .ECHO "5.25\" HD" + #ENDIF + #IF (FD1TYPE == FDT_8 + .ECHO "8\" DD" + #ENDIF + .ECHO "\n" #ENDIF ; #IF ($ - FD_CFGTBL) != (FD_DEVCNT * FD_CFGSIZ) diff --git a/Source/HBIOS/gdc.asm b/Source/HBIOS/gdc.asm index be5f3f2d..865f08c8 100644 --- a/Source/HBIOS/gdc.asm +++ b/Source/HBIOS/gdc.asm @@ -36,16 +36,33 @@ GDC_COLS .EQU 80 ; *** TODO: CGA AND EGA ARE PLACEHOLDERS. THESE EQUATES SHOULD ; BE USED TO ALLOW FOR MULTIPLE MONITOR TIMINGS AND/OR FONT ; DEFINITIONS. +; + .ECHO "GDC: MODE=" +; +#IF (GDCMODE == GDCMODE_ECB) + .ECHO "ECB" +#ENDIF +#IF (GDCMODE == GDCMODE_RPH) + .ECHO "RPH" +#ENDIF +; + .ECHO ", DISPLAY=" ; #IF (GDCMON == GDCMON_CGA) #DEFINE USEFONTCGA #DEFINE GDC_FONT FONTCGA + .ECHO "CGA" #ENDIF ; #IF (GDCMON == GDCMON_EGA) #DEFINE USEFONT8X16 #DEFINE GDC_FONT FONT8X16 + .ECHO "EGA" #ENDIF +; + .ECHO ", IO=" + .ECHO GDC_BASE + .ECHO "\n" ; TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER ; @@ -70,7 +87,7 @@ GDC_INIT: #ENDIF #IF (GDCMON == GDCMON_EGA) PRTS(" EGA$") -#ENDIF +#ENDIF ; PRTS(" IO=0x$") LD A,GDC_BASE diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index bec7254f..f967f72f 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -217,6 +217,24 @@ RTCDEF .SET RTCDEF | %00001000 ; INITIAL SPEED LOW ; ; ; +#IF (FPLED_ENABLE | FPSW_ENABLE) + .ECHO "FP: " + #IF (FPLED_ENABLE) + .ECHO "LEDIO=" + .ECHO FPLED_IO + #ENDIF + #IF (FPLED_ENABLE & FPSW_ENABLE) + .ECHO ", " + #ENDIF + #IF (FPSW_ENABLE) + .ECHO "SWIO=" + .ECHO FPSW_IO + #ENDIF + .ECHO "\n" +#ENDIF +; +; +; #IFNDEF APPBOOT ; .ORG 0 diff --git a/Source/HBIOS/hdsk.asm b/Source/HBIOS/hdsk.asm index 2349de36..2fa6fddf 100644 --- a/Source/HBIOS/hdsk.asm +++ b/Source/HBIOS/hdsk.asm @@ -21,6 +21,12 @@ HDSK_CFGSIZ .EQU 6 ; SIZE OF CFG TBL ENTRIES HDSK_DEV .EQU 0 ; OFFSET OF DEVICE NUMBER (BYTE) HDSK_STAT .EQU 1 ; OFFSET OF STATUS (BYTE) HDSK_LBA .EQU 2 ; OFFSET OF LBA (DWORD) +; + .ECHO "HDSK: IO=" + .ECHO HDSK_IO + .ECHO ", DEVICE COUNT=" + .ECHO HDSK_DEVCNT + .ECHO "\n" ; HDSK_CFGTBL: ; DEVICE 0 diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm index 2c80dd08..a086456a 100644 --- a/Source/HBIOS/ide.asm +++ b/Source/HBIOS/ide.asm @@ -213,6 +213,27 @@ IDE_DEV0M: ; DEVICE 0, MASTER .DB IDE0DATLO ; IO BASE ADDRESS .DB IDE0DATHI ; IO BASE ADDRESS .DW IDE_DEV0S ; PARTNER +; + .ECHO "IDE: MODE=" + #IF (IDE0MODE == IDEMODE_NONE) + .ECHO "NONE" + #ENDIF + #IF (IDE0MODE == IDEMODE_DIO) + .ECHO "DIO" + #ENDIF + #IF (IDE0MODE == IDEMODE_DIDE) + .ECHO "DIDE" + #ENDIF + #IF (IDE0MODE == IDEMODE_MK4) + .ECHO "MK4" + #ENDIF + #IF (IDE0MODE == IDEMODE_RC) + .ECHO "RC" + #ENDIF + .ECHO ", IO=" + .ECHO IDE0BASE + .ECHO ", MASTER" + .ECHO "\n" ; IDE_DEV0S: ; DEVICE 0, SLAVE .DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY) @@ -227,6 +248,27 @@ IDE_DEV0S: ; DEVICE 0, SLAVE .DB IDE0DATLO ; IO BASE ADDRESS .DB IDE0DATHI ; IO BASE ADDRESS .DW IDE_DEV0M ; PARTNER +; + .ECHO "IDE: MODE=" + #IF (IDE0MODE == IDEMODE_NONE) + .ECHO "NONE" + #ENDIF + #IF (IDE0MODE == IDEMODE_DIO) + .ECHO "DIO" + #ENDIF + #IF (IDE0MODE == IDEMODE_DIDE) + .ECHO "DIDE" + #ENDIF + #IF (IDE0MODE == IDEMODE_MK4) + .ECHO "MK4" + #ENDIF + #IF (IDE0MODE == IDEMODE_RC) + .ECHO "RC" + #ENDIF + .ECHO ", IO=" + .ECHO IDE0BASE + .ECHO ", SLAVE" + .ECHO "\n" #ENDIF ; #IF (IDECNT >= 2) @@ -244,6 +286,27 @@ IDE_DEV1M: ; DEVICE 1, MASTER .DB IDE1DATLO ; IO BASE ADDRESS .DB IDE1DATHI ; IO BASE ADDRESS .DW IDE_DEV1S ; PARTNER +; + .ECHO "IDE: MODE=" + #IF (IDE1MODE == IDEMODE_NONE) + .ECHO "NONE" + #ENDIF + #IF (IDE1MODE == IDEMODE_DIO) + .ECHO "DIO" + #ENDIF + #IF (IDE1MODE == IDEMODE_DIDE) + .ECHO "DIDE" + #ENDIF + #IF (IDE1MODE == IDEMODE_MK4) + .ECHO "MK4" + #ENDIF + #IF (IDE1MODE == IDEMODE_RC) + .ECHO "RC" + #ENDIF + .ECHO ", IO=" + .ECHO IDE1BASE + .ECHO ", MASTER" + .ECHO "\n" ; IDE_DEV1S: ; DEVICE 1, SLAVE .DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY) @@ -258,6 +321,27 @@ IDE_DEV1S: ; DEVICE 1, SLAVE .DB IDE1DATLO ; IO BASE ADDRESS .DB IDE1DATHI ; IO BASE ADDRESS .DW IDE_DEV1M ; PARTNER +; + .ECHO "IDE: MODE=" + #IF (IDE1MODE == IDEMODE_NONE) + .ECHO "NONE" + #ENDIF + #IF (IDE1MODE == IDEMODE_DIO) + .ECHO "DIO" + #ENDIF + #IF (IDE1MODE == IDEMODE_DIDE) + .ECHO "DIDE" + #ENDIF + #IF (IDE1MODE == IDEMODE_MK4) + .ECHO "MK4" + #ENDIF + #IF (IDE1MODE == IDEMODE_RC) + .ECHO "RC" + #ENDIF + .ECHO ", IO=" + .ECHO IDE1BASE + .ECHO ", SLAVE" + .ECHO "\n" #ENDIF ; #IF (IDECNT >= 3) @@ -275,6 +359,27 @@ IDE_DEV2M: ; DEVICE 2, MASTER .DB IDE2DATLO ; IO BASE ADDRESS .DB IDE2DATHI ; IO BASE ADDRESS .DW IDE_DEV2S ; PARTNER +; + .ECHO "IDE: MODE=" + #IF (IDE2MODE == IDEMODE_NONE) + .ECHO "NONE" + #ENDIF + #IF (IDE2MODE == IDEMODE_DIO) + .ECHO "DIO" + #ENDIF + #IF (IDE2MODE == IDEMODE_DIDE) + .ECHO "DIDE" + #ENDIF + #IF (IDE2MODE == IDEMODE_MK4) + .ECHO "MK4" + #ENDIF + #IF (IDE2MODE == IDEMODE_RC) + .ECHO "RC" + #ENDIF + .ECHO ", IO=" + .ECHO IDE2BASE + .ECHO ", MASTER" + .ECHO "\n" ; IDE_DEV2S: ; DEVICE 2, SLAVE .DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY) @@ -289,6 +394,27 @@ IDE_DEV2S: ; DEVICE 2, SLAVE .DB IDE2DATLO ; IO BASE ADDRESS .DB IDE2DATHI ; IO BASE ADDRESS .DW IDE_DEV1M ; PARTNER +; + .ECHO "IDE: MODE=" + #IF (IDE2MODE == IDEMODE_NONE) + .ECHO "NONE" + #ENDIF + #IF (IDE2MODE == IDEMODE_DIO) + .ECHO "DIO" + #ENDIF + #IF (IDE2MODE == IDEMODE_DIDE) + .ECHO "DIDE" + #ENDIF + #IF (IDE2MODE == IDEMODE_MK4) + .ECHO "MK4" + #ENDIF + #IF (IDE2MODE == IDEMODE_RC) + .ECHO "RC" + #ENDIF + .ECHO ", IO=" + .ECHO IDE2BASE + .ECHO ", SLAVE" + .ECHO "\n" #ENDIF ; #IF ($ - IDE_CFGTBL) != (IDE_DEVCNT * IDE_CFGSIZ) diff --git a/Source/HBIOS/imm.asm b/Source/HBIOS/imm.asm index d9076758..d85a76cd 100644 --- a/Source/HBIOS/imm.asm +++ b/Source/HBIOS/imm.asm @@ -1525,6 +1525,17 @@ IMM0_CFG: ; DEVICE 0 .DB IMM0BASE ; IO BASE ADDRESS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + .ECHO "IMM: MODE=" + #IF (IMMMODE == IMMMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (IMMMODE == IMMMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO IMM0BASE + .ECHO "\n" #ENDIF ; #IF (IMMCNT >= 2) @@ -1536,6 +1547,17 @@ IMM1_CFG: ; DEVICE 1 .DB IMM1BASE ; IO BASE ADDRESS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + .ECHO "IMM: MODE=" + #IF (IMMMODE == IMMMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (IMMMODE == IMMMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO IMM1BASE + .ECHO "\n" #ENDIF ; #IF ($ - IMM_CFG) != (IMMCNT * IMM_CFGSIZ) diff --git a/Source/HBIOS/intrtc.asm b/Source/HBIOS/intrtc.asm index cbb2184f..8d65e2e2 100644 --- a/Source/HBIOS/intrtc.asm +++ b/Source/HBIOS/intrtc.asm @@ -4,6 +4,8 @@ ;================================================================================================== ; INTRTC_BUFSIZ .EQU 6 ; SIX BYTE BUFFER (YYMMDDHHMMSS) +; + .ECHO "INTRTC: ENABLED\n" ; ; RTC DEVICE INITIALIZATION ENTRY ; diff --git a/Source/HBIOS/kbd.asm b/Source/HBIOS/kbd.asm index 7c8b7fac..113c8aa1 100644 --- a/Source/HBIOS/kbd.asm +++ b/Source/HBIOS/kbd.asm @@ -55,6 +55,8 @@ KBD_RSTATE .DB 0 ; STATE BITS FOR "RIGHT" KEYS KBD_STATUS .DB 0 ; CURRENT STATUS BITS (SEE ABOVE) KBD_REPEAT .DB 0 ; CURRENT REPEAT RATE KBD_IDLE .DB 0 ; IDLE COUNT +; + .ECHO "KBD: ENABLED\n" ; ;__________________________________________________________________________________________________ ; KEYBOARD INITIALIZATION diff --git a/Source/HBIOS/lpt.asm b/Source/HBIOS/lpt.asm index 0b75fae5..73f26b5e 100644 --- a/Source/HBIOS/lpt.asm +++ b/Source/HBIOS/lpt.asm @@ -346,10 +346,10 @@ LPT_DETECT: LD A,$A5 ; TEST VALUE OUT (C),A ; PUSH VALUE TO PORT IN A,(C) ; GET PORT VALUE -#IF (LPTTRACE >= 3) + #IF (LPTTRACE >= 3) CALL PC_SPACE CALL PRTHEXBYTE -#ENDIF + #ENDIF CP $A5 ; CHECK FOR TEST VALUE JR Z,LPT_DETECT1 ; FOUND IT LD A,LPTMODE_NONE ; NOT FOUND @@ -420,6 +420,17 @@ LPT0_CFG: .DB 0 ; MODULE ID .DB LPT0BASE ; BASE PORT .DW 0 ; LINE CONFIGURATION +; + .ECHO "LPT: MODE=" + #IF (LPTMODE == LPTMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (LPTMODE == LPTMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO LPT0BASE + .ECHO "\n" ; LPT_CFGSIZ .EQU $ - LPT_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -432,6 +443,17 @@ LPT1_CFG: .DB 1 ; MODULE ID .DB LPT1BASE ; BASE PORT .DW 0 ; LINE CONFIGURATION +; + .ECHO "LPT: MODE=" + #IF (LPTMODE == LPTMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (LPTMODE == LPTMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO LPT1BASE + .ECHO "\n" ; #ENDIF ; diff --git a/Source/HBIOS/md.asm b/Source/HBIOS/md.asm index b6f806a0..6e8adbb8 100644 --- a/Source/HBIOS/md.asm +++ b/Source/HBIOS/md.asm @@ -39,6 +39,8 @@ MD_CFGTBL: .DW 0,0 ; CURRENT LBA .DB MID_MDRAM ; DEVICE MEDIA ID .DB MD_ARAM ; DEVICE ATTRIBUTE +; + .ECHO "MD: TYPE=RAM\n" #ENDIF ; #IF (MDROM) @@ -48,6 +50,8 @@ MD_CFGTBL: .DW 0,0 ; CURRENT LBA .DB MID_MDROM ; DEVICE MEDIA ID .DB MD_AROM ; DEVICE ATTRIBUTE +; + .ECHO "MD: TYPE=ROM\n" #ENDIF ; MD_DEVCNT .EQU ($ - MD_CFGTBL) / MD_CFGSIZ diff --git a/Source/HBIOS/pcf.asm b/Source/HBIOS/pcf.asm index 266f23c3..ab17f85c 100644 --- a/Source/HBIOS/pcf.asm +++ b/Source/HBIOS/pcf.asm @@ -93,6 +93,10 @@ PCF_PINTO .EQU 65000 PCF_ACKTO .EQU 65000 PCF_BBTO .EQU 65000 PCF_LABDLY .EQU 65000 +; + .ECHO "PCF: IO=" + .ECHO PCF_BASE + .ECHO "\n" ; ; DATA PORT REGISTERS ; diff --git a/Source/HBIOS/pio.asm b/Source/HBIOS/pio.asm index 18016f4f..1dc823a9 100644 --- a/Source/HBIOS/pio.asm +++ b/Source/HBIOS/pio.asm @@ -307,6 +307,10 @@ PIO0A_CFG: .DB PIO0A_DAT ; DATA PORT .DW DEFSERCFG ; LINE CONFIGURATION .DW PIO0A_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "PIO: IO=" + .ECHO PIO0BASE + .ECHO ", CHANNEL A\n" ; PIO_CFGSIZ .EQU $ - PIO_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -319,6 +323,10 @@ PIO0B_CFG: .DB PIO0B_DAT ; DATA PORT .DW DEFSERCFG ; LINE CONFIGURATION .DW PIO0B_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "PIO: IO=" + .ECHO PIO0BASE + .ECHO ", CHANNEL B\n" ; #IF (PIOCNT >= 2) ; @@ -331,6 +339,10 @@ PIO1A_CFG: .DB PIO1A_DAT ; DATA PORT .DW DEFSERCFG ; LINE CONFIGURATION .DW PIO1A_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "PIO: IO=" + .ECHO PIO1BASE + .ECHO ", CHANNEL A\n" ; ; PIO1 CHANNEL B PIO1B_CFG: @@ -341,6 +353,10 @@ PIO1B_CFG: .DB PIO1B_DAT ; DATA PORT .DW DEFSERCFG ; LINE CONFIGURATION .DW PIO1B_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "PIO: IO=" + .ECHO PIO1BASE + .ECHO ", CHANNEL B\n" ; #ENDIF ; diff --git a/Source/HBIOS/pkd.asm b/Source/HBIOS/pkd.asm index 14d3969f..a837155c 100644 --- a/Source/HBIOS/pkd.asm +++ b/Source/HBIOS/pkd.asm @@ -65,6 +65,10 @@ PKD_CMD_CLK .EQU %00100000 ; SET CLK PRESCALE PKD_CMD_FIFO .EQU %01000000 ; READ FIFO ; PKD_PRESCL .EQU PKDOSC/100000 ; PRESCALER +; + .ECHO "PKD: IO=" + .ECHO PKDPPIBASE + .ECHO "\n" ; ;__PKD_PREINIT_______________________________________________________________________________________ ; diff --git a/Source/HBIOS/ppa.asm b/Source/HBIOS/ppa.asm index 9af70614..e13493d8 100644 --- a/Source/HBIOS/ppa.asm +++ b/Source/HBIOS/ppa.asm @@ -139,7 +139,7 @@ PPA_LBA .EQU 8 ; OFFSET OF LBA (DWORD) ; ; INCLUDE MG014 NIBBLE MAP FOR MG014 MODE ; -#IF (IMMMODE == IMMMODE_MG014) +#IF (PPAMODE == IMMMODE_MG014) #DEFINE MG014_MAP #ENDIF ; @@ -1385,6 +1385,17 @@ PPA0_CFG: ; DEVICE 0 .DB PPA0BASE ; IO BASE ADDRESS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + .ECHO "PPA: MODE=" + #IF (PPAMODE == PPAMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (PPAMODE == PPAMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO PPA0BASE + .ECHO "\n" #ENDIF ; #IF (PPACNT >= 2) @@ -1396,6 +1407,17 @@ PPA1_CFG: ; DEVICE 1 .DB PPA1BASE ; IO BASE ADDRESS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + .ECHO "PPA: MODE=" + #IF (PPAMODE == PPAMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (PPAMODE == PPAMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO PPA1BASE + .ECHO "\n" #ENDIF ; #IF ($ - PPA_CFG) != (PPACNT * PPA_CFGSIZ) diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm index 5449899d..8b027bfd 100644 --- a/Source/HBIOS/ppide.asm +++ b/Source/HBIOS/ppide.asm @@ -229,6 +229,11 @@ PPIDE_DEV0M: ; DEVICE 0, MASTER .DB PPIDE0BASE+2 ; CTL .DB PPIDE0BASE+3 ; PPI .DW PPIDE_DEV0S ; PARTNER +; + .ECHO "PPIDE: IO=" + .ECHO PPIDE0BASE + .ECHO ", MASTER" + .ECHO "\n" ; PPIDE_DEV0S: ; DEVICE 0, SLAVE .DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY) @@ -242,6 +247,11 @@ PPIDE_DEV0S: ; DEVICE 0, SLAVE .DB PPIDE0BASE+2 ; CTL .DB PPIDE0BASE+3 ; PPI .DW PPIDE_DEV0M ; PARTNER +; + .ECHO "PPIDE: IO=" + .ECHO PPIDE0BASE + .ECHO ", SLAVE" + .ECHO "\n" ; #ENDIF ; @@ -259,6 +269,11 @@ PPIDE_DEV1M: ; DEVICE 1, MASTER .DB PPIDE1BASE+2 ; CTL .DB PPIDE1BASE+3 ; PPI .DW PPIDE_DEV1S ; PARTNER +; + .ECHO "PPIDE: IO=" + .ECHO PPIDE1BASE + .ECHO ", MASTER" + .ECHO "\n" ; PPIDE_DEV1S: ; DEVICE 1, SLAVE .DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY) @@ -272,6 +287,11 @@ PPIDE_DEV1S: ; DEVICE 1, SLAVE .DB PPIDE1BASE+2 ; CTL .DB PPIDE1BASE+3 ; PPI .DW PPIDE_DEV1M ; PARTNER +; + .ECHO "PPIDE: IO=" + .ECHO PPIDE1BASE + .ECHO ", SLAVE" + .ECHO "\n" ; #ENDIF ; @@ -289,6 +309,11 @@ PPIDE_DEV2M: ; DEVICE 2, MASTER .DB PPIDE2BASE+2 ; CTL .DB PPIDE2BASE+3 ; PPI .DW PPIDE_DEV2S ; PARTNER +; + .ECHO "PPIDE: IO=" + .ECHO PPIDE2BASE + .ECHO ", MASTER" + .ECHO "\n" ; PPIDE_DEV2S: ; DEVICE 2, SLAVE .DB $FE ; DRIVER DEVICE NUMBER (FILLED DYNAMICALLY) @@ -302,6 +327,11 @@ PPIDE_DEV2S: ; DEVICE 2, SLAVE .DB PPIDE2BASE+2 ; CTL .DB PPIDE2BASE+3 ; PPI .DW PPIDE_DEV2M ; PARTNER +; + .ECHO "PPIDE: IO=" + .ECHO PPIDE2BASE + .ECHO ", SLAVE" + .ECHO "\n" ; #ENDIF ; diff --git a/Source/HBIOS/ppk.asm b/Source/HBIOS/ppk.asm index 6672782b..3c8dbb0a 100644 --- a/Source/HBIOS/ppk.asm +++ b/Source/HBIOS/ppk.asm @@ -59,6 +59,8 @@ PPK_STATUS .DB 0 ; CURRENT STATUS BITS (SEE ABOVE) PPK_REPEAT .DB 0 ; CURRENT REPEAT RATE PPK_IDLE .DB 0 ; IDLE COUNT PPK_WAITTO .DW 0 ; TIMEOUT WAIT LOOP COUNT (COMPUTED IN INIT) +; + .ECHO "PPK: ENABLED\n" ; ;__________________________________________________________________________________________________ ; KEYBOARD INITIALIZATION diff --git a/Source/HBIOS/ppp.asm b/Source/HBIOS/ppp.asm index b998ec08..72d2ab53 100644 --- a/Source/HBIOS/ppp.asm +++ b/Source/HBIOS/ppp.asm @@ -8,6 +8,10 @@ PPP_IO .EQU PPPBASE + 0 ; PPP DATA I/O (PPI PORT A) PPP_CTL .EQU PPPBASE + 2 ; PPP CTL LINES (PPI PORT C) PPP_PPICTL .EQU PPPBASE + 3 ; PPI CONTROL PORT +; + .ECHO "PPP: IO=" + .ECHO PPP_IO + .ECHO "\n" ; ; COMMAND BYTES ; @@ -248,6 +252,8 @@ PPP_FWVER .DB $00, $00, $00, $00 ; MMNNBBB (M=MAJOR, N=MINOR, B=BUILD) ; PPPCON_ROWS .EQU 37 ; PROPELLER VGA DISPLAY ROWS (40 - 3 STATUS LINES) PPPCON_COLS .EQU 80 ; PROPELLER VGA DISPLAY COLS +; + .ECHO "PPPCON: ENABLED\n" ; PPPCON_INIT: CALL NEWLINE @@ -413,6 +419,8 @@ PPPSD_CFGTBL: #ENDIF ; .DB $FF ; END MARKER +; + .ECHO "PPPSD: ENABLED\n" ; ; SD CARD INITIALIZATION ; diff --git a/Source/HBIOS/prp.asm b/Source/HBIOS/prp.asm index 738e971a..f857c5fc 100644 --- a/Source/HBIOS/prp.asm +++ b/Source/HBIOS/prp.asm @@ -6,6 +6,10 @@ ; TODO: ; PRP_IOBASE .EQU $A8 +; + .ECHO "PRP: IO=" + .ECHO PRP_IOBASE + .ECHO "\n" ; ; GLOBAL PROPIO INITIALIZATION ; @@ -119,6 +123,8 @@ PRPCON_DSPRDY .EQU $10 ; BIT SET WHEN DISPLAY BUF IS READY FOR A BYTE (BUF EMPT ; PRPCON_ROWS .EQU 37 ; PROPELLER VGA DISPLAY ROWS (40 - 3 STATUS LINES) PRPCON_COLS .EQU 80 ; PROPELLER VGA DISPLAY COLS +; + .ECHO "PRPCON: ENABLED\n" ; ; ; @@ -310,6 +316,8 @@ PRPSD_CFGTBL: #ENDIF ; .DB $FF ; END MARKER +; + .ECHO "PRPSD: ENABLED\n" ; ; SD CARD INITIALIZATION ; diff --git a/Source/HBIOS/rf.asm b/Source/HBIOS/rf.asm index f9bc94f1..29d9dabc 100644 --- a/Source/HBIOS/rf.asm +++ b/Source/HBIOS/rf.asm @@ -42,6 +42,11 @@ RF_CFGTBL: .DW 0,0 ; CURRENT LBA .DB 0 ; UNUSED .DB RF_U0IO ; DEVICE BASE ADDR +; + .ECHO "RF: IO=" + .ECHO RF_U0IO + .ECHO "\n" +; #IF (RF_DEVCNT > 1) ; DEVICE 1 .DB 1 ; DEVICE NUMBER @@ -50,6 +55,11 @@ RF_CFGTBL: .DB 0 ; UNUSED .DB RF_U1IO ; DEVICE BASE ADDR #ENDIF +; + .ECHO "RF: IO=" + .ECHO RF_U1IO + .ECHO "\n" +; #IF (RF_DEVCNT > 2) ; DEVICE 2 .DB 2 ; DRIVER DEVICE NUMBER @@ -58,13 +68,23 @@ RF_CFGTBL: .DB 0 ; UNUSED .DB RF_U2IO ; DEVICE BASE ADDR #ENDIF -; ; DEVICE 3 +; + .ECHO "RF: IO=" + .ECHO RF_U2IO + .ECHO "\n" +; #IF (RF_DEVCNT > 3) + ; DEVICE 3 .DB 3 ; DEVICE NUMBER .DB 0 ; DEVICE STATUS .DW 0,0 ; CURRENT LBA .DB 0 ; UNUSED .DB RF_U3IO ; DEVICE BASE ADDR +; + .ECHO "RF: IO=" + .ECHO RF_U3IO + .ECHO "\n" +; #ENDIF ; #IF ($ - RF_CFGTBL) != (RF_DEVCNT * RF_CFGSIZ) diff --git a/Source/HBIOS/rp5rtc.asm b/Source/HBIOS/rp5rtc.asm index df74a42d..fe1d5e90 100644 --- a/Source/HBIOS/rp5rtc.asm +++ b/Source/HBIOS/rp5rtc.asm @@ -55,6 +55,10 @@ MODE_RAM1 .EQU 3 MD_TIME .EQU 8 MD_ALRM .EQU 4 + .ECHO "RP5C01: IO=" + .ECHO RP5RTC_REG + .ECHO "\n" + RP5RTC_INIT: LD A, (RTC_DISPACT) ; RTC DISPATCHER ALREADY SET? OR A ; SET FLAGS diff --git a/Source/HBIOS/scon.asm b/Source/HBIOS/scon.asm index 0d3d8750..9a32457f 100644 --- a/Source/HBIOS/scon.asm +++ b/Source/HBIOS/scon.asm @@ -15,6 +15,10 @@ SCON_DSPRDY .EQU %00000100 ; SCON_COLS .EQU 80 SCON_ROWS .EQU 40 +; + .ECHO "SCON: IO=" + .ECHO SCON_IOBASE + .ECHO "\n" ; ; ; diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index 9b850850..d79a4c5f 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -116,6 +116,8 @@ SD_NOPULLUP .EQU TRUE ; ASSUME NO PULLUP ; SD_DEVCNT .EQU SDCNT ; SET SD_DEVCNT TO SDCNT CONFIG VAR +; + .ECHO "SD: MODE=" ; #IF (SDMODE == SDMODE_JUHA) ; JUHA MINI-BOARD SD_DEVMAX .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) @@ -129,6 +131,7 @@ SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU) SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS + .ECHO "JUHA" ; RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE #ENDIF @@ -145,6 +148,7 @@ SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU) SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS + .ECHO "N8" ; RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE #ENDIF @@ -159,6 +163,7 @@ SD_CNTR .EQU Z180_CNTR SD_TRDR .EQU Z180_TRDR SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS + .ECHO "CSIO" ; RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE #ENDIF @@ -179,6 +184,7 @@ SD_DI .EQU %00000001 ; PPIC:0 IS DATA IN (CARD <- CPU) SD_DO .EQU %10000000 ; PPIB:7 IS DATA OUT (CARD -> CPU) SD_IOBASE .EQU SD_PPIBASE ; IOBASE SD_INVCS .EQU TRUE ; INVERT CS + .ECHO "PPI" #ENDIF ; #IF (SDMODE == SDMODE_UART) @@ -193,6 +199,7 @@ SD_DI .EQU %00000001 ; UART MCR:0 IS DATA IN (CARD <- CPU) SD_DO .EQU %00100000 ; UART MSR:5 IS DATA OUT (CARD -> CPU) SD_IOBASE .EQU UARTIOB ; IOBASE SD_INVCS .EQU TRUE ; INVERT CS + .ECHO "UART" #ENDIF ; #IF (SDMODE == SDMODE_DSD) ; DUAL SD @@ -208,6 +215,7 @@ SD_DI .EQU %00000001 ; RTC:6 IS DATA IN (CARD <- CPU) SD_DO .EQU %00000001 ; RTC:0 IS DATA OUT (CARD -> CPU) SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS + .ECHO "DSD" #ENDIF ; #IF (SDMODE == SDMODE_MK4) ; MARK IV (CSIO STYLE INTERFACE) @@ -219,6 +227,7 @@ SD_CNTR .EQU Z180_CNTR SD_TRDR .EQU Z180_TRDR SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS + .ECHO "MK4" #ENDIF ; #IF (SDMODE == SDMODE_SC) ; SC @@ -232,9 +241,16 @@ SD_CNTR .EQU Z180_CNTR SD_TRDR .EQU Z180_TRDR SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU TRUE ; INVERT CS + .ECHO "SC" ; RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE #ENDIF +; + .ECHO ", IO=" + .ECHO SD_IOBASE + .ECHO ", UNITS=" + .ECHO SDCNT + .ECHO "\n" ; #IF (SDMODE == SDMODE_MT) ; MT shift register for RCBUS (ref SDMODE_CSIO) ; diff --git a/Source/HBIOS/simrtc.asm b/Source/HBIOS/simrtc.asm index 521b806d..69943d35 100644 --- a/Source/HBIOS/simrtc.asm +++ b/Source/HBIOS/simrtc.asm @@ -7,6 +7,10 @@ SIMRTC_IO .EQU $FE ; SIMH IO PORT SIMRTC_CLKREAD .EQU 7 ; READ CLOCK COMMAND SIMRTC_CLKWRITE .EQU 8 ; WRITE CLOCK COMMAND SIMRTC_BUFSIZ .EQU 6 ; SIX BYTE BUFFER (YYMMDDHHMMSS) +; + .ECHO "SIMRTC: IO=" + .ECHO SIMRTC_IO + .ECHO "\n" ; ; RTC DEVICE INITIALIZATION ENTRY ; diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm index 4f7f9b86..3cf5a52b 100644 --- a/Source/HBIOS/sio.asm +++ b/Source/HBIOS/sio.asm @@ -104,12 +104,12 @@ SIO1B_CMD .EQU SIO1BASE + $07 SIO1B_DAT .EQU SIO1BASE + $05 #ENDIF ; -#IF (SIO1MODE == SIOMODE_Z80R) -SIO1A_CMD .EQU SIO0BASE + $03 -SIO1A_DAT .EQU SIO0BASE + $01 -SIO1B_CMD .EQU SIO0BASE + $02 -SIO1B_DAT .EQU SIO0BASE + $00 -#ENDIF + #IF (SIO1MODE == SIOMODE_Z80R) +SIO1A_CMD .EQU SIO1BASE + $03 +SIO1A_DAT .EQU SIO1BASE + $01 +SIO1B_CMD .EQU SIO1BASE + $02 +SIO1B_DAT .EQU SIO1BASE + $00 + #ENDIF ; #ENDIF ; @@ -1170,6 +1170,31 @@ SIO0A_CFG: .DW SIO0ACLK >> 16 ; ... DWORD VALUE .DB SIO0ACTCC ; CTC CHANNEL .DB SIO0MODE ; MODE +; + .ECHO "SIO MODE=" +#IF (SIO0MODE == SIOMODE_STD) + .ECHO "STD" +#ENDIF +#IF (SIO0MODE == SIOMODE_RC) + .ECHO "RC" +#ENDIF + +#IF (SIO0MODE == SIOMODE_SMB) + .ECHO "SMB" +#ENDIF +#IF (SIO0MODE == SIOMODE_ZP) + .ECHO "ZP" +#ENDIF +#IF (SIO0MODE == SIOMODE_Z80R) + .ECHO "Z80R" +#ENDIF + .ECHO ", IO=" + .ECHO SIO0BASE + .ECHO ", CHANNEL A" + #IF (INTMODE > 0) + .ECHO ", INTERRUPTS ENABLED" + #ENDIF + .ECHO "\n" ; SIO_CFGSIZ .EQU $ - SIO_CFG ; SIZE OF ONE CFG TABLE ENTRY ; @@ -1186,6 +1211,30 @@ SIO0B_CFG: .DW SIO0BCLK >> 16 ; ... DWORD VALUE .DB SIO0BCTCC ; CTC CHANNEL .DB SIO0MODE ; MODE +; + .ECHO "SIO MODE=" +#IF (SIO0MODE == SIOMODE_STD) + .ECHO "STD" +#ENDIF +#IF (SIO0MODE == SIOMODE_RC) + .ECHO "RC" +#ENDIF +#IF (SIO0MODE == SIOMODE_SMB) + .ECHO "SMB" +#ENDIF +#IF (SIO0MODE == SIOMODE_ZP) + .ECHO "ZP" +#ENDIF +#IF (SIO0MODE == SIOMODE_Z80R) + .ECHO "Z80R" +#ENDIF + .ECHO ", IO=" + .ECHO SIO0BASE + .ECHO ", CHANNEL B" + #IF (INTMODE > 0) + .ECHO ", INTERRUPTS ENABLED" + #ENDIF + .ECHO "\n" ; #IF (SIOCNT >= 2) ; @@ -1202,6 +1251,31 @@ SIO1A_CFG: .DW SIO1ACLK >> 16 ; ... DWORD VALUE .DB SIO1ACTCC ; CTC CHANNEL .DB SIO1MODE ; MODE +; + .ECHO "SIO MODE=" +#IF (SIO1MODE == SIOMODE_STD) + .ECHO "STD" +#ENDIF +#IF (SIO1MODE == SIOMODE_RC) + .ECHO "RC" +#ENDIF + +#IF (SIO1MODE == SIOMODE_SMB) + .ECHO "SMB" +#ENDIF +#IF (SIO1MODE == SIOMODE_ZP) + .ECHO "ZP" +#ENDIF +#IF (SIO1MODE == SIOMODE_Z80R) + .ECHO "Z80R" +#ENDIF + .ECHO ", IO=" + .ECHO SIO1BASE + .ECHO ", CHANNEL A" + #IF (INTMODE > 0) + .ECHO ", INTERRUPTS ENABLED" + #ENDIF + .ECHO "\n" ; ; SIO1 CHANNEL B SIO1B_CFG: @@ -1216,6 +1290,30 @@ SIO1B_CFG: .DW SIO1BCLK >> 16 ; ... DWORD VALUE .DB SIO1BCTCC ; CTC CHANNEL .DB SIO1MODE ; MODE +; + .ECHO "SIO MODE=" +#IF (SIO1MODE == SIOMODE_STD) + .ECHO "STD" +#ENDIF +#IF (SIO1MODE == SIOMODE_RC) + .ECHO "RC" +#ENDIF +#IF (SIO1MODE == SIOMODE_SMB) + .ECHO "SMB" +#ENDIF +#IF (SIO1MODE == SIOMODE_ZP) + .ECHO "ZP" +#ENDIF +#IF (SIO1MODE == SIOMODE_Z80R) + .ECHO "Z80R" +#ENDIF + .ECHO ", IO=" + .ECHO SIO1BASE + .ECHO ", CHANNEL B" + #IF (INTMODE > 0) + .ECHO ", INTERRUPTS ENABLED" + #ENDIF + .ECHO "\n" ; #ENDIF ; diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm index 59570c07..ec132742 100644 --- a/Source/HBIOS/sn76489.asm +++ b/Source/HBIOS/sn76489.asm @@ -15,16 +15,29 @@ ;====================================================================== ; CONSTANTS ;====================================================================== +; + + .ECHO "SN76489 MODE=" ; #IF (SNMODE == SNMODE_VGM) SN76489_PORT_LEFT .EQU $C6 ; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT) SN76489_PORT_RIGHT .EQU $C7 ; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT) + .ECHO "VGM" #ENDIF ; #IF (SNMODE == SNMODE_RC) SN76489_PORT_LEFT .EQU $FF ; PORTS FOR ACCESSING THE SN76489 CHIP (LEFT) SN76489_PORT_RIGHT .EQU $FB ; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT) + .ECHO "RC" #ENDIF +; + .ECHO ", IO_LEFT=" + .ECHO SN76489_PORT_LEFT + .ECHO ", IO_RIGHT=" + .ECHO SN76489_PORT_RIGHT + .ECHO ", CLOCK=" + .ECHO SN7CLK + .ECHO " HZ\n" ; SN7_IDAT .EQU 0 SN7_TONECNT .EQU 3 ; COUNT NUMBER OF TONE CHANNELS @@ -34,10 +47,6 @@ CHANNEL_0_SILENT .EQU $9F CHANNEL_1_SILENT .EQU $BF CHANNEL_2_SILENT .EQU $DF CHANNEL_3_SILENT .EQU $FF -; - .ECHO "SN76489 CLOCK: " - .ECHO SN7CLK - .ECHO "\n" ; #INCLUDE "audio.inc" ; diff --git a/Source/HBIOS/spk.asm b/Source/HBIOS/spk.asm index 67c9f7f5..780ca4b8 100644 --- a/Source/HBIOS/spk.asm +++ b/Source/HBIOS/spk.asm @@ -40,6 +40,10 @@ SP_RTCIOMSK .EQU 00000100B SP_PENDING_PERIOD .DW SP_NOTE_C8 ; PENDING PERIOD (16 BITS) SP_PENDING_VOLUME .DB $FF ; PENDING VOL (8 BITS) SP_PENDING_DURATION .DW 0 ; PENDING DURATION (16 BITS) +; + .ECHO "SPK: IO=" + .ECHO RTCIO + .ECHO "\n" ; ;====================================================================== ; DRIVER INITIALIZATION diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 6e5b7800..bf7a372a 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -510,7 +510,7 @@ CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ ; .ECHO "ASSUMED CPU SPEED: " .ECHO CPUKHZ - .ECHO " KHZ\r\n" + .ECHO " KHZ\n" ; .ECHO "INTERRUPTS: " #IF (INTMODE == 0) @@ -525,7 +525,7 @@ CPUMHZ .EQU CPUKHZ / 1000 ; CPU FREQ IN MHZ #IF (INTMODE == 3) .ECHO "MODE 3" #ENDIF - .ECHO "\r\n" + .ECHO "\n" ; ; SYSTEM PERIODIC TIMER MODE ; @@ -598,7 +598,7 @@ SYSTIM .SET TM_Z280 #IF ((DEFSERCFG & %1111100000000) == SER_BAUD115200 .ECHO "115200" #ENDIF - .ECHO " BAUD\r\n" + .ECHO " BAUD\n" #ENDIF ; ; @@ -629,16 +629,16 @@ SYSTIM .SET TM_Z280 #IF (MEMMGR == MM_RPH) .ECHO "RHYOPHYRE ONBOARD (RPH)" #ENDIF - .ECHO "\r\n" + .ECHO "\n" #ENDIF ; .ECHO "ROM SIZE: " .ECHO ROMSIZE - .ECHO " KB\r\n" + .ECHO " KB\n" ; .ECHO "RAM SIZE: " .ECHO RAMSIZE - .ECHO " KB\r\n" + .ECHO " KB\n" ; ; MEMORY BANK CONFIGURATION ; diff --git a/Source/HBIOS/syq.asm b/Source/HBIOS/syq.asm index 29126f9e..824d3bed 100644 --- a/Source/HBIOS/syq.asm +++ b/Source/HBIOS/syq.asm @@ -1446,6 +1446,17 @@ SYQ0_CFG: ; DEVICE 0 .DB SYQ0BASE ; IO BASE ADDRESS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + .ECHO "SYQ: MODE=" + #IF (SYQMODE == SYQMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (SYQMODE == SYQMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO SYQ0BASE + .ECHO "\n" #ENDIF ; #IF (SYQCNT >= 2) @@ -1457,6 +1468,17 @@ SYQ1_CFG: ; DEVICE 1 .DB SYQ1BASE ; IO BASE ADDRESS .DW 0,0 ; DEVICE CAPACITY .DW 0,0 ; CURRENT LBA +; + .ECHO "SYQ: MODE=" + #IF (SYQMODE == SYQMODE_SPP) + .ECHO "SPP" + #ENDIF + #IF (SYQMODE == SYQMODE_MG014) + .ECHO "MG014" + #ENDIF + .ECHO ", IO=" + .ECHO SYQ1BASE + .ECHO "\n" #ENDIF ; #IF ($ - SYQ_CFG) != (SYQCNT * SYQ_CFGSIZ) diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm index 89b8521e..e2a6fd65 100644 --- a/Source/HBIOS/tms.asm +++ b/Source/HBIOS/tms.asm @@ -42,9 +42,7 @@ TMSCTRL1: .EQU 1 ; CONTROL BITS TMSINTEN: .EQU 5 ; INTERRUPT ENABLE BIT ; -#IF TMSTIMENABLE - .ECHO "TMS INTERRUPTS ENABLED\n" -#ENDIF + .ECHO "TMS: MODE=" ; #IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958)) TMS_DATREG .EQU $98 ; READ/WRITE DATA @@ -53,6 +51,13 @@ TMS_PPIA .EQU 0 ; PPI PORT A TMS_PPIB .EQU 0 ; PPI PORT B TMS_PPIC .EQU 0 ; PPI PORT C TMS_PPIX .EQU 0 ; PPI CONTROL PORT +; + #IF (TMSMODE == TMSMODE_MSX) + .ECHO "MSX" + #ENDIF + #IF (TMSMODE == TMSMODE_MSX9958) + .ECHO "MSX9958" + #ENDIF #ENDIF ; #IF (TMSMODE == TMSMODE_COLECO) @@ -62,6 +67,7 @@ TMS_PPIA .EQU 0 ; PPI PORT A TMS_PPIB .EQU 0 ; PPI PORT B TMS_PPIC .EQU 0 ; PPI PORT C TMS_PPIX .EQU 0 ; PPI CONTROL PORT + .ECHO "COLECO" #ENDIF ; #IF (TMSMODE == TMSMODE_MSXKBD) @@ -69,6 +75,7 @@ TMS_DATREG .EQU $98 ; READ/WRITE DATA TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL TMS_KBDDATA .EQU $E0 ; KBD CTLR DATA PORT TMS_KBDST .EQU $E1 ; KBD CTLR STATUS/CMD PORT + .ECHO "MSXKBD" #ENDIF ; #IF (TMSMODE == TMSMODE_N8) @@ -78,6 +85,7 @@ TMS_PPIA .EQU $84 ; PPI PORT A TMS_PPIB .EQU $85 ; PPI PORT B TMS_PPIC .EQU $86 ; PPI PORT C TMS_PPIX .EQU $87 ; PPI CONTROL PORT + .ECHO "N8" #ENDIF ; #IF (TMSMODE == TMSMODE_SCG) @@ -88,6 +96,7 @@ TMS_PPIA .EQU 0 ; PPI PORT A TMS_PPIB .EQU 0 ; PPI PORT B TMS_PPIC .EQU 0 ; PPI PORT C TMS_PPIX .EQU 0 ; PPI CONTROL PORT + .ECHO "SCG" #ENDIF ; #IF (TMSMODE == TMSMODE_MBC) @@ -100,7 +109,15 @@ TMS_PPIC .EQU 0 ; PPI PORT C TMS_PPIX .EQU 0 ; PPI CONTROL PORT TMS_KBDDATA .EQU $E2 ; KBD CTLR DATA PORT TMS_KBDST .EQU $E3 ; KBD CTLR STATUS/CMD PORT + .ECHO "MBC" +#ENDIF +; + .ECHO ", IO=" + .ECHO TMS_DATREG +#IF TMSTIMENABLE + .ECHO ", INTERRUPTS ENABLED" #ENDIF + .ECHO "\n" ; TMS_ROWS .EQU 24 ; diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm index 19f623e1..4b5404c9 100644 --- a/Source/HBIOS/uart.asm +++ b/Source/HBIOS/uart.asm @@ -1041,6 +1041,13 @@ UART_CFG_SBC: .DB UARTSBASE + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW UARTSBC_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "UART: MODE=SBC, IO=" + .ECHO UARTSBASE + #IF ((UARTINTS) & (INTMODE > 0)) + .ECHO ", INTERRUPTS ENABLED" + #ENDIF + .ECHO "\n" #ENDIF #IF (UARTAUX) UART_CFG_AUX: @@ -1051,6 +1058,10 @@ UART_CFG_AUX: .DB UARTABASE + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; NO INT HANDLER +; + .ECHO "UART: MODE=AUX, IO=" + .ECHO UARTABASE + .ECHO "\n" #ENDIF #IF (UARTCAS) UART_CFG_CAS: @@ -1061,6 +1072,13 @@ UART_CFG_CAS: .DB UARTCBASE + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCASSPD ; LINE CONFIGURATION .DW UARTCAS_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + .ECHO "UART: MODE=CAS, IO=" + .ECHO UARTCBASE + #IF ((UARTINTS) & (INTMODE > 0)) + .ECHO ", INTERRUPTS ENABLED" + #ENDIF + .ECHO "\n" #ENDIF #IF (UARTMFP) UART_CFG_MFP: @@ -1071,6 +1089,10 @@ UART_CFG_MFP: .DB UARTMBASE + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=MFP, IO=" + .ECHO UARTSBASE + .ECHO "\n" #ENDIF #IF (UART4) ; 4UART SERIAL PORT A @@ -1080,6 +1102,11 @@ UART_CFG_MFP: .DB UART4BASE+0 + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=4UART, IO=" + .ECHO UART4BASE+0 + .ECHO "\n" +; ; 4UART SERIAL PORT B .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -1087,6 +1114,11 @@ UART_CFG_MFP: .DB UART4BASE+8 + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=4UART, IO=" + .ECHO UART4BASE+8 + .ECHO "\n" +; ; 4UART SERIAL PORT C .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -1094,6 +1126,11 @@ UART_CFG_MFP: .DB UART4BASE+16 + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=4UART, IO=" + .ECHO UART4BASE+16 + .ECHO "\n" +; ; 4UART SERIAL PORT D .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -1101,6 +1138,10 @@ UART_CFG_MFP: .DB UART4BASE+24 + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=4UART, IO=" + .ECHO UART4BASE+24 + .ECHO "\n" #ENDIF #IF (UARTRC) ; UARTRC SERIAL PORT A @@ -1110,6 +1151,11 @@ UART_CFG_MFP: .DB UARTRBASE + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=RC, IO=" + .ECHO UARTRBASE+0 + .ECHO "\n" +; ; UARTRC SERIAL PORT B .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -1117,6 +1163,11 @@ UART_CFG_MFP: .DB UARTRBASE+8 + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=RC, IO=" + .ECHO UARTRBASE+8 + .ECHO "\n" +; #ENDIF #IF (UARTDUAL) ; DUAL UART CHANNEL A @@ -1126,6 +1177,11 @@ UART_CFG_MFP: .DB UARTDBASE + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=DUAL, IO=" + .ECHO UARTDBASE+0 + .ECHO "\n" +; ; DUAL UART CHANNEL B .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) .DB 0 ; UART TYPE @@ -1133,6 +1189,11 @@ UART_CFG_MFP: .DB UARTDBASE+8 + UART_LSR ; LINE STATUS PORT (LSR) .DW UARTCFG ; LINE CONFIGURATION .DW 0 ; SHOULD NEVER NEED INT HANDLER +; + .ECHO "UART: MODE=DUAL, IO=" + .ECHO UARTDBASE+8 + .ECHO "\n" +; #ENDIF ; UART_CNT .EQU ($ - UART_CFG) / 8 diff --git a/Source/HBIOS/uf.asm b/Source/HBIOS/uf.asm index 049167c0..328ac033 100644 --- a/Source/HBIOS/uf.asm +++ b/Source/HBIOS/uf.asm @@ -23,6 +23,10 @@ UF_USB_ACTIVE .DB 0 ; USB CABLE CONNECTED STATUS FLAG ; DEVICE DESCRIPTION TABLE ; UF_CFG: .DW SER_9600_8N1 ; DUMMY CONFIGURATION +; + .ECHO "USB-FIFO: IO=" + .ECHO UFBASE + .ECHO "\n" ; ; SETUP THE DISPATCH TABLE ENTRY AND INITIALIZE HARDWARE ; diff --git a/Source/HBIOS/vdu.asm b/Source/HBIOS/vdu.asm index 0d035bf4..890e2a06 100644 --- a/Source/HBIOS/vdu.asm +++ b/Source/HBIOS/vdu.asm @@ -81,6 +81,12 @@ VDU_R11 .EQU DSCANL-1 VDU_R10 .EQU (VDU_BLNK + DSCANL-1) VDU_R11 .EQU DSCANL-1 #ENDIF +; + .ECHO "VDU: IO=" + .ECHO VDU_RAMRD + .ECHO ", PPK IO=" + .ECHO VDU_PPIA + .ECHO "\n" ; ;====================================================================== ; VDU DRIVER - INITIALIZATION diff --git a/Source/HBIOS/vga.asm b/Source/HBIOS/vga.asm index 039a1445..8ed9c280 100644 --- a/Source/HBIOS/vga.asm +++ b/Source/HBIOS/vga.asm @@ -20,6 +20,14 @@ VGA_CFG .EQU VGA_BASE + $04 ; VGA3 BOARD CFG REGISTER VGA_HI .EQU VGA_BASE + $05 ; BOARD RAM HI ADDRESS VGA_LO .EQU VGA_BASE + $06 ; BOARD RAM LO ADDRESS VGA_DAT .EQU VGA_BASE + $07 ; BOARD RAM BYTE R/W +; + .ECHO "VGA: " + .ECHO "IO=" + .ECHO VGA_BASE + .ECHO ", KBD MODE=PS/2" + .ECHO ", KBD IO=" + .ECHO VGA_KBDDATA + .ECHO "\n" ; VGA_NOBL .EQU 00000000B ; NO BLINK VGA_NOCU .EQU 00100000B ; NO CURSOR diff --git a/Source/HBIOS/vrc.asm b/Source/HBIOS/vrc.asm index d9751cdb..3f25392e 100644 --- a/Source/HBIOS/vrc.asm +++ b/Source/HBIOS/vrc.asm @@ -25,6 +25,13 @@ VRC_COLS .EQU 64 #DEFINE VRC_FONT FONTVGARC ; TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER +; + .ECHO "VRC: IO=" + .ECHO VRC_BASE + .ECHO ", KBD MODE=VRC" + .ECHO ", KBD IO=" + .ECHO VRC_KBDDATA + .ECHO "\n" ; ;====================================================================== ; VRC DRIVER - INITIALIZATION diff --git a/Source/HBIOS/ym2612.asm b/Source/HBIOS/ym2612.asm index afa4bd48..936dabae 100644 --- a/Source/HBIOS/ym2612.asm +++ b/Source/HBIOS/ym2612.asm @@ -38,6 +38,10 @@ YM_RDY_RST .DB 0 ; FLAG INDICATES IF DEVICE IS IN READY (NZ) OR RESET STATE (Z) YM_DEBUG .EQU 0 ; CHANGE TO 1 TO ENABLE DEBUGGING YM_RSTCFG .EQU 0 ; SET TO 1 FOR FULL REGISTER CLEAR YM_FAST3438 .EQU 0 ; FAST CPU'S WITH A YM3438 MAY REQUIRE A DELAY +; + .ECHO "YM: IO=" + .ECHO YMSEL + .ECHO "\n" ; ;------------------------------------------------------------------------------ ; Driver function table and instance data diff --git a/Source/HBIOS/z2u.asm b/Source/HBIOS/z2u.asm index d4ac9ac3..9e54ebb0 100644 --- a/Source/HBIOS/z2u.asm +++ b/Source/HBIOS/z2u.asm @@ -715,6 +715,15 @@ Z2U0_CFG: .DW Z2U0CFG ; LINE CONFIGURATION .DW Z2U0_RCVBUF ; POINTER TO RCV BUFFER STRUCT ; +; + .ECHO "Z2U: IO=" + .ECHO Z2U0BASE +#IF (INTMODE == 3) + .ECHO ", INTERRUPTS ENABLED" +#ENDIF + .ECHO "\n" + +; Z2U_CFGSIZ .EQU $ - Z2U_CFG ; SIZE OF ONE CFG TABLE ENTRY ; Z2U_CFGCNT .EQU ($ - Z2U_CFG) / Z2U_CFGSIZ diff --git a/Source/ver.inc b/Source/ver.inc index cc253650..cf066c01 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 4 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.4.0-dev.25" +#DEFINE BIOSVER "3.4.0-dev.26" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index f3857cdc..fadf6dde 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 4 rup equ 0 rtp equ 0 biosver macro - db "3.4.0-dev.25" + db "3.4.0-dev.26" endm