Merge pull request #4 from wwarthen/master

upstream master

Doc/ChangeLog.txt

@@ -28,7 +28,7 @@ Version 2.9.2
 - WBW: Updated FAT to add MD and FORMAT commands
 - WBW: Add CP/M 3 (experimental)
 - M?T: Support Shift register SPI WIZNET for RC2014
-- P?S: Added seconds register in HBIOS
+- PLS: Added seconds register in HBIOS
 
 Version 2.9.1
 -------------

ReadMe.txt

@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.2-pre.20, 2019-11-11
+Version 2.9.2-pre.21, 2019-11-15
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 

Source/CBIOS/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.20"
+#DEFINE BIOSVER	"2.9.2-pre.21"

Source/HBIOS/hbios.asm

@@ -981,22 +981,69 @@ HB_CPU1:
 	LD	A,L
 	LD	(HB_CPUTYPE),A
 ;
+#IF (DSRTCENABLE)
+	CALL	DSRTC_PREINIT
+#ENDIF
+;
+#IF (CPUFAM == CPU_Z180)
+;
+	; AT BOOT, Z180 PHI IS OSC / 2
+	LD	C,(CPUOSC / 2) / 1000000
+	LD	DE,(CPUOSC / 2) / 1000
+;
+#IF (Z180_CLKDIV >= 1)
+	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
+	CP	2		; Z8S180 REV K OR BETTER?
+	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
+	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
+	LD	A,$80
+	OUT0	(Z180_CCR),A
+	; REFLECT SPEED CHANGE
+	LD	C,CPUOSC / 1000000
+	LD	DE,CPUOSC / 1000
+#ENDIF
+
+#IF (Z180_CLKDIV >= 2)
+	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
+	CP	3		; Z8S180 REV N OR BETTER?
+	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
+	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
+	LD	A,$80
+	OUT0	(Z180_CMR),A
+	; REFLECT SPEED CHANGE
+	LD	C,(CPUOSC * 2) / 1000000
+	LD	DE,(CPUOSC * 2) / 1000
+#ENDIF
+;
+HB_CPU2:
+	; SAVE CPU SPEED IN CONFIG BLOCK
+	LD	A,C
+	LD	(CB_CPUMHZ),A
+	LD	(CB_CPUKHZ),DE
+;
+#ENDIF
+;
+	DIAG(%00011111)
+;
+; PERFORM DYNAMIC CPU SPEED DERIVATION
+;
+	CALL	HB_CPUSPD		; CPU SPEED DETECTION
+;
+	CALL	DELAY_INIT		; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS
+;
+#IF (CPUFAM == CPU_Z180)
+;
+	; SET FINAL DESIRED WAIT STATES
+	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
+	OUT0	(Z180_DCNTL),A
+;
+#ENDIF
+;
 #IF (KIOENABLE)
 	LD	A,%11111001	; RESET ALL DEVICES, SET DAISYCHAIN
 	OUT	(KIOBASE+$0E),A	; DO IT
-	;CALL	DLY64		; WAIT A BIT FOR RESET TO COMPLETE
 #ENDIF  
 ;
-; SETUP INTERRUPT VECTORS, AS APPROPRIATE
-;
-;#IF (INTMODE == 1)
-;	; OVERLAY $0038 WITH JP INT_IM1
-;	LD	A,$C3			; JP INSTRUCTION
-;	LD	($0038),A		; INSTALL IT
-;	LD	HL,INT_IM1		; DESTINATION ADDRESS
-;	LD	($0039),HL		; INSTALL IT
-;#ENDIF
-;
 #IF (INTMODE == 2)
 	; SETUP Z80 IVT AND INT MODE 2
 	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
@@ -1010,7 +1057,7 @@ HB_CPU1:
 
 	IM	2			; SWITCH TO INT MODE 2
 #ENDIF
-
+;
 #IF (PLATFORM == PLT_SBC)
 ;
   #IF (HTIMENABLE)			; SIMH TIMER
@@ -1142,7 +1189,6 @@ HB_CPU1:
 ;
 #ENDIF
 ;
-;
 #IF (PLATFORM == PLT_RCZ80)
 ;
 ; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO
@@ -1245,11 +1291,10 @@ HB_CPU1:
 	LD	(IVT(INT_TIM0)),HL	; Z180 TIMER 0
 
 	; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0
-;	LD	HL,CPUOSC/TICKSPERSEC/20-1	; 50HZ = 18432000 / 50 / 20
-	LD	HL,(CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
-	DEC	HL			; RELOAD OCCURS *AFTER* ZERO
+	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
 	OUT0	(Z180_TMDR0L),L		; INITIALIZE TIMER 0 DATA REGISTER
 	OUT0	(Z180_TMDR0H),H
+	DEC	HL			; RELOAD OCCURS *AFTER* ZERO
 	OUT0	(Z180_RLDR0L),L		; INITIALIZE TIMER 0 RELOAD REGISTER
 	OUT0	(Z180_RLDR0H),H
 	LD	A,%00010001		; ENABLE TIMER0 INT AND DOWN COUNTING
@@ -1259,67 +1304,6 @@ HB_CPU1:
 ;
 #ENDIF
 ;
-#IF (DSRTCENABLE)
-	CALL	DSRTC_PREINIT
-#ENDIF
-;
-#IF (CPUFAM == CPU_Z180)
-;
-	; AT BOOT, Z180 PHI IS OSC / 2
-	LD	C,(CPUOSC / 2) / 1000000
-	LD	DE,(CPUOSC / 2) / 1000
-;
-#IF (Z180_CLKDIV == 1)
-	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
-	CP	2		; Z8S180 REV K OR BETTER?
-	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
-	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
-	LD	A,$80
-	OUT0	(Z180_CCR),A
-	; REFLECT SPEED CHANGE
-	LD	C,CPUOSC / 1000000
-	LD	DE,CPUOSC / 1000
-#ELSE
-;
-#IF (Z180_CLKDIV == 2)
-	LD	A,(HB_CPUTYPE)	; GET CPU TYPE
-	CP	3		; Z8S180 REV N OR BETTER?
-	JR	C,HB_CPU2	; IF NOT, NOT POSSIBLE!
-	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
-	LD	A,$80
-	OUT0	(Z180_CMR),A	; MUST SET CMR BEFORE CCR
-	OUT0	(Z180_CCR),A
-	; REFLECT SPEED CHANGE
-	LD	C,(CPUOSC * 2) / 1000000
-	LD	DE,(CPUOSC * 2) / 1000
-#ENDIF
-;
-#ENDIF
-;
-HB_CPU2:
-	; SAVE CPU SPEED IN CONFIG BLOCK
-	LD	A,C
-	LD	(CB_CPUMHZ),A
-	LD	(CB_CPUKHZ),DE
-;
-#ENDIF
-;
-; PERFORM DYNAMIC CPU SPEED DERIVATION
-;
-	CALL	HB_CPUSPD		; CPU SPEED DETECTION
-;
-#IF (CPUFAM == CPU_Z180)
-;
-	; SET DESIRED WAIT STATES
-	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
-	OUT0	(Z180_DCNTL),A
-;
-#ENDIF
-;
-	CALL	DELAY_INIT		; INITIALIZE SPEED COMPENSATED DELAY FUNCTIONS
-;
-	DIAG(%00011111)
-;
 ; INITIALIZE HEAP STORAGE
 ;
 	; INITIALIZE POINTERS

Source/HBIOS/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.20"
+#DEFINE BIOSVER	"2.9.2-pre.21"