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SZ80 Tweaks

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Support full 1MB of RAM on S100 Z80 CPU.
This commit is contained in:
Wayne Warthen
2025-09-23 11:59:47 -07:00
parent 1f6672ebab
commit 74cfca470d
5 changed files with 61 additions and 19 deletions
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4
Source/HBIOS/Config/SZ80_std.asm
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@@ -48,7 +48,7 @@
#INCLUDE "cfg_SZ80.asm"
;
CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
RAMSIZE .SET 1024 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
MEMMGR .SET MM_SZ80 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80]
@@ -60,5 +60,3 @@ PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
ESPSDENABLE .SET TRUE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
ESPSDCNT .SET 1 ; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD
ESPSD0DUAL .SET TRUE ; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD)
#DEFINE SIZERAM

58
Source/SZ80/Bank Layout.txt
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@@ -1,9 +1,17 @@
S100 Z80 has no real ROM. It has 1024K RAM.
S100 Z80 CPU
============
S100 Z80 has only a small monitor ROM at the to of CPU address space
which is not utilized by RomWBW. RomWBW treats the system as a
ROMless system. RAM is provided by a separate board. RomWBW assumes
the RAM board has >= 1024K which is the maximum RAM supported by the
Z80 CPU memory manager.
The ROMless startup mode treats the entire 1024KB as RAM. 128KB of RAM
must be preloaded by the Monitor CF Loader. There will be no ROM
disk available under RomWBW. There will be a RAM Disk and it's initial
contents will be seeded by the image loaded by the CF Loader.
disk available under RomWBW.
The RomWBW 32K bank layout is as follows:
Bank Contents Description
-------- -------- -----------
@@ -11,19 +19,50 @@ Bank Contents Description
0x1 IMG0 ROM Loader, Monitor, ROM OSes
0x2 IMG1 ROM Applications
0x3 IMG2 Reserved
0x4-0x1B RAMD RAM Disk Banks
0x4-0xF RAMD RAM Disk Banks
0x10-1B APP Application Banks
0x1C BUF OS Buffers (CP/M3)
0x1D AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0x1E USR User Bank (CP/M TPA, etc.)
0x1F COM Common Bank, Upper 32KB
Memory Manager
--------------
FPGA Z80 has no real ROM. It has a single 512K RAM chip.
The Z80 CPU implements a custom memory manager that allows mapping the 2
lowest 16K portions of CPU address space ($0000-$3FFFF, and $4000-$7FFF).
Each of these banks can be mapped to any physical 16K bank.
The physical 16K banks are 16K aligned. The memory manager
can address a maximum of 1MB of physical memory. Which is
64 x 16K banks (bank numbers $00-$3F)
The top 32K of CPU address space ($8000-$FFFF) is statically mapped
to physical banks $02 & $03. RomWBW is designed to have the top
32K of CPU address space assigned to the last two banks of
RAM. So the RomWBW memory manager for this board (MM_SZ80)
rotates the requested bank numbers by 4. With wrapping, this
causes a RomWBW request for the top two banks to be mapped to
physical banks $02 & $03.
Z80 CPU Physical: 00 01 02 03 ... 38 39 3A 3B 3C 3D 3E 3F
RomWBW Logical: 04 05 06 07 ... 3C 3D 3E 3F 00 01 02 03
As a result, the Z80 CPU Monitor loads RomWBW starting at
physical bank 04.
S100 FPGA Z80 SBC
=================
FPGA Z80 has no real ROM. It has a single onboard 512K RAM chip.
RomWBW assumes the use of the T35 FPGA with associated firmware.
The ROMless startup mode treats the entire 512KB as RAM. 384KB of RAM
must be preloaded by the FPGA Monitor CF Loader. There will be no ROM
disk available under RomWBW. There will be a RAM Disk and it's initial
contents will be seeded by the image loaded by the CF Loader.
disk available under RomWBW.
The RomWBW 32K bank layout is as follows:
Bank Contents Description
-------- -------- -----------
@@ -36,3 +75,8 @@ Bank Contents Description
0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0xE USR User Bank (CP/M TPA, etc.)
0xF COM Common Bank, Upper 32KB
Memory Manager
--------------
The T35 FPGA Z80 implements the Zeta 2 (Z2) memory manager.

2
Source/SZ80/Build.cmd
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@@ -16,7 +16,7 @@ echo.
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 sz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\%1.rom -binary -offset 0x80000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xA0000 ..\..\Binary\%1.upd -binary -offset 0x80000 -o temp.dat -binary
move temp.dat ..\..\Binary\%1_hd1k_prefix.dat
copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b

8
Source/SZ80/Makefile
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@@ -3,8 +3,8 @@ DEST=../../Binary
HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \
$(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img
ROMS := $(wildcard $(DEST)/SZ80_*.rom)
ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS))
ROMS := $(wildcard $(DEST)/SZ80_*.upd)
ROMS := $(patsubst $(DEST)/%.upd,%,$(ROMS))
OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS))
OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS))
@@ -15,10 +15,10 @@ include $(TOOLS)/Makefile.inc
DIFFPATH = $(DIFFTO)/Binary
%_hd1k_prefix.dat: $(DEST)/%.rom
%_hd1k_prefix.dat: $(DEST)/%.upd
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 sz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $< -binary -offset 0x80000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xA0000 $< -binary -offset 0x80000 -o temp.dat -binary
mv temp.dat $@
%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS)

8
Source/SZ80/SZ80 Disk Layout.txt
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@@ -1,4 +1,4 @@
FZ80 Disk Prefix Layout
SZ80 Disk Prefix Layout
=======================
---- Bytes ---- --- Sectors ---
@@ -13,7 +13,7 @@ Start Length Start Length Description
Notes
-----
- Z80 Monitor reads 384KB (RomWBW) from sectors 1024-1791 of CF into first 384KB of physical RAM
- Z80 Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
- Z80 Monitor reads 128KB (RomWBW) from sectors 1024-1279 of CF into first 128KB of RAM
- Z80 Monitor maps first 16KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
-- WBW 3:18 PM 6/30/2024
-- WBW 10:07 AM 9/23/2025