@ -66,7 +66,6 @@
;
; TODO
; - Add remaining service routine stubs for IM3 (NMI, etc.)
; - Review bank selection code (selectable user/sys bank?)
; - Fix app boot under Z280
;
; INCLUDE GENERIC STUFF
@ -637,20 +636,6 @@ HBX_PPRET:
HBX_PPSP .EQU $ - 2
RET
;
; SYSCALL VECTOR ENTRY POINT. TAKES STACK PARAMETER AS A BRANCH
; ADDRESS AND CALLS IT. ALLOWS ANY USER MODE CODE TO CALL INTO AN
; ARBITRARY LOCATION OF SYSTEM MODE CODE.
;
# IF ( MEMMGR = = MM_Z280 )
Z280_SYSCALL:
EX ( SP ), HL
LD ( Z280_SYSCALL_GO + 1 ), HL
POP HL
Z280_SYSCALL_GO:
CALL $ FFFF ; PARM SET ABOVE
.DB $ ED , $ 55 ; RETIL
# ENDIF
;
; PRIVATE STACK AT END OF HBIOS CODE
; OCCUPIES SPACE BEFORE IVT
;
@ -977,7 +962,7 @@ HB_START:
; INITIALIZE ALL OF THE SYSTEM PAGE DESCRIPTORS WITH BLOCK MOVE
XOR A ; FIRST USER PDR
OUT ( Z280_MMUPDRPTR ), A ; SET THE PDR POINTER
LD HL , Z280_PDRTBL ; START OF PDR VALUES TABLE
LD HL , Z280_BOOT PDRTBL ; START OF PDR VALUES TABLE
LD C , Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B , 16 ; PROGRAM 16 PDRS
.DB $ ED , $ 93 ; OTIRW
@ -985,7 +970,7 @@ HB_START:
; INITIALIZE ALL OF THE USER PAGE DESCRIPTORS WITH BLOCK MOVE
LD A , $ 10 ; FIRST SYSTEM PDR
OUT ( Z280_MMUPDRPTR ), A ; SET THE PDR POINTER
LD HL , Z280_PDRTBL ; START OF PDR VALUES TABLE
LD HL , Z280_BOOT PDRTBL ; START OF PDR VALUES TABLE
LD C , Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B , 16 ; PROGRAM 16 PDRS
.DB $ ED , $ 93 ; OTIRW
@ -1007,7 +992,12 @@ HB_START:
;
JP Z280_INITZ ; JUMP TO CODE CONTINUATION
;
Z280_PDRTBL:
# IF (( $ % 2 ) = = 1 )
; BYTE ALIGN THE TABLE
.DB 0
# ENDIF
;
Z280_BOOTPDRTBL:
; LOWER 32 K (BANKED)
.DW ( $ 000 << 4 ) | $ A
.DW ( $ 001 << 4 ) | $ A
@ -1186,10 +1176,15 @@ Z280_INITZ:
;
; TRANSITION TO HBIOS IN RAM BANK
;
# IF ( MEMMGR = = MM_Z280 )
LD A , BID_BIOS
CALL Z280_BNKSEL
# ELSE
LD A , BID_BIOS ; BIOS BANK ID
LD IX , HB_START1 ; EXECUTION RESUMES HERE
CALL HBX_BNKCALL ; CONTINUE IN RAM BANK, DO NOT RETURN
HALT ; WE SHOULD NOT COME BACK HERE!
# ENDIF
;
HB_RAMFLAG .DB FALSE ; INITIALLY FALSE, SET TO TRUE BELOW AFTER RAM TRANSITION
;
@ -1906,10 +1901,14 @@ INITSYS4:
HB_DI ; NOT SURE THIS IS NEEDED
;; FIXUP BNKSEL TO WORK ON USER MODE PDRS
;XOR A
;LD (W_MMU0+1),A
;LD (W_MMU1+1),A
; FIXUP BNKSEL TO WORK ON USER MODE PDRS
XOR A
LD ( W_MMU0 + 1 ), A
LD ( W_MMU1 + 1 ), A
LD ( Z280_BNKSEL2 + 1 ), A
;CALL NEWLINE
;LD DE,$1050
@ -3824,6 +3823,350 @@ Z280_IVT:
;
# IF ( MEMMGR = = MM_Z280 )
;
; REG A HAS BANK ID
;
Z280_BNKSEL:
PUSH BC
PUSH HL
;
; SELECT I/O PAGE FOR MMU
LD L , $ FF ; MMU AT I/O PAGE $FF
LD C , Z280_IOPR ; I/O PAGE REGISTER TO C
.DB $ ED , $ 6 E ; LDCTL (C),HL
;
; POINT HL TO PORTION OF TABLE TO PROGRAM PDRS WITH
LD HL , Z280_PDRTBL ; POINT TO PDR TABLE
SLA A ; BANK ID TIMES TWO, RAM BIT TO C
JR NC , Z280_BNKSEL1 ; IF ROM, SKIP AHEAD
INC H ; HANDLE RAM OFFSET
Z280_BNKSEL1:
RLCA
RLCA
RLCA
ADD A , L
LD L , A
JR NC , Z280_BNKSEL2 ; NO CARRY, SKIP AHEAD
INC H ; HANDLE CARRY
;
Z280_BNKSEL2:
; POINT TO FIRST PDR TO PROGRAM ($00=USER, $10=SYSTEM)
LD A , $ 10 ; FIRST SYSTEM PDR
OUT ( Z280_MMUPDRPTR ), A ; SET THE PDR POINTER
;
; PROGRAM 8 PDRS
LD C , Z280_MMUBLKMOV ; PDR BLOCK MOVE PORT
LD B , 8 ; PROGRAM 8 PDRS
.DB $ ED , $ 93 ; OTIRW
;
; SELECT I/O PAGE FOR MMU
LD L , $ 00 ; NORMAL I/O PAGE $00
LD C , Z280_IOPR ; I/O PAGE REGISTER TO C
.DB $ ED , $ 6 E ; LDCTL (C),HL
;
POP HL
POP BC
RET
;
# IF (( $ % 2 ) = = 1 )
; BYTE ALIGN THE TABLE
.DB 0
# ENDIF
;
Z280_PDRTBL:
; BANK $00
.DW ( $ 000 << 4 ) | $ A
.DW ( $ 001 << 4 ) | $ A
.DW ( $ 002 << 4 ) | $ A
.DW ( $ 003 << 4 ) | $ A
.DW ( $ 004 << 4 ) | $ A
.DW ( $ 005 << 4 ) | $ A
.DW ( $ 006 << 4 ) | $ A
.DW ( $ 007 << 4 ) | $ A
; BANK $01
.DW ( $ 008 << 4 ) | $ A
.DW ( $ 009 << 4 ) | $ A
.DW ( $ 00 A << 4 ) | $ A
.DW ( $ 00B << 4 ) | $ A
.DW ( $ 00 C << 4 ) | $ A
.DW ( $ 00 D << 4 ) | $ A
.DW ( $ 00 E << 4 ) | $ A
.DW ( $ 00 F << 4 ) | $ A
; BANK $02
.DW ( $ 010 << 4 ) | $ A
.DW ( $ 011 << 4 ) | $ A
.DW ( $ 012 << 4 ) | $ A
.DW ( $ 013 << 4 ) | $ A
.DW ( $ 014 << 4 ) | $ A
.DW ( $ 015 << 4 ) | $ A
.DW ( $ 016 << 4 ) | $ A
.DW ( $ 017 << 4 ) | $ A
; BANK $03
.DW ( $ 018 << 4 ) | $ A
.DW ( $ 019 << 4 ) | $ A
.DW ( $ 01 A << 4 ) | $ A
.DW ( $ 01B << 4 ) | $ A
.DW ( $ 01 C << 4 ) | $ A
.DW ( $ 01 D << 4 ) | $ A
.DW ( $ 01 E << 4 ) | $ A
.DW ( $ 01 F << 4 ) | $ A
; BANK $04
.DW ( $ 020 << 4 ) | $ A
.DW ( $ 021 << 4 ) | $ A
.DW ( $ 022 << 4 ) | $ A
.DW ( $ 023 << 4 ) | $ A
.DW ( $ 024 << 4 ) | $ A
.DW ( $ 025 << 4 ) | $ A
.DW ( $ 026 << 4 ) | $ A
.DW ( $ 027 << 4 ) | $ A
; BANK $05
.DW ( $ 028 << 4 ) | $ A
.DW ( $ 029 << 4 ) | $ A
.DW ( $ 02 A << 4 ) | $ A
.DW ( $ 02 B << 4 ) | $ A
.DW ( $ 02 C << 4 ) | $ A
.DW ( $ 02 D << 4 ) | $ A
.DW ( $ 02 E << 4 ) | $ A
.DW ( $ 02 F << 4 ) | $ A
; BANK $06
.DW ( $ 030 << 4 ) | $ A
.DW ( $ 031 << 4 ) | $ A
.DW ( $ 032 << 4 ) | $ A
.DW ( $ 033 << 4 ) | $ A
.DW ( $ 034 << 4 ) | $ A
.DW ( $ 035 << 4 ) | $ A
.DW ( $ 036 << 4 ) | $ A
.DW ( $ 037 << 4 ) | $ A
; BANK $07
.DW ( $ 038 << 4 ) | $ A
.DW ( $ 039 << 4 ) | $ A
.DW ( $ 03 A << 4 ) | $ A
.DW ( $ 03 B << 4 ) | $ A
.DW ( $ 03 C << 4 ) | $ A
.DW ( $ 03 D << 4 ) | $ A
.DW ( $ 03 E << 4 ) | $ A
.DW ( $ 03 F << 4 ) | $ A
; BANK $08
.DW ( $ 040 << 4 ) | $ A
.DW ( $ 041 << 4 ) | $ A
.DW ( $ 042 << 4 ) | $ A
.DW ( $ 043 << 4 ) | $ A
.DW ( $ 044 << 4 ) | $ A
.DW ( $ 045 << 4 ) | $ A
.DW ( $ 046 << 4 ) | $ A
.DW ( $ 047 << 4 ) | $ A
; BANK $09
.DW ( $ 048 << 4 ) | $ A
.DW ( $ 049 << 4 ) | $ A
.DW ( $ 04 A << 4 ) | $ A
.DW ( $ 04 B << 4 ) | $ A
.DW ( $ 04 C << 4 ) | $ A
.DW ( $ 04 D << 4 ) | $ A
.DW ( $ 04 E << 4 ) | $ A
.DW ( $ 04 F << 4 ) | $ A
; BANK $0A
.DW ( $ 050 << 4 ) | $ A
.DW ( $ 051 << 4 ) | $ A
.DW ( $ 052 << 4 ) | $ A
.DW ( $ 053 << 4 ) | $ A
.DW ( $ 054 << 4 ) | $ A
.DW ( $ 055 << 4 ) | $ A
.DW ( $ 056 << 4 ) | $ A
.DW ( $ 057 << 4 ) | $ A
; BANK $0B
.DW ( $ 058 << 4 ) | $ A
.DW ( $ 059 << 4 ) | $ A
.DW ( $ 05 A << 4 ) | $ A
.DW ( $ 05 B << 4 ) | $ A
.DW ( $ 05 C << 4 ) | $ A
.DW ( $ 05 D << 4 ) | $ A
.DW ( $ 05 E << 4 ) | $ A
.DW ( $ 05 F << 4 ) | $ A
; BANK $0C
.DW ( $ 060 << 4 ) | $ A
.DW ( $ 061 << 4 ) | $ A
.DW ( $ 062 << 4 ) | $ A
.DW ( $ 063 << 4 ) | $ A
.DW ( $ 064 << 4 ) | $ A
.DW ( $ 065 << 4 ) | $ A
.DW ( $ 066 << 4 ) | $ A
.DW ( $ 067 << 4 ) | $ A
; BANK $0D
.DW ( $ 068 << 4 ) | $ A
.DW ( $ 069 << 4 ) | $ A
.DW ( $ 06 A << 4 ) | $ A
.DW ( $ 06 B << 4 ) | $ A
.DW ( $ 06 C << 4 ) | $ A
.DW ( $ 06 D << 4 ) | $ A
.DW ( $ 06 E << 4 ) | $ A
.DW ( $ 06 F << 4 ) | $ A
; BANK $0E
.DW ( $ 070 << 4 ) | $ A
.DW ( $ 071 << 4 ) | $ A
.DW ( $ 072 << 4 ) | $ A
.DW ( $ 073 << 4 ) | $ A
.DW ( $ 074 << 4 ) | $ A
.DW ( $ 075 << 4 ) | $ A
.DW ( $ 076 << 4 ) | $ A
.DW ( $ 077 << 4 ) | $ A
; BANK $0F
.DW ( $ 078 << 4 ) | $ A
.DW ( $ 079 << 4 ) | $ A
.DW ( $ 07 A << 4 ) | $ A
.DW ( $ 07 B << 4 ) | $ A
.DW ( $ 07 C << 4 ) | $ A
.DW ( $ 07 D << 4 ) | $ A
.DW ( $ 07 E << 4 ) | $ A
.DW ( $ 07 F << 4 ) | $ A
; BANK $10
.DW ( $ 080 << 4 ) | $ A
.DW ( $ 081 << 4 ) | $ A
.DW ( $ 082 << 4 ) | $ A
.DW ( $ 083 << 4 ) | $ A
.DW ( $ 084 << 4 ) | $ A
.DW ( $ 085 << 4 ) | $ A
.DW ( $ 086 << 4 ) | $ A
.DW ( $ 087 << 4 ) | $ A
; BANK $11
.DW ( $ 088 << 4 ) | $ A
.DW ( $ 089 << 4 ) | $ A
.DW ( $ 08 A << 4 ) | $ A
.DW ( $ 08 B << 4 ) | $ A
.DW ( $ 08 C << 4 ) | $ A
.DW ( $ 08 D << 4 ) | $ A
.DW ( $ 08 E << 4 ) | $ A
.DW ( $ 08 F << 4 ) | $ A
; BANK $12
.DW ( $ 090 << 4 ) | $ A
.DW ( $ 091 << 4 ) | $ A
.DW ( $ 092 << 4 ) | $ A
.DW ( $ 093 << 4 ) | $ A
.DW ( $ 094 << 4 ) | $ A
.DW ( $ 095 << 4 ) | $ A
.DW ( $ 096 << 4 ) | $ A
.DW ( $ 097 << 4 ) | $ A
; BANK $13
.DW ( $ 098 << 4 ) | $ A
.DW ( $ 099 << 4 ) | $ A
.DW ( $ 09 A << 4 ) | $ A
.DW ( $ 09 B << 4 ) | $ A
.DW ( $ 09 C << 4 ) | $ A
.DW ( $ 09 D << 4 ) | $ A
.DW ( $ 09 E << 4 ) | $ A
.DW ( $ 09 F << 4 ) | $ A
; BANK $14
.DW ( $ 0 A0 << 4 ) | $ A
.DW ( $ 0 A1 << 4 ) | $ A
.DW ( $ 0 A2 << 4 ) | $ A
.DW ( $ 0 A3 << 4 ) | $ A
.DW ( $ 0 A4 << 4 ) | $ A
.DW ( $ 0 A5 << 4 ) | $ A
.DW ( $ 0 A6 << 4 ) | $ A
.DW ( $ 0 A7 << 4 ) | $ A
; BANK $15
.DW ( $ 0 A8 << 4 ) | $ A
.DW ( $ 0 A9 << 4 ) | $ A
.DW ( $ 0 AA << 4 ) | $ A
.DW ( $ 0 AB << 4 ) | $ A
.DW ( $ 0 AC << 4 ) | $ A
.DW ( $ 0 AD << 4 ) | $ A
.DW ( $ 0 AE << 4 ) | $ A
.DW ( $ 0 AF << 4 ) | $ A
; BANK $16
.DW ( $ 0B 0 << 4 ) | $ A
.DW ( $ 0B 1 << 4 ) | $ A
.DW ( $ 0B 2 << 4 ) | $ A
.DW ( $ 0B 3 << 4 ) | $ A
.DW ( $ 0B 4 << 4 ) | $ A
.DW ( $ 0B 5 << 4 ) | $ A
.DW ( $ 0B 6 << 4 ) | $ A
.DW ( $ 0B 7 << 4 ) | $ A
; BANK $17
.DW ( $ 0B 8 << 4 ) | $ A
.DW ( $ 0B 9 << 4 ) | $ A
.DW ( $ 0B A << 4 ) | $ A
.DW ( $ 0B B << 4 ) | $ A
.DW ( $ 0B C << 4 ) | $ A
.DW ( $ 0B D << 4 ) | $ A
.DW ( $ 0B E << 4 ) | $ A
.DW ( $ 0B F << 4 ) | $ A
; BANK $18
.DW ( $ 0 C0 << 4 ) | $ A
.DW ( $ 0 C1 << 4 ) | $ A
.DW ( $ 0 C2 << 4 ) | $ A
.DW ( $ 0 C3 << 4 ) | $ A
.DW ( $ 0 C4 << 4 ) | $ A
.DW ( $ 0 C5 << 4 ) | $ A
.DW ( $ 0 C6 << 4 ) | $ A
.DW ( $ 0 C7 << 4 ) | $ A
; BANK $19
.DW ( $ 0 C8 << 4 ) | $ A
.DW ( $ 0 C9 << 4 ) | $ A
.DW ( $ 0 CA << 4 ) | $ A
.DW ( $ 0 CB << 4 ) | $ A
.DW ( $ 0 CC << 4 ) | $ A
.DW ( $ 0 CD << 4 ) | $ A
.DW ( $ 0 CE << 4 ) | $ A
.DW ( $ 0 CF << 4 ) | $ A
; BANK $1A
.DW ( $ 0 D0 << 4 ) | $ A
.DW ( $ 0 D1 << 4 ) | $ A
.DW ( $ 0 D2 << 4 ) | $ A
.DW ( $ 0 D3 << 4 ) | $ A
.DW ( $ 0 D4 << 4 ) | $ A
.DW ( $ 0 D5 << 4 ) | $ A
.DW ( $ 0 D6 << 4 ) | $ A
.DW ( $ 0 D7 << 4 ) | $ A
; BANK $1B
.DW ( $ 0 D8 << 4 ) | $ A
.DW ( $ 0 D9 << 4 ) | $ A
.DW ( $ 0 DA << 4 ) | $ A
.DW ( $ 0 DB << 4 ) | $ A
.DW ( $ 0 DC << 4 ) | $ A
.DW ( $ 0 DD << 4 ) | $ A
.DW ( $ 0 DE << 4 ) | $ A
.DW ( $ 0 DF << 4 ) | $ A
; BANK $1C
.DW ( $ 0 E0 << 4 ) | $ A
.DW ( $ 0 E1 << 4 ) | $ A
.DW ( $ 0 E2 << 4 ) | $ A
.DW ( $ 0 E3 << 4 ) | $ A
.DW ( $ 0 E4 << 4 ) | $ A
.DW ( $ 0 E5 << 4 ) | $ A
.DW ( $ 0 E6 << 4 ) | $ A
.DW ( $ 0 E7 << 4 ) | $ A
; BANK $1D
.DW ( $ 0 E8 << 4 ) | $ A
.DW ( $ 0 E9 << 4 ) | $ A
.DW ( $ 0 EA << 4 ) | $ A
.DW ( $ 0 EB << 4 ) | $ A
.DW ( $ 0 EC << 4 ) | $ A
.DW ( $ 0 ED << 4 ) | $ A
.DW ( $ 0 EE << 4 ) | $ A
.DW ( $ 0 EF << 4 ) | $ A
; BANK $1E
.DW ( $ 0 F0 << 4 ) | $ A
.DW ( $ 0 F1 << 4 ) | $ A
.DW ( $ 0 F2 << 4 ) | $ A
.DW ( $ 0 F3 << 4 ) | $ A
.DW ( $ 0 F4 << 4 ) | $ A
.DW ( $ 0 F5 << 4 ) | $ A
.DW ( $ 0 F6 << 4 ) | $ A
.DW ( $ 0 F7 << 4 ) | $ A
; BANK $1F
.DW ( $ 0 F8 << 4 ) | $ A
.DW ( $ 0 F9 << 4 ) | $ A
.DW ( $ 0 FA << 4 ) | $ A
.DW ( $ 0 FB << 4 ) | $ A
.DW ( $ 0 FC << 4 ) | $ A
.DW ( $ 0 FD << 4 ) | $ A
.DW ( $ 0 FE << 4 ) | $ A
.DW ( $ 0 FF << 4 ) | $ A
;
# ENDIF
;
# IF ( MEMMGR = = MM_Z280 ) & FALSE
;
Z280_BNKSEL:
PUSH HL
PUSH DE
@ -4012,6 +4355,20 @@ Z2DMAADR1:
RET
# ENDIF
;
; Z280 SYSCALL VECTOR ENTRY POINT. TAKES STACK PARAMETER AS A BRANCH
; ADDRESS AND CALLS IT. ALLOWS ANY USER MODE CODE TO CALL INTO AN
; ARBITRARY LOCATION OF SYSTEM MODE CODE.
;
# IF ( MEMMGR = = MM_Z280 )
Z280_SYSCALL:
EX ( SP ), HL
LD ( Z280_SYSCALL_GO + 1 ), HL
POP HL
Z280_SYSCALL_GO:
CALL $ FFFF ; PARM SET ABOVE
.DB $ ED , $ 55 ; RETIL
# ENDIF
;
;==================================================================================================
; DEVICE DRIVERS
;==================================================================================================