Duodyne Work in Progress

- Updated DMA Driver
- Updated PCF I2C Driver

ReadMe.md

@@ -3,7 +3,7 @@
 **RomWBW ReadMe** \
 Version 3.3 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-07 Jul 2023
+02 Aug 2023
 
 # Overview
 

ReadMe.txt

@@ -1,6 +1,6 @@
 RomWBW ReadMe
 Wayne Warthen (wwarthen@gmail.com)
-07 Jul 2023
+02 Aug 2023
 
 
 

Source/Apps/Test/I2C/i2cscan.asm

@@ -5,12 +5,13 @@
 ; MARCO MACCAFERRI, HTTPS://WWW.MACCASOFT.COM
 ; HBIOS VERSION BY PHIL SUMMERS (B1ACKMAILER) DIFFICULTLEVELHIGH@GMAIL.COM
 ;
-PCF	.EQU	1
-P8X180	.EQU	0
-SC126	.EQU	0
-SC137	.EQU	0
+PCFECB		.EQU	0
+PCFDUO		.EQU	1
+P8X180		.EQU	0
+SC126		.EQU	0
+SC137		.EQU	0
 ;
-#IF (PCF)
+#IF (PCFECB)
 I2C_BASE 	.EQU  	0F0H
 PCF_ID   	.EQU  	0AAH
 CPU_CLK	 	.EQU  	12
@@ -20,6 +21,16 @@ PCF_RS1  	.EQU  	PCF_RS0+1
 PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
 #ENDIF
 ;
+#IF (PCFDUO)
+I2C_BASE 	.EQU  	056H
+PCF_ID   	.EQU  	0AAH
+CPU_CLK	 	.EQU  	12
+;
+PCF_RS0  	.EQU  	I2C_BASE
+PCF_RS1  	.EQU  	PCF_RS0+1
+PCF_OWN	 	.EQU  	(PCF_ID >> 1)        	; PCF'S ADDRESS IN SLAVE MODE
+#ENDIF
+;
 #IF (P8X180)
 I2C_BASE	.EQU	0A0h
 _sda		.EQU	0
@@ -153,8 +164,11 @@ lp5f:	ld	a,(addr)	; next address
 	jp	0
 
 signon:	.db	"I2C Bus Scanner"
-#IF (PCF)
-	.DB	" - PCF8584"
+#IF (PCFECB)
+	.DB	" - PCF8584 (ECB)"
+#ENDIF
+#IF (PCFDUO)
+	.DB	" - PCF8584 (Duodyne)"
 #ENDIF
 #IF (SC126)
 	.DB	" - SC126"
@@ -219,7 +233,7 @@ _cout:				; character
 	ret
 
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_start:
 PCF_START:
         LD     A,PCF_START_  
@@ -418,7 +432,7 @@ PCF_PINFAIL 	.DB	"PIN FAIL$"
 PCF_BBFAIL	.DB	"BUS BUSY$"
 ;
 ;-----------------------------------------------------------------------------
-#IF (PCF)
+#IF (PCFECB | PCFDUO)
 _i2c_stop:  
 PCF_STOP: 
 	LD   	A,PCF_STOP_	; issue 

Source/Doc/UserGuide.md

@@ -2308,26 +2308,35 @@ This application understands both FAT filesystems as well as CP/M filesystems.
 * Long filenames are not supported.  Files with long filenames will
   show up with their names truncated into the older 8.3 convention.
 * A FAT filesystem can be located on floppy or hard disk media.  For
-  hard disk media, the FAT filesystem must be located within a valid
-  FAT partition.
+  hard disk media, a valid FAT Filesystem partition must exist.
+* Note that CP/M (and compatible) OSes do not support all of the
+  filename characters that a modern computer does.  The following
+  characters are **not permitted** in a CP/M filename:
+
+  `< > . , ; : = ? * [ ] _ % | ( ) / \`
   
+  The FAT application does not auto-rename files when it encounters
+  invalid filenames.  It will just issue an error and quit.
+  Additionally, the error message is not very clear about the problem.
+
 ## FAT Filesystem Preparation
 
 In general, you can create media formatted with a FAT filesystem on
 your RomWBW computer or on your modern computer.  We will only be
 discussing the RomWBW-based approach here.
 
-In the case of a floppy disk, you can use the `FAT` application to
-format the floppy disk.  For example, if your floppy disk is on RomWBW
-disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite the
-floppy with a FAT filesystem and all previous contents will be lost.
-Once formatted this way, the floppy disk can be used in a floppy drive
-attached to a modern computer or it can be used on RomWBW using the
+In the case of a floppy disk, you can use the `FAT` application to 
+format the floppy disk.  The floppy disk must already be physically 
+formatted using RomWBW FDU or equivalent.  If your floppy disk is on 
+RomWBW disk unit 2, you could use `FAT FORMAT 2:`.  This will overwrite 
+the floppy with a FAT filesystem and all previous contents will be lost.
+Once formatted this way, the floppy disk can be used in a floppy drive 
+attached to a modern computer or it can be used on RomWBW using the 
 other `FAT` tool commands.
 
 In the case of hard disk media, it is necessary to have a FAT
 partition.  If you prepared your RomWBW hard disk media using the
-disk image process, then this partition will already be present and
+disk image process, then this partition will already be defined and
 you do not need to recreate it.  This default FAT partition is located
 at approximately 512MB from the start of your disk and it is 384MB in
 size.  So, your hard disk media must be 1GB or greater to use this
@@ -2375,8 +2384,13 @@ If your RomWBW system has multiple disk drives/slots, you can also just
 create a disk with your modern computer that is a dedicated FAT 
 filesystem disk.  You can use your modern computer to format the disk 
 (floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW 
-computer and access if using `FAT` based on its RomWBW unit number.
+computer and access it using `FAT` based on its RomWBW unit number.
 
+**WARNING**: Microsoft Windows will sometimes suggest reformatting
+partitions that it does not recognize.  If you are prompted to format
+a partition of your SD/CF Card when inserting the card into a Windows
+computer, you probably want to select Cancel.
+  
 ## FAT Application Usage
 
 Complete instructions for the `FAT` application are found in $doc_apps$.

Source/HBIOS/Config/DUO_std.asm

@@ -38,6 +38,8 @@ BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
 ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ;
+PCFENABLE	.SET	TRUE		; ENABLE PCF8584 I2C CONTROLLER
+;
 MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3

Source/HBIOS/cfg_duo.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -294,8 +297,7 @@ SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$40		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_DUO	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
-

Source/HBIOS/cfg_dyno.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -280,7 +283,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_master.asm

@@ -87,6 +87,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -368,7 +371,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_mbc.asm

@@ -54,6 +54,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -292,7 +295,7 @@ SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_mk4.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -289,7 +292,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_n8.asm

@@ -62,6 +62,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -282,7 +285,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rcz180.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -306,7 +309,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rcz280.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -310,7 +313,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rcz80.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -304,7 +307,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_rph.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -271,7 +274,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_s100.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -300,7 +303,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_sbc.asm

@@ -54,6 +54,9 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -270,7 +273,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_scz180.asm

@@ -60,6 +60,9 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -300,7 +303,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_z80retro.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -231,7 +234,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -46,6 +46,9 @@ KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -202,7 +205,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/cfg_zeta2.asm

@@ -57,6 +57,9 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
+PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
 SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
@@ -213,7 +216,7 @@ SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
 DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
 DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
+DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
 YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
 VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)

Source/HBIOS/dma.asm

@@ -2,6 +2,18 @@
 ; Z80 DMA DRIVER
 ;==================================================================================================
 ;
+#IF ((DMAMODE == DMAMODE_ECB) | (DMAMODE == DMAMODE_MBC))
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 1
+DMA_USEHALF	.EQU	TRUE
+#ENDIF
+;
+#IF (DMAMODE == DMAMODE_DUO)
+DMA_IO		.EQU	DMABASE
+DMA_CTL		.EQU	DMABASE + 3
+DMA_USEHALF	.EQU	FALSE
+#ENDIF
+;
 DMA_CONTINUOUS			.equ 	%10111101	; + Pulse
 DMA_BYTE			.equ 	%10011101	; + Pulse
 DMA_BURST 			.equ	%11011101	; + Pulse
@@ -30,21 +42,18 @@ DMA_FORCE			.EQU	0
 ; DMA CLOCK SPEED CONTROL - OPTION TO SWITCH TO HALF CLOCK SPEED. MOST SYSTEMS NEED THIS.
 ;==================================================================================================
 ;
-DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_MBC))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (DMA_USEHALF & (DMAMODE=DMAMODE_ECB))
-#DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
-#DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
-#ENDIF
-;
-#IF (!DMA_USEHALF)
-#DEFINE DMAIOHALF \;
-#DEFINE DMAIOFULL \;
+#IF (DMA_USEHALF)
+  #IF (DMAMODE=DMAMODE_MBC)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ AND ~%00001000 \ OUT (RTCIO),A
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+  #IF (DMAMODE=DMAMODE_ECB)
+    #DEFINE DMAIOHALF LD A,(HB_RTCVAL) \ OR %00001000 \ OUT (RTCIO),A 
+    #DEFINE DMAIOFULL PUSH AF \ LD A,(HB_RTCVAL) \ OUT (RTCIO),A \ POP AF
+  #ENDIF
+#ELSE
+  #DEFINE DMAIOHALF \;
+  #DEFINE DMAIOFULL \;
 #ENDIF
 ;
 ;==================================================================================================
@@ -54,11 +63,11 @@ DMA_USEHALF			.equ	TRUE	; USE CLOCK DIVIDER
 DMA_INIT:
 	CALL	NEWLINE
 	PRTS("DMA: IO=0x$")		; announce
-	LD	A, DMABASE
+	LD	A, DMA_IO
 	CALL	PRTHEXBYTE
 ;
 	LD	A,DMA_FORCE
-	out	(DMABASE+1),a		; force ready off
+	out	(DMA_CTL),a		; force ready off
 ;
 	DMAIOHALF
 ;
@@ -67,7 +76,7 @@ DMA_INIT:
 ;
 	ld	hl,DMACode		; program the
 	ld	b,DMACode_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	di
 	otir				; load dma
@@ -104,30 +113,30 @@ DMA_FAIL_FLAG:
 ;
 DMAProbe:
 	ld	a,DMA_RESET		; $C3
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,%01111101 		; R0-Transfer mode, A -> B, start address follows $7D
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$cc
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$dd
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$e5
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,$1a
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,DMA_LOAD		; $CF
-	out	(DMABASE),a
+	out	(DMA_IO),a
 ;
 	ld	a,DMA_READ_MASK_FOLLOWS	; set up ; $BB
-	out	(DMABASE),a		; for 
+	out	(DMA_IO),a		; for 
 	ld	a,%00011000		; register $18
-	out	(DMABASE),a		; read
+	out	(DMA_IO),a		; read
 	ld	a,DMA_START_READ_SEQUENCE	; $A7
-	out	(DMABASE),a
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)		; read in 
+	in	a,(DMA_IO)		; read in 
 	ld	c,a			; address
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 ;
 	xor	a			; is it
@@ -165,7 +174,7 @@ DMALDIR:
 ;
 	ld	hl,DMACopy		; program the
 	ld	b,DMACopy_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -174,8 +183,8 @@ DMALDIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 
@@ -211,7 +220,7 @@ DMAOTIR:
 ;
 	ld	hl,DMAOutCode		; program the
 	ld	b,DMAOut_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 
@@ -220,8 +229,8 @@ DMAOTIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -262,7 +271,7 @@ DMAINIR:
 ;
 	ld	hl,DMAInCode		; program the
 	ld	b,DMAIn_Len		; dma command
-	ld	c,DMABASE		; block
+	ld	c,DMA_IO		; block
 ;
 	DMAIOHALF
 ;
@@ -271,8 +280,8 @@ DMAINIR:
 	ei
 ;
 	ld	a,DMA_READ_STATUS_BYTE	; check status
-	out	(DMABASE),a		; of transfer
-	in	a,(DMABASE)		; set non-zero
+	out	(DMA_IO),a		; of transfer
+	in	a,(DMA_IO)		; set non-zero
 	and	%00111011		; if failed
 	sub	%00011011
 ;
@@ -306,31 +315,31 @@ DMAIn_Len 	.equ	$-DMAInCode
 ;
 DMARegDump:
 	ld	a,DMA_READ_MASK_FOLLOWS
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,%01111110
-	out	(DMABASE),a
+	out	(DMA_IO),a
 	ld	a,DMA_START_READ_SEQUENCE
-	out	(DMABASE),a
+	out	(DMA_IO),a
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 	ld	a,':'
 	call	COUT
 ;
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	c,a
-	in	a,(DMABASE)
+	in	a,(DMA_IO)
 	ld	b,a
 	call	PRTHEXWORD
 ;

Source/HBIOS/ds7rtc.asm

@@ -5,6 +5,11 @@
 ;
 ;==================================================================================================
 ;
+#IF (!PCFENABLE)
+	.ECHO	"*** DS7 DRIVER REQUIRES PCF DRIVER.  SET PCFENABLE!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+#ENDIF
+;
 DS7_OUT		.EQU	10000000B		; SELECT SQUARE WAVE FUNCTION
 DS7_SQWE	.EQU	00010000B		; ENABLE SQUARE WAVE OUTPUT
 DS7_RATE	.EQU	00000000B		; SET 1HZ OUPUT
@@ -31,6 +36,7 @@ DS7_CTL		.EQU	(DS7_OUT | DS7_SQWE | DS7_RATE)
 ; 12HR MODE IS CURRENTLY ASSUMED
 ;
 DS7RTC_INIT:
+	CALL	NEWLINE			; Formatting
 	PRTS("DS1307: $")		; ANNOUNCE DRIVER
 ;
 	LD	A,(PCF_FAIL_FLAG)	; CHECK IF THE

Source/HBIOS/hbios.asm

@@ -3179,6 +3179,9 @@ HB_INITTBL:
 #IF (CTCENABLE)
 	.DW	CTC_INIT
 #ENDIF
+#IF (PCFENABLE)
+	.DW	PCF_INIT
+#ENDIF
 #IF (DSKYENABLE)
   #IF (ICMENABLE)
 	.DW	ICM_INIT
@@ -3247,7 +3250,6 @@ HB_INITTBL:
 	.DW	INTRTC_INIT
 #ENDIF
 #IF (DS7RTCENABLE)
-	.DW	PCF8584_INIT
 	.DW	DS7RTC_INIT
 #ENDIF
 #IF (RP5RTCENABLE)
@@ -6164,6 +6166,7 @@ SIZ_BQRTC	.EQU	$ - ORG_BQRTC
 		.ECHO	SIZ_BQRTC
 		.ECHO	" bytes.\n"
 #ENDIF
+;
 #IF (SIMRTCENABLE)
 ORG_SIMRTC	.EQU	$
   #INCLUDE "simrtc.asm"
@@ -6172,15 +6175,16 @@ SIZ_SIMRTC	.EQU	$ - ORG_SIMRTC
 		.ECHO	SIZ_SIMRTC
 		.ECHO	" bytes.\n"
 #ENDIF
-#IF (DS7RTCENABLE & (DS7RTCMODE=DS7RTCMODE_PCF))
-ORG_PCF8584	.EQU	$
-  #INCLUDE "pcf8584.asm"
-SIZ_PCF8584	.EQU	$ - ORG_PCF8584
-		.ECHO	"PCF8584 occupies "
-		.ECHO	SIZ_PCF8584
+;
+#IF (PCFENABLE)
+ORG_PCF		.EQU	$
+  #INCLUDE "pcf.asm"
+SIZ_PCF		.EQU	$ - ORG_PCF
+		.ECHO	"PCF occupies "
+		.ECHO	SIZ_PCF
 		.ECHO	" bytes.\n"
 #ENDIF
-
+;
 #IF (DS7RTCENABLE)
 ORG_DS7RTC	.EQU	$
   #INCLUDE "ds7rtc.asm"

Source/HBIOS/pcf8584.asm → Source/HBIOS/pcf.asm

@@ -2,12 +2,11 @@
 ; PCF8584 I2C CLOCK DRIVER
 ;==================================================================================================
 ;
-PCF_BASE  	.EQU  0F0H
+PCF_BASE  	.EQU  PCFBASE
 PCF_ID   	.EQU  0AAH
-CPU_CLK	  	.EQU  12
-
+;
 PCF_RS0		.EQU  PCF_BASE
-PCF_RS1		.EQU  PCF_RS0+1
+PCF_RS1		.EQU  PCF_BASE+1
 PCF_OWN	 	.EQU  (PCF_ID >> 1)	 	; PCF'S ADDRESS IN SLAVE MODE
 ;
 ;T4LC512D	.EQU	10100000B		; DEVICE IDENTIFIER
@@ -37,10 +36,10 @@ PCF_STA  	.EQU  00000100B
 PCF_STO  	.EQU  00000010B
 PCF_ACK  	.EQU  00000001B
 ;
-PCF_START_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_STOP_		.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
-PCF_REPSTART_ 	.EQU  (	   PCF_ES0 | PCF_STA | PCF_ACK)
-PCF_IDLE_		.EQU  (PCF_PIN | PCF_ES0		| PCF_ACK)
+PCF_START_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_STOP_	.EQU  (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK)
+PCF_REPSTART_ 	.EQU  (PCF_ES0 | PCF_STA | PCF_ACK)
+PCF_IDLE_	.EQU  (PCF_PIN | PCF_ES0 | PCF_ACK)
 ;
 ; STATUS REGISTER BITS
 ;
@@ -54,13 +53,26 @@ PCF_AAS   	.EQU  00000100B
 PCF_LAB   	.EQU  00000010B
 PCF_BB		.EQU  00000001B
 ;
+; THE PCF8584 TARGETS A TOP I2C CLOCK SPEED OF 90KHZ AND SUPPORTS DIVIDERS FOR 
+; 3, 4.43, 6, 8 AND 12MHZ TO ACHEIVE THIS.
+;
+; +--------------------------------------------------------------------------------------------+
+; | div/clk |  2MHz |  4MHz  |  6MHz | 7.38Mhz |  10MHz | 12MHz |  16MHz | 18.432Mhz |  20MHz  |
+; +----------------------------------------------------------------------------------+---------+
+; |   3MHz  | 60Khz | 120Khz |       |         |        |       |        |           |         |
+; | 4.43MHz |       |  81Khz |       |         |        |       |        |           |         | 
+; |   6MHz  |       |        | 90Khz | 110Khz  |        |       |        |           |         |
+; |   8MHz  |       |        |       |  83Khz  | 112Khz |       |        |           |         |
+; |  12MHz  |       |        |       |         |        | 90Khz | 120Khz |   138Khz  |  150Khz |
+; +----------------------------------------------------------------------------------+---------+
+;
 ; CLOCK CHIP FREQUENCIES
 ;
 PCF_CLK3   	.EQU	000H
 PCF_CLK443 	.EQU	010H
 PCF_CLK6   	.EQU	014H
 PCF_CLK8   	.EQU	018H
-PCF_CLK12  	.EQU	01cH
+PCF_CLK12  	.EQU	01CH
 ;
 ; TRANSMISSION FREQUENCIES
 ;
@@ -69,6 +81,12 @@ PCF_TRNS45 	.EQU	001H	;  45 kHz */
 PCF_TRNS11 	.EQU	002H	;  11 kHz */
 PCF_TRNS15 	.EQU	003H	; 1.5 kHz */
 ;
+; BELOW VARIABLES CONTROL PCF CLOCK DIVISOR PROGRAMMING
+; HARD-CODED FOR NOW
+;
+PCF_CLK	  	.EQU	PCF_CLK12
+PCF_TRNS	.EQU	PCF_TRNS90
+;
 ; TIMEOUT AND DELAY VALUES (ARBITRARY)
 ;
 PCF_PINTO	.EQU	65000
@@ -78,40 +96,14 @@ PCF_LABDLY	.EQU	65000
 ;
 ; DATA PORT REGISTERS
 ;
-#IF (CPU_CLK = 443)
-PCF_CLK .EQU PCF_CLK4433
-#ELSE 
- #IF (CPU_CLK = 8)
-PCF_CLK .EQU PCF_CLK8
- #ELSE 
-  #IF (CPU_CLK = 12)
-PCF_CLK .EQU PCF_CLK12
-  #ELSE ***ERROR
-  #ENDIF
- #ENDIF	
-#ENDIF
-;
-; THE PCF8584 TARGETS A TOP I2C CLOCK SPEED OF 90KHZ AND SUPPORTS DIVIDERS FOR 
-; 3, 4.43, 6, 8 AND 12MHZ TO ACHEIVE THIS.
-;
-; +--------------------------------------------------------------------------------------------+
-; | div/clk |  2MHz |  4MHz  |  6MHz | 7.38Mhz |  10MHz | 12MHz |  16MHz | 18.432Mhz |  20MHz  |
-; +----------------------------------------------------------------------------------+---------+
-; |   3MHz  | 60Khz | 120Khz |       |         |        |       |        |           |         |
-; | 4.43MHz |       |  81Khz |       |         |        |       |        |           |         | 
-; |   6MHz  |       |        | 90Khz | 110Khz  |        |       |        |           |         |
-; |   8MHz  |       |        |       |  83Khz  | 112Khz |       |        |           |         |
-; |  12MHz  |       |        |       |         |        | 90Khz | 120Khz |   138Khz  |  150Khz |
-; +----------------------------------------------------------------------------------+---------+
-;
-PCF8584_INIT:
+PCF_INIT:
 	CALL	NEWLINE				; Formatting
-	PRTS("I2C: IO=0x$")
+	PRTS("PCF: IO=0x$")
 	LD	A, PCF_BASE
 	CALL	PRTHEXBYTE
 	CALL	PC_SPACE
-	CALL	PCF_INIT
-	CALL	NEWLINE
+	CALL	PCF_INITDEV
+	;CALL	NEWLINE
 	RET
 ;
 ; LINUX DRIVER BASED CODE
@@ -141,11 +133,13 @@ PCF_STOP:
 ;
 ;-----------------------------------------------------------------------------
 ;
-PCF_INIT:
+PCF_INITDEV:
 	LD	A,PCF_PIN   	; S1=80H: S0 SELECTED, SERIAL 
 	OUT	(PCF_RS1),A	; INTERFACE OFF
 	NOP
 	IN	A,(PCF_RS1)	; CHECK TO SEE S1 NOW USED AS R/W
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH	  	; CTRL. PCF8584 DOES THAT WHEN ESO
 	JR	NZ,PCF_FAIL	; IS ZERO
 ;
@@ -153,6 +147,8 @@ PCF_INIT:
 	OUT	(PCF_RS0),A	; EFFECTIVE ADDRESS IS (OWN <<1)
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT IS REALLY WRITTEN
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	PCF_OWN
 	JP	NZ,PCF_SETERR
 ;
@@ -160,14 +156,18 @@ PCF_INIT:
 	OUT	(PCF_RS1),A		; NEXT BYTE IN S2
 	NOP
 	IN	A,(PCF_RS1)
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	07FH
 	CP	PCF_ES1
 	JP	NZ,PCF_REGERR
 ;
-	LD	A,PCF_CLK	; LOAD CLOCK REGISTER S2
+	LD	A,PCF_CLK | PCF_TRNS	; LOAD CLOCK REGISTER S2
 	OUT	(PCF_RS0),A
 	NOP
 	IN	A,(PCF_RS0)	; CHECK IT'S REALLY WRITTEN, ONLY
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	AND	1FH	   	; THE LOWER 5 BITS MATTER
 	CP	PCF_CLK
 	JP	NZ,PCF_CLKERR
@@ -176,6 +176,8 @@ PCF_INIT:
 	OUT	(PCF_RS1),A  
 	NOP
 	IN	A,(PCF_RS1)  
+	;CALL	PC_SPACE
+	;CALL	PRTHEXBYTE
 	CP	+(PCF_PIN | PCF_BB)
 	JP	NZ,PCF_IDLERR
 ;
@@ -381,12 +383,12 @@ PCF_READI2C:
 ;
 ; POLL THE BUS BUSY BIT TO DETERMINE IF BUS IS FREE.
 ; RETURN WITH A=00H/Z STATUS IF BUS IS FREE
-; RETURN WITH A=FFH/NZ STATUS IF BUS
+; RETURN WITH A=FFH/NZ STATUS IF BUS IS BUSY
 ;
 ; AFTER RESET THE BUS BUSY BIT WILL BE SET TO 1 I.E. NOT BUSY
 ;
 PCF_WAIT_FOR_BB:
-	 LD	HL,PCF_BBTO
+	LD	HL,PCF_BBTO
 PCF_WFBB0:
 	IN	A,(PCF_RS1)
 	AND	PCF_BB

Source/HBIOS/std.asm

@@ -282,6 +282,7 @@ DMAMODE_Z180	.EQU	2		; Z180 INTEGRATED DMA
 DMAMODE_Z280	.EQU	3		; Z280 INTEGRATED DMA
 DMAMODE_RC	.EQU	4		; RCBUS Z80 DMA
 DMAMODE_MBC	.EQU	5		; MBC
+DMAMODE_DUO	.EQU	6		; DUO
 ;
 ; KEYBOARD MODE SELECTIONS
 ;

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.40"
+#DEFINE BIOSVER	"3.3.0-dev.41"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.40"
+	db	"3.3.0-dev.41"
 	endm