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Bringing trunk up to status of old "current"

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wayne
2012-10-23 08:19:24 +00:00
parent 01564959ad
commit 79ad7201cb
117 changed files with 31984 additions and 530 deletions
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424
trunk/XSource/Makefile
View File

@@ -1,6 +1,8 @@
#
# GCC based makefile
#
# 09/28/2012 2.2 dwg - updated for Mac OS X 10.8.2 Mountain Lion
#
# 06/18/2012 2.0 dgg - updated for v2.0
#
# 02/22/2012 1.5 dgg - modified for assembly under Linux
@@ -65,11 +67,11 @@
# do this with commands like the following at an OS command
# prompt or in a batch file:
#
# SET CONFIG=n8vem
# SET ROMSIZE=512
# SET CPU=80
# SET SYS=CPM
# SET ROMNAME=n8vem
# SET CONFIG=zeta
# SET ROMSIZE=512
# SET CPU=80
# SET SYS=CPM
# SET ROMNAME=zeta
#
# Note: use "make clean" to delete temporary and output files
#
@@ -84,47 +86,40 @@
#
# Uncomment and update values below to hardcode settings:
#
#CONFIG := n8vem
#ROMSIZE := 512
#CPU := 80
#SYS := CPM
#ROMNAME := n8vem
# Dougs Configuration
CONFIG := zeta
CONFIG := zeta
ROMSIZE := 512
CPU := 80
SYS := CPM
ROMNAME := dougzeta
CPU := 80
SYS := CPM
ROMNAME := zeta
ifndef ROMNAME
ROMNAME := $(CONFIG)
endif
CPMCP := bin/cpmcp
CVT := bin/CVT2MAC
SRC := ../Source/
ROMDSKFILES := ../RomDsk/$(SYS)_$(ROMSIZE)KB/*.* ../RomDsk/cfg_$(CONFIG)/*.* ../RomDsk/RomApps/*.*
ROMDSKFILES := ../RomDsk/$(SYS)_$(ROMSIZE)KB/*.* ../RomDsk/cfg_$(CONFIG)/*.* ../Apps/core/*.*
ifeq "$(SYS)" "CPM"
DOSBIN := bdosb01.bin
CPBIN := ccpb03.bin
CPASM := ccpb03.asm
else
DOSBIN := zsdos.bin
CPBIN := zcprw.bin
CPASM := zcprw.asm
endif
OUTDIR := ../Output
TASM := bin/tasm
TASM := bin/TASM
TASMTABS := bin
export TASMTABS
ASMOPT80 := -t$(CPU) -g3
ASMOPT85 := -t85 -g3
ASM80 := $(TASM) $(ASMOPT80) -b
ASM80 := $(TASM) $(ASMOPT80)
ASM85 := $(TASM) $(ASMOPT85)
ASMIMG := $(TASM) $(ASMOPT80) -b -fE5
@@ -132,7 +127,7 @@ NULL :=
SPACE := ${NULL} ${NULL}
%.bin: %.asm
$(ASM80) -b $< $@
$(ASM80) $< $@
%.com: %.asm
$(ASM80) $< $@
@@ -149,264 +144,197 @@ $(error Usage: make CONFIG=<config> ROMSIZE=[512|1024] CPU=[80|180] SYS=[CPM|ZSY
endif
endif
all: $(OUTDIR)/$(ROMNAME).rom $(OUTDIR)/$(ROMNAME).sys $(OUTDIR)/$(ROMNAME).com
all: tasm80.tab tasm85.tab $(OUTDIR)/$(ROMNAME).rom $(OUTDIR)/$(ROMNAME).sys $(OUTDIR)/$(ROMNAME).com
tasm80.tab: bin/TASM80.TAB
cp bin/TASM80.TAB tasm80.tab
tasm85.tab: bin/TASM85.TAB
cp bin/TASM85.TAB tasm85.tab
build.inc:
echo ';' >$@
/bin/echo ';' >$@
/bin/echo -n '; RomWBW Configured for '$(CONFIG)' ' >>$@
date >> $@
echo ; >>$@
/bin/echo ; >>$@
/bin/echo -n '#DEFINE TIMESTAMP "' >>$@
date '+%Y%m%d%H%M"' >>$@
echo ; >>$@
echo '#DEFINE VARIANT "WBW-$(USERNAME)"' >>$@
echo ; >>$@
echo ROMSIZE .EQU $(ROMSIZE) >>$@
echo ; >>$@
echo '#INCLUDE "config_'$(CONFIG)'.asm"' >>$@
echo ; >>$@
date '+%Y %m %d %H%M"' >>$@
/bin/echo ; >>$@
/bin/echo '#DEFINE VARIANT "WBW-$(USERNAME)"' >>$@
/bin/echo ; >>$@
/bin/echo ROMSIZE .EQU $(ROMSIZE) >>$@
/bin/echo ; >>$@
/bin/echo '#INCLUDE "config_'$(CONFIG)'.asm"' >>$@
/bin/echo ; >>$@
#loader.bin: loader.asm util.asm
# $(TASM) $(ASMOPT80) -b $<
loader.bin: loader.asm util.asm
loader.asm: ../Source/loader.asm
cp $< .
bin/cvt2mac $@
bnk1.asm: ../Source/bnk1.asm
cp $< .
bin/cvt2mac $@
bdosb01.asm: ../Source/bdosb01.asm
cp $< .
bin/cvt2mac $@
bootrom.bin : bootrom.asm memmgr.asm std.asm build.inc ver.inc
bootrom.bin : bootrom.asm std.asm build.inc ver.inc memmgr.asm config_$(CONFIG).asm
$(TASM) $(ASMOPT80) $< $@
bootrom.asm: ../Source/bootrom.asm config_$(CONFIG).asm
cp $< .
bin/cvt2mac $@
bootapp.bin : bootapp.asm std.asm build.inc ver.inc
bootapp.bin: bootapp.asm std.asm build.inc ver.inc
$(TASM) $(ASMOPT80) $< $@
bootapp.asm: ../Source/bootapp.asm
cp $< .
bin/cvt2mac $@
cbios.asm: ../Source/cbios.asm
cp $< .
bin/cvt2mac $@
config_$(CONFIG).asm: ../Source/config_$(CONFIG).asm
cp $< .
bin/cvt2mac $@
cnfgdata.inc: ../Source/cnfgdata.inc
cp $< .
bin/cvt2mac $@
dbgmon.asm: ../Source/dbgmon.asm
cp $< .
bin/cvt2mac $@
fd.asm: ../Source/fd.asm
cp $< .
bin/cvt2mac $@
fd_data.asm: ../Source/fd_data.asm
cp $< .
bin/cvt2mac $@
#hbios.asm: ../Source/hbios.asm
# cp $< .
# bin/cvt2mac $@
hbfill.asm: ../Source/hbfill.asm
cp $< .
bin/cvt2mac $@
ide.asm: ../Source/ide.asm
cp $< .
bin/cvt2mac $@
ide_data.asm: ../Source/ide_data.asm
cp $< .
bin/cvt2mac $@
infolist.inc: ../Source/infolist.inc
cp $< .
bin/cvt2mac $@
memmgr.asm: ../Source/memmgr.asm
cp $< .
bin/cvt2mac $@
pgzero.bin : pgzero.asm std.asm build.inc ver.inc
$(TASM) $(ASMOPT80) $< $@
pgzero.asm: ../Source/pgzero.asm
cp $< .
bin/cvt2mac $@
ppide.asm: ../Source/ppide.asm
cp $< .
bin/cvt2mac $@
ppide_data.asm: ../Source/ppide_data.asm
cp $< .
bin/cvt2mac $@
ppp.asm: ../Source/ppp.asm
cp $< .
bin/cvt2mac $@
ppp_data.asm: ../Source/ppp_data.asm
cp $< .
bin/cvt2mac $@
prefix.asm: ../Source/prefix.asm
cp $< .
bin/cvt2mac $@
prp.asm: ../Source/prp.asm
cp $< .
bin/cvt2mac $@
prp_data.asm: ../Source/prp_data.asm
cp $< .
bin/cvt2mac $@
romfill.bin: romfill.asm
$(TASM) $(ASMOPT80) -b $< $@
romfill.asm: ../Source/romfill.asm
cp $< .
bin/cvt2mac $@
sd.asm: ../Source/sd.asm
cp $< .
bin/cvt2mac $@
sd_data.asm: ../Source/sd_data.asm
cp $< .
bin/cvt2mac $@
std.asm: ../Source/std.asm
cp $< .
bin/cvt2mac $@
syscfg.asm: ../Source/syscfg.asm
cp $< .
bin/cvt2mac $@
uart.asm: ../Source/uart.asm
cp $< .
bin/cvt2mac $@
util.bin: util.asm
util.asm: ../Source/util.asm
cp $< .
bin/cvt2mac $@
vdu.asm: ../Source/vdu.asm
cp $< .
bin/cvt2mac $@
ver.inc: ../Source/ver.inc
cp $< .
bin/cvt2mac $@
zcprw.bin : zcprw.asm zcpr.asm
pgzero.bin: pgzero.asm std.asm build.inc ver.inc
$(TASM) $(ASMOPT80) $< $@
zcprw.bin: zcprw.asm zcpr.asm
$(TASM) $(ASMOPT85) $< $@
zsdos.bin : zsdos.asm zsdos.lib zsdos-gp.z80
zsdos.bin: zsdos.asm zsdos.lib zsdos-gp.z80
$(TASM) $(ASMOPT80) $< $@
hbfill.bin: hbfill.asm fd.asm ide.asm ppide.asm sd.asm prp.asm ppp.asm std.asm ver.inc build.inc
cbios.bin: cbios.asm fd_data.asm ide_data.asm ppide_data.asm sd_data.asm prp_data.asm ppp_data.asm uart.asm vdu.asm std.asm ver.inc build.inc infolist.inc
$(ASM80) -b -dBLD_SYS=SYS_$(SYS) $< $@
$(TASM) $(ASMOPT80) -dBLD_SYS=SYS_$(SYS) $< $@
cbios.asm: ../Source/cbios.asm
cp $< .
bin/cvt2mac $@
dbgmon.bin: dbgmon.asm std.asm ver.inc build.inc
dbgmon.bin: dbgmon.asm hbfill.bin std.asm ver.inc build.inc
syscfg.bin: syscfg.asm std.asm build.inc ver.inc
syscfg.bin: syscfg.asm std.asm build.inc ver.inc cnfgdata.inc
$(CPASM): ../Source/$(CPASM)
cp $< .
bin/cvt2mac $@
os.bin: $(CPBIN) $(DOSBIN) cbios.bin
cat $(CPBIN) $(DOSBIN) cbios.bin >>$@
rom0.bin: pgzero.bin bootrom.bin syscfg.bin loader.bin romfill.bin dbgmon.bin os.bin hbfill.bin
cat pgzero.bin bootrom.bin syscfg.bin loader.bin romfill.bin dbgmon.bin os.bin hbfill.bin >>$@
$(OUTDIR)/$(ROMNAME).rom: diskdefs rom0.bin rom1.bin $(ROMDISKFILES) $(OUTDIR)/$(ROMNAME).sys blank$(ROMSIZE)KB.dat
for d in ../Apps/*; do \
if test -e $$d/*.com; then \
cp $$d/*.com ../RomDsk/RomApps; \
fi; \
done;
for d in ../Apps/*; do \
if test -e $$d/*.man; then \
cp $$d/*.man ../RomDsk/RomApps; \
fi; \
done;
for d in ../Apps/*; do \
if test -e $$d/*.bsp; then \
cp $$d/*.bsp ../RomDsk/RomApps; \
fi; \
done;
cp blank$(ROMSIZE)KB.dat RomDisk.tmp
rom1.bin: pgzero.bin bootrom.bin syscfg.bin loader.bin bnk1.bin
cat pgzero.bin bootrom.bin syscfg.bin loader.bin bnk1.bin >>$@
$(OUTDIR)/$(ROMNAME).rom: rom0.bin rom1.bin $(ROMDISKFILES) $(OUTDIR)/$(ROMNAME).sys diskdefs
cp $(SRC)blank$(ROMSIZE)KB.dat RomDisk.tmp
$(CPMCP) -f rom$(ROMSIZE)KB RomDisk.tmp $(ROMDSKFILES) 0:
$(CPMCP) -f rom$(ROMSIZE)KB RomDisk.tmp ../Output/$(ROMNAME).sys 0:$(SYS).sys
cat rom0.bin rom1.bin RomDisk.tmp >>$@
diskdefs: bin/diskdefs
cp bin/diskdefs .
bin/cvt2mac diskdefs
$(OUTDIR)/$(ROMNAME).com: bootapp.bin syscfg.bin loader.bin bnk1.bin dbgmon.bin os.bin
cat bootapp.bin syscfg.bin loader.bin bnk1.bin dbgmon.bin os.bin >>$@
$(OUTDIR)/$(ROMNAME).com: bootapp.bin syscfg.bin loader.bin bnk1.bin dbgmon.bin sys.bin
cat bootapp.bin syscfg.bin loader.bin bnk1.bin dbgmon.bin sys.bin >>$@
$(OUTDIR)/$(ROMNAME).sys: prefix.bin os.bin
cat prefix.bin os.bin >>$@
$(OUTDIR)/$(ROMNAME).sys: prefix.bin sys.bin
cat prefix.bin sys.bin >>$(OUTDIR)/$(ROMNAME).sys
bdosb01.asm: $(SRC)bdosb01.asm
cp $< $@
$(CVT) $@
rom0.bin: pgzero.bin bootrom.bin syscfg.bin loader.bin romfill.bin dbgmon.bin sys.bin hbfill.bin
cat $< >>rom0.bin
bnk1.asm: $(SRC)bnk1.asm fd.asm ppide.asm
cp $(SRC)bnk1.asm $@
$(CVT) $@
rom1.bin: pgzero.bin bootrom.bin syscfg.bin loader.bin bnk1.bin
cat $< >>rom1.bin
bootapp.asm: $(SRC)bootapp.asm
cp $< $@
$(CVT) $@
sys.bin: $(CPBIN) $(DOSBIN) cbios.bin hbfill.bin ccpb03.bin
echo at sys.bin target, about to cat
cat $(CPBIN) $(DOSBIN) cbios.bin hbfill.bin >>$@
bootrom.asm: $(SRC)bootrom.asm
cp $< $@
$(CVT) $@
prefix.bin: prefix.asm
cbios.asm: $(SRC)cbios.asm
cp $< $@
$(CVT) $@
blank512KB.dat: ../Source/blank512KB.dat
cp $< .
ccpb03.asm: $(SRC)ccpb03.asm
cp $< $@
$(CVT) $@
blank1024KB.dat: ../Source/blank1024KB.dat
cp $< .
cnfgdata.inc: $(SRC)cnfgdata.inc
cp $< $@
$(CVT) $@
#cbios.asm: ../Source/cbios.asm
# cp $< .
# bin/cvt2mac $@
config_zeta.asm: $(SRC)config_zeta.asm
cp $< $@
$(CVT) $@
ccpb03.asm: ../Source/ccpb03.asm
cp $< .
bin/cvt2mac $@
dbgmon.asm: $(SRC)dbgmon.asm
cp $< $@
$(CVT) $@
diskdefs: $(SRC)diskdefs
cp $< $@
$(CVT) $@
fd.asm: $(SRC)fd.asm
cp $< $@
$(CVT) $@
fd_data.asm: $(SRC)fd_data.asm
cp $< $@
$(CVT) $@
hbfill.asm: $(SRC)hbfill.asm
cp $< $@
$(CVT) $@
ide_data.asm: $(SRC)ide_data.asm
cp $< $@
$(CVT) $@
infolist.inc: $(SRC)infolist.inc
cp $< $@
$(CVT) $@
loader.asm: $(SRC)loader.asm util.asm
cp $(SRC)loader.asm $@
$(CVT) $@
memmgr.asm: $(SRC)memmgr.asm
cp $< $@
$(CVT) $@
pgzero.asm: $(SRC)pgzero.asm
cp $< $@
$(CVT) $@
ppide.asm: $(SRC)ppide.asm
cp $< $@
$(CVT) $@
ppide_data.asm: $(SRC)ppide_data.asm
cp $< $@
$(CVT) $@
ppp_data.asm: $(SRC)ppp_data.asm
cp $< $@
$(CVT) $@
prefix.asm: $(SRC)prefix.asm
cp $< $@
$(CVT) $@
prp_data.asm: $(SRC)prp_data.asm
cp $< $@
$(CVT) $@
romfill.asm: $(SRC)romfill.asm
cp $< $@
$(CVT) $@
sd_data.asm: $(SRC)sd_data.asm
cp $< $@
$(CVT) $@
std.asm: $(SRC)std.asm
cp $< $@
$(CVT) $@
syscfg.asm: $(SRC)syscfg.asm config_$(CONFIG).asm cnfgdata.inc
cp $< $@
$(CVT) $@
uart.asm: $(SRC)uart.asm
cp $< $@
$(CVT) $@
util.asm: $(SRC)util.asm
cp $< $@
$(CVT) $@
vdu.asm: $(SRC)vdu.asm
cp $< $@
$(CVT) $@
ver.inc: $(SRC)ver.inc
cp $< $@
$(CVT) $@
clean:
rm -f *.asm *.obj *.bin *.com *.img *.rom *.lst *.exp *.tmp *.inc
rm -f *.tab *.TAB *.inc *.asm *.bin *.com *.img *.rom *.lst *.exp *.tmp
rm -f build.inc diskdefs
rm -f $(OUTDIR)/*.*
rm -f ../RomDsk/RomApps/*.*
rm -f diskdefs
rm -f blank$(ROMSIZE)KB.dat

7
trunk/XSource/README.TXT
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@@ -1,5 +1,6 @@
The Mac OS X Makefile is not fully debugged yet and is
not usable in it's current form. It will be updated and
posted when it is working correctly.
This build is experimental. Most likely it is working,
but you should be careful with it until it is verified.
Douglas Goodall
Santa Maria
9/2012

162
trunk/XSource/bin/8051.H Normal file
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@@ -0,0 +1,162 @@
;*************************************************************
;* TASM 8051/8052/80154 SFR BIT/BYTE MNEMONIC EQUATES LIST *
;*************************************************************
P0 .equ 080H ;Port 0
SP .equ 081H ;Stack pointer
DPL .equ 082H
DPH .equ 083H
PCON .equ 087H
TCON .equ 088H
TMOD .equ 089H
TL0 .equ 08AH
TL1 .equ 08BH
TH0 .equ 08CH
TH1 .equ 08DH
P1 .equ 090H ;Port 1
SCON .equ 098H
SBUF .equ 099H
P2 .equ 0A0H ;Port 2
IE .equ 0A8H
P3 .equ 0B0H ;Port 3
IP .equ 0B8H
T2CON .equ 0C8H ;8052, 80154 only
RCAP2L .equ 0CAH ;8052, 80154 only
RCAP2H .equ 0CBH ;8052, 80154 only
TL2 .equ 0CCH ;8052, 80154 only
TH2 .equ 0CDH ;8052, 80154 only
PSW .equ 0D0H
ACC .equ 0E0H ;Accumulator
B .equ 0F0H ;Secondary Accumulator
IOCON .equ 0F8H ;80154 only
;PORT 0 BITS
P0.0 .equ 080H ;Port 0 bit 0
P0.1 .equ 081H ;Port 0 bit 1
P0.2 .equ 082H ;Port 0 bit 2
P0.3 .equ 083H ;Port 0 bit 3
P0.4 .equ 084H ;Port 0 bit 4
P0.5 .equ 085H ;Port 0 bit 5
P0.6 .equ 086H ;Port 0 bit 6
P0.7 .equ 087H ;Port 0 bit 7
;PORT 1 BITS
P1.0 .equ 090H ;Port 1 bit 0
P1.1 .equ 091H ;Port 1 bit 1
P1.2 .equ 092H ;Port 1 bit 2
P1.3 .equ 093H ;Port 1 bit 3
P1.4 .equ 094H ;Port 1 bit 4
P1.5 .equ 095H ;Port 1 bit 5
P1.6 .equ 096H ;Port 1 bit 6
P1.7 .equ 097H ;Port 1 bit 7
;PORT 2 BITS
P2.0 .equ 0A0H ;Port 2 bit 0
P2.1 .equ 0A1H ;Port 2 bit 1
P2.2 .equ 0A2H ;Port 2 bit 2
P2.3 .equ 0A3H ;Port 2 bit 3
P2.4 .equ 0A4H ;Port 2 bit 4
P2.5 .equ 0A5H ;Port 2 bit 5
P2.6 .equ 0A6H ;Port 2 bit 6
P2.7 .equ 0A7H ;Port 2 bit 7
;PORT 3 BITS
P3.0 .equ 0B0H ;Port 3 bit 0
P3.1 .equ 0B1H ;Port 3 bit 1
P3.2 .equ 0B2H ;Port 3 bit 2
P3.3 .equ 0B3H ;Port 3 bit 3
P3.4 .equ 0B4H ;Port 3 bit 4
P3.5 .equ 0B5H ;Port 3 bit 5
P3.6 .equ 0B6H ;Port 3 bit 6
P3.7 .equ 0B7H ;Port 3 bit 7
;ACCUMULATOR BITS
ACC.0 .equ 0E0H ;Acc bit 0
ACC.1 .equ 0E1H ;Acc bit 1
ACC.2 .equ 0E2H ;Acc bit 2
ACC.3 .equ 0E3H ;Acc bit 3
ACC.4 .equ 0E4H ;Acc bit 4
ACC.5 .equ 0E5H ;Acc bit 5
ACC.6 .equ 0E6H ;Acc bit 6
ACC.7 .equ 0E7H ;Acc bit 7
;B REGISTER BITS
B.0 .equ 0F0H ;Breg bit 0
B.1 .equ 0F1H ;Breg bit 1
B.2 .equ 0F2H ;Breg bit 2
B.3 .equ 0F3H ;Breg bit 3
B.4 .equ 0F4H ;Breg bit 4
B.5 .equ 0F5H ;Breg bit 5
B.6 .equ 0F6H ;Breg bit 6
B.7 .equ 0F7H ;Breg bit 7
;PSW REGISTER BITS
P .equ 0D0H ;Parity flag
F1 .equ 0D1H ;User flag 1
OV .equ 0D2H ;Overflow flag
RS0 .equ 0D3H ;Register bank select 1
RS1 .equ 0D4H ;Register bank select 0
F0 .equ 0D5H ;User flag 0
AC .equ 0D6H ;Auxiliary carry flag
CY .equ 0D7H ;Carry flag
;TCON REGISTER BITS
IT0 .equ 088H ;Intr 0 type control
IE0 .equ 089H ;Intr 0 edge flag
IT1 .equ 08AH ;Intr 1 type control
IE1 .equ 08BH ;Intr 1 edge flag
TR0 .equ 08CH ;Timer 0 run
TF0 .equ 08DH ;Timer 0 overflow
TR1 .equ 08EH ;Timer 1 run
TF1 .equ 08FH ;Timer 1 overflow
;SCON REGISTER BITS
RI .equ 098H ;RX Intr flag
TI .equ 099H ;TX Intr flag
RB8 .equ 09AH ;RX 9th bit
TB8 .equ 09BH ;TX 9th bit
REN .equ 09CH ;Enable RX flag
SM2 .equ 09DH ;8/9 bit select flag
SM1 .equ 09EH ;Serial mode bit 1
SM0 .equ 09FH ;Serial mode bit 0
;IE REGISTER BITS
EX0 .equ 0A8H ;External intr 0
ET0 .equ 0A9H ;Timer 0 intr
EX1 .equ 0AAH ;External intr 1
ET1 .equ 0ABH ;Timer 1 intr
ES .equ 0ACH ;Serial port intr
ET2 .equ 0ADH ;Timer 2 intr
;Reserved 0AEH Reserved
EA .equ 0AFH ;Global intr enable
;IP REGISTER BITS
PX0 .equ 0B8H ;Priority level-External intr 0
PT0 .equ 0B9H ;Priority level-Timer 0 intr
PX1 .equ 0BAH ;Priority level-External intr 1
PT1 .equ 0BBH ;Priority level-Timer 1 intr
PS .equ 0BCH ;Priority level-Serial port intr
PT2 .equ 0BDH ;Priority level-Timer 2 intr
;Reserved 0BEH Reserved
PCT .equ 0BFH ;Global priority level
;IOCON REGISTER BITS 80154 ONLY
ALF .equ 0F8H ;Power down port condition
P1HZ .equ 0F9H ;Port 1 control
P2HZ .equ 0FAH ;Port 2 control
P3HZ .equ 0FBH ;Port 3 control
IZC .equ 0FCH ;Pullup select
SERR .equ 0FDH ;Serial reception error
T32 .equ 0FEH ;32 bit timer config
WDT .equ 0FFH ;Watchdog config
;T2CON REGISTER BITS 8052/80154 ONLY
CP/RL2 .equ 0C8H ;Timer 2 capture/reload flag
C/T2 .equ 0C9H ;Timer 2 timer/counter select
TR2 .equ 0CAH ;Timer 2 start/stop
EXEN2 .equ 0CBH ;Timer 2 external enable
TCLK .equ 0CCH ;TX clock flag
RCLK .equ 0CDH ;RX clock flag
EXF2 .equ 0CEH ;Timer 2 external flag
TF2 .equ 0CFH ;Timer 2 overflow

62
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@@ -0,0 +1,62 @@
The Telemark Assembler Copyright Notification
The files on this disk are:
Copyright 1985-1993 by Speech Technology Incorporated, all rights reserved.
Copyright 1998,1999,2001 by Thomas N. Anderson , all rights reserved.
The following files on this disk may be freely copied and shared with others:
TASM.EXE - TASM Assembler, executable
TASM48.TAB - 8048 Instruction definition table
TASM51.TAB - 8051 Instruction definition table
TASM65.TAB - 6502 Instruction definition table
TASM85.TAB - 8085 Instruction definition table
TASM80.TAB - Z80 Instruction definition table
TASM05.TAB - 6805 Instruction definition table
TASM68.TAB - 6800/6801/68HC11 Instruction definition table
TASM3210.TAB - TMS32010 Instruction definition table
TASM3225.TAB - TMS32025 Instruction definition table
TASM70.TAB - TMS7000 Instruction definition table
TASMMAN.HTM - TASM Documentation (HTML)
TASMTABS.HTM - TASM Documentation on individual tables (HTML)
TEST*.ASM - TASM test cases (one for each table)
TESTTABS.BAT - Batch script to execute the test cases
8051.H - Useful register definitions for the 8051
MOTO.H - Useful directive definitions for Motorola compatibility
README.TXT - Brief Explanation of Disk contents
COPYRIGH.TXT - Copyright notice
ORDERFRM.TXT - Registration Form
ORDERFRM.HTM - Registration Form (HTML)
RELNOTES.TXT - Release notes.
Although you may freely copy the above files, TASM is not 'free' or
'public domain'. It is copyrighted material which can be copied and
evaluated by people without registration, but those that use it on a
regular basis must register (see the ORDERFRM.TXT or ORDERFRM.HTM files).
The following files are to be copied only with the following
restrictions: The owner of this software may make as many copies of
the following as is deemed necessary as long as no possibility exists
for the software (or derivitive products) to be in use on more than
one machine at a time. Or, if a site license has been purchased, the
software can only be used on machines at that site.
TASM.C
TASMMAIN.C
MACRO.C
PARSE.C
STR.C
LOOKUP.C
WRTOBJ.C
FNAME.C
WRTOBJ.C
ERRLOG.C
TASM.H
Thomas N. Anderson
Squak Valley Software
837 Front Street South
Issaquah, WA 98027
email: andersontn@acm.org

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; A few handy defines to make TASM more like typcial
; motorola syntax
.MSFIRST ; Most Significant byte first
#define EQU .EQU
#define ORG .ORG
#define RMB .BLOCK
#define FCB .BYTE
#define FCC .TEXT
#define FDB .WORD
#define equ .EQU
#define org .ORG
#define rmb .BLOCK
#define fcb .BYTE
#define fcc .TEXT
#define fdb .WORD

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#!/bin/sh
#rem mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
#rem $Id: testtabs.bat 1.3 1998/02/25 12:27:04 toma Exp $
#rem mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
#rem Run TASM on all the table test files. Those that have
#rem extended instuctions use the -x option.
AS = ./TASM
OBJS = TEST48.obj TEST65.obj TEST51.obj TEST85.obj TESTZ80.obj
OBJS2= TEST05.obj TEST3210.obj TEST3225.obj TEST68.obj TEST70.obj TEST96.obj
all: $(OBJS) $(OBJS2)
# ./TASM -48 -x TEST48.ASM
# ./TASM -65 -x TEST65.ASM
# ./TASM -51 TEST51.ASM
# ./TASM -85 TEST85.ASM
# ./TASM -80 -x TESTZ80.ASM
# ./TASM -05 -x TEST05.ASM
# ./TASM -3210 TEST3210.ASM
# ./TASM -3225 TEST3225.ASM
# ./TASM -68 -x TEST68.ASM
# ./TASM -70 TEST70.ASM
# ./TASM -96 -x TEST96.ASM
TEST48.obj: TEST48.ASM
$(AS) -48 -x $<
TEST65.obj: TEST65.ASM
$(AS) -65 -x $<
TEST51.obj: TEST51.ASM
$(AS) -51 $<
TEST85.obj: TEST85.asm
$(AS) -85 $<
TESTZ80.obj: TESTZ80.ASM
$(AS) -80 -x $<
TEST05.obj: TEST05.ASM
$(AS) -05 -x $<
TEST3210.obj: TEST3210.ASM
$(AS) -3210 $<
TEST3225.obj: TEST3225.ASM
$(AS) -3225 $<
TEST68.obj: TEST68.ASM
$(AS) -68 -x $<
TEST70.obj: TEST70.ASM
$(AS) -70 $<
TEST96.obj: TEST96.ASM
$(AS) -96 -x $<
clean:
rm -r -f *.obj
rm -r -f *.lst
rm -r -f *.sym

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<!DOCTYPE HTML PUBLIC "-//SQ//DTD HTML 2.0 HoTMetaL + extensions//EN">
<HTML>
<HEAD>
<TITLE>Telemark Cross Assembler (TASM) Order Form</TITLE></HEAD>
<BODY>
<H1>TASM Order Form</H1>
<P>To order TASM, print this page, fill in the details and mail to SVS at:</P>
<P><I>Squak Valley Software<BR>837 Front Street South<BR>Issaquah, WA 98027<BR>USA</I></P>
<H2>TASM registration provides the user:</H2>
<UL>
<LI>Most Recent TASM Distribution Disk (includes tables for all supported
processor families)</LI>
<LI>TASM Source code (in C)</LI>
<LI>Bound TASM Manual</LI>
<LI>Telephone Support</LI>
<LI>Knowledge that they are supporting the development of useful but
inexpensive software</LI></UL>
<TABLE BORDER="BORDER">
<TR>
<TD ALIGN="LEFT" VALIGN="MIDDLE"><B>Item Description</B></TD>
<TD ALIGN="CENTER"><B>Unit Price</B></TD>
<TD ALIGN="CENTER" VALIGN="MIDDLE"><B>Amount Extended</B></TD></TR>
<TR>
<TD>TASM 3.2 Registration </TD>
<TD ALIGN="RIGHT" VALIGN="MIDDLE">$40</TD>
<TD>______________________</TD></TR>
<TR>
<TD>TASM 3.2 Site Registration</TD>
<TD ALIGN="RIGHT" VALIGN="MIDDLE">$90</TD>
<TD>______________________</TD></TR>
<TR>
<TD>TASM 3.2 Update for registered users</TD>
<TD ALIGN="RIGHT">$10</TD>
<TD>______________________</TD></TR>
<TR>
<TD></TD>
<TD></TD>
<TD></TD></TR>
<TR>
<TD><B>Subtotal</B></TD>
<TD></TD>
<TD>______________________</TD></TR>
<TR>
<TD>Tax (Washington State residents add 8.6%)</TD>
<TD></TD>
<TD>______________________</TD></TR>
<TR>
<TD>Billing Fee (for orders not accompanied by payment)</TD>
<TD ALIGN="RIGHT">$10</TD>
<TD>______________________</TD></TR>
<TR>
<TD>Foreign postage and handling</TD>
<TD ALIGN="RIGHT">$10</TD>
<TD>______________________</TD></TR>
<TR>
<TD><B>Total</B></TD>
<TD></TD>
<TD>______________________</TD></TR></TABLE>
<UL>
<LI>All payments must be in US funds drawn on a US bank (No credit card
payments) </LI>
<LI>Orders outside North America please add the indicated foreign postage and
handling.</LI>
<LI>Purchase orders allowed from North America only (all others must be
prepaid).</LI></UL>
<H2>Ship To:</H2>
<TABLE BORDER="BORDER">
<TR>
<TD>Name</TD>
<TD>____________________________________</TD></TR>
<TR>
<TD>Company</TD>
<TD> ___________________________________</TD></TR>
<TR>
<TD>Street Address</TD>
<TD>____________________________________</TD></TR>
<TR>
<TD>City, State/Province, Postal Code</TD>
<TD>____________________________________</TD></TR>
<TR>
<TD>Country</TD>
<TD> ____________________________________</TD></TR></TABLE></BODY></HTML>

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ORDERING INFORMATION (TASM Version 3.2)
TASM is distributed as shareware. The shareware portion of the
product may be freely copied and used for evaluation purposes. Use
of TASM beyond a reasonable evaluation period requires registration.
Registered users receive the following benefits:
1. The recent version of TASM.
2. TASM source code (in C).
3. Bound TASM manual.
4. Telephone support.
5. Knowledge that they are supporting the development of
useful but inexpensive software.
DESCRIPTION UNIT PRICE PRICE
--------------------------------------------------------------------
TASM Registration (TASM disk, manual, & source) $40.00 _______
TASM Site Registration (for sites with multiple 90.00 _______
users. Includes same materials as above.)
TASM User's Manual (included above) 10.00 _______
TASM update for registered users 10.00 _______
(latest disk (with source), and manual)
Subtotal _______
Tax (Washington state residents add 8.6%) _______
Billing fee (for orders not accompanied by check) 10.00 _______
Foreign postage (outside North America) add $10.00 _______
(Foreign orders must be in US funds drawn on a US bank)
TOTAL (post paid) _______
Which processors are of primary interest to you? __________________
(This is for our information only. You will
receive all current TASM tables).
Shipping Address:
______________________________________________
______________________________________________
______________________________________________
Send check or money order (no credit cards) to: Squak Valley Software
837 Front Street South
Issaquah, WA 98027

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This is the registered distribution disk for TASM - the Telemark Assembler.
The files on the disk are:
Readme.1st - This file
Tasm32.zip - TASM distribution archive, Version 3.2
To extract the archive use pkunzip or pkzip for windows and extract
into the desired directory for TASM.
See the README.TXT file after extraction.
See the BUILD.TXT file for notes on building from the source archive.
Thomas N. Anderson
Squak Valley Software
837 Front Street South
Issaquah, WA 98027
andersontn@acm.org

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This is the shareware distribution disk for TASM - a table driven
assembler. The files on the disk include:
TASM.EXE - TASM Assembler, executable
TASM48.TAB - 8048 Instruction definition table
TASM51.TAB - 8051 Instruction definition table
TASM65.TAB - 6502 Instruction definition table
TASM85.TAB - 8085 Instruction definition table
TASM80.TAB - Z80 Instruction definition table
TASM05.TAB - 6805 Instruction definition table
TASM3210.TAB - TMS32010 Instruction definition table
TASM3225.TAB - TMS32025 Instruction definition table
TASM68.TAB - 6800/6801 Instruction definition table
TASM70.TAB - TMS7000 Instruction definition table
TASM96.TAB - 8096 Instruction definition table
TEST*.ASM - TASM test files (one for each table).
TESTTABS.BAT - Batch script to execute TASM for each test case.
8051.H - Useful register definitions for the 8051
MOTO.H - Useful directive definitions for Motorola compatibility
TASMMAN.HTM - TASM User's Manual (HTML)
TASMTABS.HTM - TASM Table Description Manual (HTML)
README.TXT - Brief Explanation of Disk contents
COPYRIGH.TXT - Copyright notice
ORDERFRM.TXT - Order Form (plain text)
ORDERFRM.HTM - Order Form (HTML)
For a brief discription of how to run TASM, execute TASM with no command
line parameters.
If you find TASM useful, why not register? Unregistered use of TASM
beyond a 30 day evaluation period is a violation of the license.
For the $40.00 registration fee you get:
1. Latest version of TASM.
2. Source code (in C).
3. Bound Manual.
4. email support.
To register, use the form on the disk (ORDERFRM.TXT), or just send
$40.00 check or money order to:
Thomas N. Anderson
Squak Valley Software
837 Front Street South
Issaquah, WA 98027
andersontn@acm.org

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TASM RELEASE NOTES [September 2001]
RELEASE DATE/VERSION DESCRIPTION
-----------------------------------------------------------------------
10/01/85 Version 2.0 First version with external table def files.
01/01/86 Version 2.1 Added '*=' and '=' directives as
alternatives to .ORG and .EQU (for
more complete MOS Technology compatibility).
Enhanced parsing algorithm so it can
deal with more than one variable expression.
Added -d option
02/14/86 Version 2.2 Modified so instruction set definition
tables don't need to be compiled in.
Added 8051 tables.
Increased the number of labels allowed.
03/31/87 Version 2.3 Fixed bug that prevented location 0xffff
from being used and written to object file.
Most changes in wrtobj() and pr_hextab().
05/01/87 Version 2.4 Added multiple byte opcode support.
Added shift/or operation capability to
args from instruction set definition table.
Converted to MS C version 3.0
Added hashing to instruction set table
lookups to speed up.
11/01/87 Version 2.5 Added DB and DW directives.
Added escape capability in TEXT strings.
Fixed inst_lookup function to treat the
multiple wild card case a little better
Added 8080/8085 and Z80 tables.
Added sorting on label table.
Increased size of read buffer.
Speed enhancements.
Added DEFCONT (macro continuation) directive.
Converted to Microsoft C 5.0 compiler.
Added 6805 table (and related modops).
Added Z80 bit modop.
Minor speed up.
Fixed bug that enters infinite loop
when a macro invocation has no closing paren.
Added some three arg MODOPs.
8/15/88 Version 2.6.1 Added CODES/NOCODES directives
Fixed bug preventing directives in multiple
statement lines.
2.6.2 Added COMB_NIBBLE and COMB_NIBBLE_SWAP MODOPS
2/1/89 Version 2.7 Removed ad hoc heap and now use malloc()
Added MSFIRST and LSFIRST directives.
Added EXPORT directive.
Added symbol table file (-s flag).
Added NSEG/CSEG/BSEG/DSEG/XSEG directives
and the SYM/AVSYM directives to support
the Avocet avsim51 simulator.
Added support for TMS320.
Added -r flag to set read buffer size.
Converted expression evaluation from
signed 16 bit to signed 32 bit (enabling
apparent ability to use signed or unsigned
16 bit values).
4/20/89 Version 2.7.1 Return 0x20000 for undefined labels so that
(label+x) type stuff won't confuse zero
page addressing.
Added duplicate label error message on pass 1.
6/20/89 Version 2.7.2 Improved macro expansion capability.
No expansion in comments.
Context sensitive identifiers.
Revised exit codes.
6/27/89 Version 2.7.3 Added -a flag for strict error checking:
(1) No outer parens around expressions.
(2) Error message if unused argbytes remain
(3) Duplicate labels
Fixed so ']' can terminate expressions.
Removed parse() from tasm.c
8/19/89 Version 2.7.4 Added Motorola hex object format.
Fixed bug that complained when \ immediately
followed a opcode with no args.
Slightly improved error reporting (Errorbuf).
10/31/89 Version 2.7.5 Added TMS7000 support.
Fixed argv[] bug (only dimensioned to 10 in pass1.
12/23/89 Version 2.7.6 Improved handling of % (modulo vs binary
prefix ambiguity).
Fixed list so lines with more than
6 bytes go on second line.
03/04/90 Version 2.7.7 Fixed bug that left off 2 bytes if ORG
went backwards and all 64K was used.
Added a command line option to ignore
case on labels.
Added a couple MODOP rules for TMS9900.
Allow double quoted text strings for BYTE.
04/15/90 Version 2.7.8 Fixed expression evaluator bug (paren popping)
and changed expression evaluator to a more
conventional left to right evaluation order.
Added TURBOC ifdef's (from Lance Jump).
08/20/90 Version 2.8 Primarily a documentation update.
Added error check for AJMP/ACALL off of
current 2K block (8051).
10/15/90 Version 2.8.1 Minor speed up in label searching.
Fixed word addressing for TMS320
Version 2.8.2 Local labels.
More label table format options (long form
suppress local labels).
11/30/90 Version 2.8.3 Turbo C conversion.
DS directive added.
12/27/90 Version 2.8.4 Added COMMENTCHAR directive to change the
comment indicator in the first column.
This was done to support the assembly
files from the small C compiler (sc11)
for the 68CH11.
02/14/91 Version 2.8.5 Added LOCALLABELCHAR directive to
override the default "_" as the
prefix for local labels.
03/18/91 Version 2.8.6 Added some MODOPs in support of TMS320C25
04/20/91 Version 2.8.7 Fixed sign extend bug in CSWAP modop.
Increased MAXLABS to 10000 for big version.
05/05/91 Version 2.8.8 Fixed pointer bug in debug output in sort_labels().
05/20/91 Version 2.9 TMS320C25 table along with some MODOP enhancements
for it.
TASMTABS.DOC updated (but not TASM.DOC)
08/09/91 Version 2.9.1 Nested conditionals.
04/01/92 Version 2.9.2 Fixed long label clobber problem in
find_label() and save_label. Syntax
errors could result in a comment line
after an instruction being lumped together
with a label resulting in a long label.
The label functions were not testing for
labels that exceed the specified size.
Added CHK directive.
Added REL3 MODOD to support uPD75xxx.
Delinting and more ANSIfication.
Modifications due to feedback from B Provo:
Added FILL directive.
Allow multiple labels for EXPORT directive.
Allow address with END directive.
TASM.DOC update
11/25/92 Version 2.9.3 Improved error reporting for mismatched quotes.
Disallow the single quote character constants.
Convert to BCC++ 3.1
Provide filename,linenum on all error messages.
Modify format of error messages for compatibility
with the Brief editor.
Added ECHO directive to send output to console.
Performance improvements in macro processing.
"Type Safe" conversion (compatible with C++).
Improved error reporting for imbalanced ifdefs.
01/29/93 Version 2.9.4 Added rules for 8096 (I1,I2,I3,I4,I5,I6).
Generate error message on forward reference
in EQUate statements.
Eliminated -a option for enabling the detection
of branches of 2K page for 8051. This
is now built into the table.
Allow white space in double quotes for BYTE
directive. This previously worked for TEXT,
but not BYTE.
Fixed defect with Z80 4 byte indexed instructions.
Fixed macro defect. If the macro definition has
args but the invocation does not some garbage
gets expanded into the source line.
Z80 OTDR opcode was incorrect.
Z80 IN0/OUT0/INA instructions did not require
the parens around the args.
Some experimental support for windows verson of TASM.
10/24/93 Version 3.0 Documentation update. TASM.DOC, TASMTABS.DOC
and RELNOTES.DOC updated, but the functionality
remains unchanged from version 2.9.4.
06/16/94 Version 3.0.1 Multiple macros on the same line.
Fixed problem with -c with >8000h bytes used goes bonkers
Corrected word addressing problem for BLOCK/DS directives.
Allow escaped quotes in TEXT strings.
11/30/97 Version 3.1 LINUX support.
Protect mode version (tasmp) with better memory
management (more labels allowed, etc.)
Added an 8096 table.
Added Logical NOT unary operator.
Added an object file format with word address
09/01/01 version 3.2 Increased LINESIZ to 512 to enable use of longer macros.
Eliminated -r command line option (to set
read buffer size - Now obsolete.)
Improved list() function to put a max of
six bytes per line to avoid problems with
directives that generate large blocks of
object code (i.e. .FILL).
Built as a 32 bit version using MS C++ 6.0

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"TASM 6805 Assembler. "
/***************************************************************************
/* $Id
/***************************************************************************
/* This is the instruction set definition table for the 6805 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, April 1988.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ADC #* A9 2 NOP 1
ADC ,X F9 1 NOP 1
ADC *,X D9 3 MZERO 1
ADC * C9 3 MZERO 1
ADD #* AB 2 NOP 1
ADD ,X FB 1 NOP 1
ADD *,X DB 3 MZERO 1
ADD * CB 3 MZERO 1
AND #* A4 2 NOP 1
AND ,X F4 1 NOP 1
AND *,X D4 3 MZERO 1
AND * C4 3 MZERO 1
ASLA "" 48 1 NOP 1
ASLX "" 58 1 NOP 1
ASL ,X 78 1 NOP 1
ASL *,X 68 2 NOP 1
ASL * 38 2 NOP 1
ASRA "" 47 1 NOP 1
ASRX "" 57 1 NOP 1
ASR ,X 77 1 NOP 1
ASR *,X 67 2 NOP 1
ASR * 37 2 NOP 1
BCC * 24 2 R1 1
BCLR *,* 11 2 MBIT 1
BCS * 25 2 R1 1
BEQ * 27 2 R1 1
BHCC * 28 2 R1 1
BHCS * 29 2 R1 1
BHI * 22 2 R1 1
BHS * 24 2 R1 1
BIH * 2F 2 R1 1
BIL * 2E 2 R1 1
BIT #* A5 2 NOP 1
BIT ,X F5 1 NOP 1
BIT *,X D5 3 MZERO 1
BIT * C5 3 MZERO 1
BLO * 25 2 R1 1
BLS * 23 2 R1 1
BMC * 2C 2 R1 1
BMI * 2B 2 R1 1
BMS * 2D 2 R1 1
BNE * 26 2 R1 1
BPL * 2A 2 R1 1
BRA * 20 2 R1 1
BRCLR *,*,* 01 3 MBIT 1
BRN * 21 2 R1 1
BRSET *,*,* 00 3 MBIT 1
BSET *,* 10 2 MBIT 1
BSR * AD 2 R1 1
CLC "" 98 1 NOP 1
CLI "" 9A 1 NOP 1
CLRA "" 4F 1 NOP 1
CLRX "" 5F 1 NOP 1
CLR ,X 7F 1 NOP 1
CLR *,X 6F 2 NOP 1
CLR * 3F 2 NOP 1
CMP #* A1 2 NOP 1
CMP ,X F1 1 NOP 1
CMP *,X D1 3 MZERO 1
CMP * C1 3 MZERO 1
CMPX #* A3 2 NOP 1 /* equivalent to CPX */
CMPX ,X F3 1 NOP 1
CMPX *,X D3 3 MZERO 1
CMPX * C3 3 MZERO 1
COMA "" 43 1 NOP 1
COMX "" 53 1 NOP 1
COM ,X 73 1 NOP 1
COM *,X 63 2 NOP 1
COM * 33 2 NOP 1
CPX #* A3 2 NOP 1
CPX ,X F3 1 NOP 1
CPX *,X D3 3 MZERO 1
CPX * C3 3 MZERO 1
DECA "" 4A 1 NOP 1
DECX "" 5A 1 NOP 1
DEX "" 5A 1 NOP 1
DEC ,X 7A 1 NOP 1
DEC *,X 6A 2 NOP 1
DEC * 3A 2 NOP 1
EOR #* A8 2 NOP 1
EOR ,X F8 1 NOP 1
EOR *,X D8 3 MZERO 1
EOR * C8 3 MZERO 1
INCA "" 4C 1 NOP 1
INCX "" 5C 1 NOP 1
INX "" 5C 1 NOP 1
INC ,X 7C 1 NOP 1
INC *,X 6C 2 NOP 1
INC * 3C 2 NOP 1
JMP ,X FC 1 NOP 1
JMP *,X DC 3 MZERO 1
JMP * CC 3 MZERO 1
JSR ,X FD 1 NOP 1
JSR *,X DD 3 MZERO 1
JSR * CD 3 MZERO 1
LDA #* A6 2 NOP 1
LDA ,X F6 1 NOP 1
LDA *,X D6 3 MZERO 1
LDA * C6 3 MZERO 1
LDX #* AE 2 NOP 1
LDX ,X FE 1 NOP 1
LDX *,X DE 3 MZERO 1
LDX * CE 3 MZERO 1
LSLA "" 48 1 NOP 1
LSLX "" 58 1 NOP 1
LSL ,X 78 1 NOP 1
LSL *,X 68 2 NOP 1
LSL * 38 2 NOP 1
LSRA "" 44 1 NOP 1
LSRX "" 54 1 NOP 1
LSR ,X 74 1 NOP 1
LSR *,X 64 2 NOP 1
LSR * 34 2 NOP 1
MUL "" 42 1 NOP 4 /* HC05C4 only */
NEGA "" 40 1 NOP 1
NEGX "" 50 1 NOP 1
NEG ,X 70 1 NOP 1
NEG *,X 60 2 NOP 1
NEG * 30 2 NOP 1
NOP "" 9D 1 NOP 1
ORA #* AA 2 NOP 1
ORA ,X FA 1 NOP 1
ORA *,X DA 3 MZERO 1
ORA * CA 3 MZERO 1
ROLA "" 49 1 NOP 1
ROLX "" 59 1 NOP 1
ROL ,X 79 1 NOP 1
ROL *,X 69 2 NOP 1
ROL * 39 2 NOP 1
RORA "" 46 1 NOP 1
RORX "" 56 1 NOP 1
ROR ,X 76 1 NOP 1
ROR *,X 66 2 NOP 1
ROR * 36 2 NOP 1
RSP "" 9C 1 NOP 1
RTI "" 80 1 NOP 1
RTS "" 81 1 NOP 1
SBC #* A2 2 NOP 1
SBC ,X F2 1 NOP 1
SBC *,X D2 3 MZERO 1
SBC * C2 3 MZERO 1
SEC "" 99 1 NOP 1
SEI "" 9B 1 NOP 1
STA ,X F7 1 NOP 1
STA *,X D7 3 MZERO 1
STA * C7 3 MZERO 1
STOP "" 8E 1 NOP 2 /* M146805 CMOS only */
STX ,X FF 1 NOP 1
STX *,X DF 3 MZERO 1
STX * CF 3 MZERO 1
SUB #* A0 2 NOP 1
SUB ,X F0 1 NOP 1
SUB *,X D0 3 MZERO 1
SUB * C0 3 MZERO 1
SWI "" 83 1 NOP 1
TAX "" 97 1 NOP 1
TSTA "" 4D 1 NOP 1
TSTX "" 5D 1 NOP 1
TST ,X 7D 1 NOP 1
TST *,X 6D 2 NOP 1
TST * 3D 2 NOP 1
TXA "" 9F 1 NOP 1
WAIT "" 8F 1 NOP 2 /* M146805 CMOS only */

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"TASM TMS32010 Assembler."
/****************************************************************************
/* $Id: tasm3210.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the TMS32010 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/*
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT MASK */
/*-------------------------------------------*/
/* Generate opcodes high byte first */
.MSFIRST
/* Don't use '*' as the wild card since it is used for indirect addressing */
/* In this table '@' is the wild card indicating where expression may appear*/
.ALTWILD
/* Use word addressing (not byte addressing)
.WORDADDRS
/* All shift/and stuff applies to opcodes, not args
.NOARGSHIFT
.REGSET *+ A0 1
.REGSET *- 90 1
.REGSET * 80 1
ABS "" 7F88 2 NOP 1
ADD !,@,@ 0000 2 T1 1 8 0F00
ADD !,@ 0008 2 T1 1 8 0F00
ADD ! 0008 2 NOP 1
ADD @,@ 0000 2 TDMA 1 8 0F00
ADD @ 0000 2 T1 1 0 007F
ADDH !,@ 6000 2 T1 1 0 01
ADDH ! 6008 2 NOP 1
ADDH @ 6000 2 T1 1 0 007F
ADDS !,@ 6100 2 T1 1 0 01
ADDS ! 6108 2 NOP 1
ADDS @ 6100 2 T1 1 0 007F
AND !,@ 7900 2 T1 1 0 01
AND ! 7908 2 NOP 1
AND @ 7900 2 T1 1 0 7F
APAC "" 7F8F 2 NOP 1
B @ F900 4 SWAP 1
BANZ @ F400 4 SWAP 1
BGEZ @ FD00 4 SWAP 1
BGZ @ FC00 4 SWAP 1
BIOZ @ F600 4 SWAP 1
BLEZ @ FB00 4 SWAP 1
BLZ @ FA00 4 SWAP 1
BNZ @ FE00 4 SWAP 1
BV @ F500 4 SWAP 1
BZ @ FF00 4 SWAP 1
CALA "" 7F8C 2 NOP 1
CALL @ F800 4 SWAP 1
DINT "" 7F81 2 NOP 1
DMOV !,@ 6900 2 T1 1 0 01
DMOV ! 6908 2 NOP 1
DMOV @ 6900 2 T1 1 0 007F
EINT "" 7F82 2 NOP 1
IN !,@,@ 4000 2 T1 1 8 0700
IN !,@ 4008 2 T1 1 8 0700
IN @,@ 4000 2 TDMA 1 8 0700
LAC !,@,@ 2000 2 T1 1 8 0F00
LAC !,@ 2008 2 T1 1 8 0F00
LAC ! 2008 2 NOP 1
LAC @,@ 2000 2 TDMA 1 8 0F00
LAC @ 2000 2 T1 1 0 007F
LACK @ 7E00 2 T1 1 0 00FF
LAR @,!,@ 3800 2 TAR 1 0 0001
LAR @,! 3808 2 TAR 1 0 0001
LAR @,@ 3800 2 TAR 1 0 007F
LARK @,@ 7000 2 TAR 1 0 00FF
LARP @ 6880 2 T1 1 0 0001
LDP !,@ 6F00 2 T1 1 0 01
LDP ! 6F08 2 NOP 1
LDP @ 6F00 2 T1 1 0 007F
LDPK @ 6E00 2 T1 1 0 01
LST !,@ 7B00 2 T1 1 0 01
LST ! 7B08 2 NOP 1
LST @ 7B00 2 T1 1 0 007F
LT !,@ 6A00 2 T1 1 0 01
LT ! 6A08 2 NOP 1
LT @ 6A00 2 T1 1 0 007F
LTA !,@ 6C00 2 T1 1 0 01
LTA ! 6C08 2 NOP 1
LTA @ 6C00 2 T1 1 0 007F
LTD !,@ 6B00 2 T1 1 0 01
LTD ! 6B08 2 NOP 1
LTD @ 6B00 2 T1 1 0 007F
MAR !,@ 6800 2 T1 1 0 01
MAR ! 6808 2 NOP 1
MAR @ 6800 2 T1 1 0 007F
MPY !,@ 6D00 2 T1 1 0 01
MPY ! 6D08 2 NOP 1
MPY @ 6D00 2 T1 1 0 007F
MPYK @ 8000 2 T1 1 0 1FFF
NOP "" 7F80 2 NOP 1
OR !,@ 7A00 2 T1 1 0 01
OR ! 7A08 2 NOP 1
OR @ 7A00 2 T1 1 0 007F
OUT !,@,@ 4800 2 T1 1 8 0700
OUT !,@ 4808 2 T1 1 8 0700
OUT @,@ 4800 2 TDMA 1 8 0700
PAC "" 7F8E 2 NOP 1
POP "" 7F9D 2 NOP 1
PUSH "" 7F9C 2 NOP 1
RET "" 7F8D 2 NOP 1
ROVM "" 7F8A 2 NOP 1
/* shift count for SACH can only be 0,1, or 4. The mask allows */
/* 0,1,4, or 5. Let the user beware */
SACH !,@,@ 5800 2 T1 1 8 0500
SACH !,@ 5808 2 T1 1 8 0500
SACH ! 5808 2 NOP 1
SACH @,@ 5800 2 TDMA 1 8 0500
SACH @ 5800 2 T1 1 0 007F
/* The data book shows a shift field for SACL but states it must be 0.
/* The previous version of this table left the shift field out
/* for simplicity, but here I have put it back for compatibility.
/* The AND mask is set to zero in this case so a error message
/* will result from non-zero shifts.
SACL !,@,@ 5000 2 T1 1 8 0000
SACL !,@ 5008 2 T1 1 8 0000
SACL ! 5008 2 NOP 1
SACL @,@ 5000 2 TDMA 1 8 0000
SACL @ 5000 2 T1 1 0 007F
SAR @,!,@ 3000 2 TAR 1 0 0001
SAR @,! 3008 2 TAR 1 0 0001
SAR @,@ 3000 2 TAR 1 0 007F
SOVM "" 7F8B 2 NOP 1
SPAC "" 7F90 2 NOP 1
SST !,@ 7C00 2 T1 1 0 0001
SST ! 7C08 2 NOP 1
SST @ 7C00 2 T1 1 0 007F
SUB !,@,@ 1000 2 T1 1 8 0F00
SUB !,@ 1008 2 T1 1 8 0F00
SUB ! 1008 2 NOP 1
SUB @,@ 1000 2 TDMA 1 8 0F00
SUB @ 1000 2 T1 1 0 007F
SUBC !,@ 6400 2 T1 1 0 01
SUBC ! 6408 2 NOP 1
SUBC @ 6400 2 T1 1 0 007F
SUBH !,@ 6200 2 T1 1 0 01
SUBH ! 6208 2 NOP 1
SUBH @ 6200 2 T1 1 0 007F
SUBS !,@ 6300 2 T1 1 0 01
SUBS ! 6308 2 NOP 1
SUBS @ 6300 2 T1 1 0 007F
TBLR !,@ 6700 2 T1 1 0 01
TBLR ! 6708 2 NOP 1
TBLR @ 6700 2 T1 1 0 007F
TBLW !,@ 7D00 2 T1 1 0 01
TBLW ! 7D08 2 NOP 1
TBLW @ 7D00 2 T1 1 0 007F
XOR !,@ 7800 2 T1 1 0 01
XOR ! 7808 2 NOP 1
XOR @ 7800 2 T1 1 0 007F
ZAC "" 7F89 2 NOP 1
ZALH !,@ 6500 2 T1 1 0 01
ZALH ! 6508 2 NOP 1
ZALH @ 6500 2 T1 1 0 007F
ZALS !,@ 6600 2 T1 1 0 01
ZALS ! 6608 2 NOP 1
ZALS @ 6600 2 T1 1 0 007F

456
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"TASM TMS32025 Assembler."
/****************************************************************************
/* $Id: tasm3225.tab 1.2 1997/09/28 22:16:44 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the TMS32025 version of TASM.
/* Bob Stricklin
/*
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT MASK */
/*-------------------------------------------*/
/* Generate opcodes high byte first */
.MSFIRST
/* Don't use '*' as the wild card since it is used for indirect addressing */
/* In this table '@' is the wild card indicating where expression may appear*/
.ALTWILD
.WORDADDRS
.NOARGSHIFT
/* Addressing mode definitions.
/* Value gets OR'd in to the opcode if the
/* addressing mode is recognized
/* Note: no special classes are defined, so if this
/* table is used for TMS32020, invalid instructions
/* will not result in errors (no BR0+/- addressing mode (for example)
/* The ! character can match any of the patterns in the REGSET:
.REGSET *BR0+ F0 1
.REGSET *BR0- C0 1
.REGSET *0+ E0 1
.REGSET *0- D0 1
.REGSET *+ A0 1
.REGSET *- 90 1
.REGSET * 80 1
ABS "" CE1B 2 NOP 1
ADD !,@,@ 0088 2 T1 1 8 0F00
ADD !,@ 0080 2 T1 1 8 0F00
ADD ! 0080 2 NOP 1
ADD @,@ 0000 2 TDMA 1 8 0F00
ADD @ 0000 2 T1 1 0 007F
ADDC !,@ 4388 2 T1 1 0 0007
ADDC ! 4380 2 NOP 1
ADDC @ 4300 2 T1 1 0 007F
ADDH !,@ 4888 2 T1 1 0 0007
ADDH ! 4880 2 NOP 1
ADDH @ 4800 2 T1 1 0 007F
ADDK @ CC00 2 T1 1 0 00FF ;8 bit constant
ADDS !,@ 4988 2 T1 1 0 0007
ADDS ! 4980 2 NOP 1
ADDS @ 4900 2 T1 1 0 007F
ADDT !,@ 4A88 2 T1 1 0 0007
ADDT ! 4A80 2 NOP 1
ADDT @ 4A00 2 T1 1 0 007F
ADLK @,@ D002 4 TLK 1 8 0F00
ADLK @ D002 4 TLK 1
ADRK @ 7E00 2 T1 1 0 00FF ;8 bit constant
AND !,@ 4E88 2 T1 1 0 0007
AND ! 4E80 2 NOP 1
AND @ 4E00 2 T1 1 0 007F
ANDK @,@ D004 4 TLK 1 8 0F00
ANDK @ D004 4 TLK 1
APAC "" CE15 2 NOP 1
B @,!,@ FF88 4 TLK 1 0 07
B @,! FF80 4 SWAP 1
B @ FF80 4 SWAP 1
BACC "" CE25 2 NOP 1
BANZ @,!,@ FB88 4 TLK 1 0 07
BANZ @,! FB80 4 SWAP 1
BANZ @ FB90 4 SWAP 1 ; Default to the equivalent of
; BANZ loop,*- (as per spec) for
; TMS32010 compatibility.
BBNZ @,!,@ F988 4 TLK 1 0 07
BBNZ @,! F980 4 SWAP 1
BBNZ @ F980 4 SWAP 1
BBZ @,!,@ F888 4 TLK 1 0 07
BBZ @,! F880 4 SWAP 1
BBZ @ F880 4 SWAP 1
BC @,!,@ 5E88 4 TLK 1 0 07
BC @,! 5E80 4 SWAP 1
BC @ 5E80 4 SWAP 1
BGEZ @,!,@ F488 4 TLK 1 0 07
BGEZ @,! F480 4 SWAP 1
BGEZ @ F480 4 SWAP 1
BGZ @,!,@ F188 4 TLK 1 0 07
BGZ @,! F180 4 SWAP 1
BGZ @ F180 4 SWAP 1
BIOZ @,!,@ FA88 4 TLK 1 0 07
BIOZ @,! FA80 4 SWAP 1
BIOZ @ FA80 4 SWAP 1
BIT !,@,@ 9088 2 T1 1 8 0F00 ;8 bit shift
BIT !,@ 9080 2 T1 1 8 0F00
BIT @,@ 9000 2 TDMA 1 8 0F00
BITT !,@ 5788 2 T1 1 0 07
BITT ! 5780 2 T1 1
BITT @ 5700 2 T1 1 0 7F
BLEZ @,!,@ F288 4 TLK 1 0 07
BLEZ @,! F280 4 SWAP 1
BLEZ @ F280 4 SWAP 1
BLKD @,!,@ FD88 4 TLK 1 0 07
BLKD @,! FD80 4 TLK 1 0 07
BLKD @,@ FD00 4 TLK 1 0 FF
BLKP @,!,@ FC88 4 TLK 1 0 07
BLKP @,! FC80 4 TLK 1 0 07
BLKP @,@ FC00 4 TLK 1 0 FF
BLZ @,!,@ F388 4 TLK 1 0 07
BLZ @,! F380 4 SWAP 1
BLZ @ F380 4 SWAP 1
BNC @,!,@ 5F88 4 TLK 1 0 07
BNC @,! 5F80 4 SWAP 1
BNC @ 5F80 4 SWAP 1
BNV @,!,@ F788 4 TLK 1 0 07
BNV @,! F780 4 SWAP 1
BNV @ F780 4 SWAP 1
BNZ @,!,@ F588 4 TLK 1 0 07
BNZ @,! F580 4 SWAP 1
BNZ @ F580 4 SWAP 1
BV @,!,@ F088 4 TLK 1 0 07
BV @,! F080 4 SWAP 1
BV @ F080 4 SWAP 1
BZ @,!,@ F688 4 TLK 1 0 07
BZ @,! F680 4 SWAP 1
BZ @ F680 4 SWAP 1
CALA "" CE24 2 NOP 1
CALL @,!,@ FE88 4 TLK 1 0 07
CALL @,! FE80 4 SWAP 1
CALL @ FE80 4 SWAP 1
CMPL "" CE27 2 NOP 1
CMPR @ CE50 2 T1 1 0 03 ;2 BIT CONTANT
CNFD "" CE04 2 NOP 1
CNFP "" CE05 2 NOP 1
CONF "" CE3C 2 T1 4 0 03 ; c26 ONLY
DINT "" CE01 2 NOP 1
DMOV !,@ 5688 2 T1 1 0 07
DMOV ! 5680 2 NOP 1
DMOV @ 5600 2 T1 1 0 007F
EINT "" CE00 2 NOP 1
FORT @ CE0E 2 T1 1 0 01
IDLE "" CE1F 2 NOP 1
IN !,@,@ 8088 2 T1 1 8 0F00
IN !,@ 8080 2 T1 1 8 0F00
IN @,@ 8000 2 TDMA 1 8 0F00
LAC !,@,@ 2088 2 T1 1 8 0F00
LAC !,@ 2080 2 T1 1 8 0F00
LAC ! 2080 2 NOP 1
LAC @,@ 2000 2 TDMA 1 8 0F00
LAC @ 2000 2 T1 1 0 007F
LACK @ CA00 2 T1 1 0 00FF ;tested for -25
LACT !,@ 4288 2 T1 1 0 07
LACT ! 4280 2 NOP 1
LACT @ 4200 2 T1 1 0 007F
LALK @,@ D001 4 TLK 1 8 0F00
LALK @ D001 4 TLK 1
LAR @,!,@ 3088 2 TAR 1 0 07
LAR @,! 3080 2 TAR 1 0 07
LAR @,@ 3000 2 TAR 1 0 7F
LARK @,@ C000 2 TAR 1 0 00FF
LARP @ 5588 2 T1 1 0 0007
LDP !,@ 5288 2 T1 1 0 07
LDP ! 5280 2 NOP 1
LDP @ 5200 2 T1 1 0 007F
LDPK @ C800 2 T1 1 0 01FF ;9 bit constant
LPH !,@ 5388 2 T1 1 0 07
LPH ! 5380 2 NOP 1
LPH @ 5300 2 T1 1 0 7F
LRLK @,@ D000 4 T5 1 8 0700 ;<arp>, <const16>
LST !,@ 5088 2 T1 1 0 07
LST ! 5080 2 NOP 1
LST @ 5000 2 T1 1 0 7F
LST1 !,@ 5188 2 T1 1 0 07
LST1 ! 5180 2 NOP 1
LST1 @ 5100 2 T1 1 0 7F
LT !,@ 3C88 2 T1 1 0 07
LT ! 3C80 2 NOP 1
LT @ 3C00 2 T1 1 0 7F
LTA !,@ 3D88 2 T1 1 0 07
LTA ! 3D80 2 NOP 1
LTA @ 3D00 2 T1 1 0 7F
LTD !,@ 3F88 2 T1 1 0 07
LTD ! 3F80 2 NOP 1
LTD @ 3F00 2 T1 1 0 7F
LTP !,@ 3E88 2 T1 1 0 07
LTP ! 3E80 2 NOP 1
LTP @ 3E00 2 T1 1 0 7F
LTS !,@ 5B88 2 T1 1 0 07
LTS ! 5B80 2 NOP 1
LTS @ 5B00 2 T1 1 0 7F
MAC @,!,@ 5D88 4 TLK 1 0 07
MAC @,! 5D80 4 TLK 1 0 07
MAC @,@ 5D00 4 TLK 1 0 7F
MACD @,!,@ 5C88 4 TLK 1 0 07
MACD @,! 5C80 4 TLK 1 0 07
MACD @,@ 5C00 4 TLK 1 0 7F
MAR !,@ 5588 2 T1 1 0 07
MAR ! 5580 2 NOP 1
MAR @ 5500 2 T1 1 0 7F
MPY !,@ 3888 2 T1 1 0 07
MPY ! 3880 2 NOP 1
MPY @ 3800 2 T1 1 0 7F
MPYA !,@ 3A88 2 T1 1 0 07
MPYA ! 3A80 2 NOP 1
MPYA @ 3A00 2 T1 1 0 7F
MPYK @ A000 2 T1 1 0 1FFF ;13 BIT CONTSTANT
MPYS !,@ 3B88 2 T1 1 0 07
MPYS ! 3B80 2 NOP 1
MPYS @ 3B00 2 T1 1 0 7F
MPYU !,@ CF88 2 T1 1 0 07
MPYU ! CF80 2 NOP 1
MPYU @ CF00 2 T1 1 0 7F
NEG "" CE23 2 NOP 1
NOP "" 5500 2 NOP 1
NORM ! CE82 2 NOP 1 ; C25
NORM "" CEA2 2 NOP 1 ; C20
OR !,@ 4D88 2 T1 1 0 07
OR ! 4D80 2 NOP 1
OR @ 4D00 2 T1 1 0 7F
ORK @,@ D005 4 TLK 1 8 0F00
ORK @ D005 4 TLK 1
OUT !,@,@ E088 2 T1 1 8 0F00
OUT !,@ E080 2 T1 1 8 0F00
OUT @,@ E000 2 TDMA 1 8 0F00
PAC "" CE14 2 NOP 1
POP "" CE1D 2 NOP 1
POPD !,@ 7A88 2 T1 1 0 07
POPD ! 7A80 2 NOP 1
POPD @ 7A00 2 T1 1 0 7F
PSHD !,@ 5488 2 T1 1 0 07
PSHD ! 5480 2 NOP 1
PSHD @ 5400 2 T1 1 0 7F
PUSH "" CE1C 2 NOP 1
RC "" CE30 2 NOP 1
RET "" CE26 2 NOP 1
RFSM "" CE36 2 NOP 1
RHM "" CE38 2 NOP 1
ROL "" CE34 2 NOP 1
ROR "" CE35 2 NOP 1
ROVM "" CE02 2 NOP 1
RPT !,@ 4B88 2 T1 1 0 07
RPT ! 4B80 2 NOP 1
RPT @ 4B00 2 T1 1 0 7F
RPTK @ CB00 2 T1 1 0 00FF ;8 bit constant
RSXM "" CE06 2 NOP 1
RTC "" CE32 2 NOP 1
RTXM "" CE20 2 NOP 1
RXF "" CE0C 2 NOP 1
/* shift count for SACH can only be 0,1, or 4 FOR 32020
/* 0-7 FOR 320c25. For now, build the table specifically for the 320C25
SACH !,@,@ 6888 2 T1 1 8 0700
SACH !,@ 6880 2 T1 1 8 0700
SACH ! 6880 2 NOP 1
SACH @,@ 6800 2 TDMA 1 8 0700
SACH @ 6800 2 T1 1 0 007F
SACL !,@,@ 6088 2 T1 1 8 0700
SACL !,@ 6080 2 T1 1 8 0700
SACL ! 6080 2 NOP 1
SACL @,@ 6000 2 TDMA 1 8 0700
SACL @ 6000 2 T1 1 0 007F
SAR @,!,@ 7088 2 TAR 1 0 0007
SAR @,! 7080 2 TAR 1 0 0007
SAR @,@ 7000 2 TAR 1 0 007F
SBLK @,@ D003 4 TLK 1 8 0F00
SBLK @ D003 4 TLK 1
SBRK @ 7F00 2 T1 1 0 00FF
SC "" CE31 2 NOP 1
SFL "" CE18 2 NOP 1
SFR "" CE19 2 NOP 1
SFSM "" CE37 2 NOP 1
SHM "" CE39 2 NOP 1
SOVM "" CE03 2 NOP 1
SPAC "" CE16 2 NOP 1
SPH !,@ 7D88 2 T1 1 0 07
SPH ! 7D80 2 NOP 1
SPH @ 7D00 2 T1 1 0 7F
SPL !,@ 7C88 2 T1 1 0 07
SPL ! 7C80 2 NOP 1
SPL @ 7C00 2 T1 1 0 7F
SPM @ CE08 2 T1 1 0 03 ;2 bit constant
SQRA !,@ 3988 2 T1 1 0 07
SQRA ! 3980 2 NOP 1
SQRA @ 3900 2 T1 1 0 7F
SQRS !,@ 5A88 2 T1 1 0 07
SQRS ! 5A80 2 NOP 1
SQRS @ 5A00 2 T1 1 0 7F
SST !,@ 7888 2 T1 1 0 07
SST ! 7880 2 NOP 1
SST @ 7800 2 T1 1 0 7F
SST1 !,@ 7988 2 T1 1 0 07
SST1 ! 7980 2 NOP 1
SST1 @ 7900 2 T1 1 0 7F
SSXM "" CE07 2 NOP 1
STC "" CE33 2 NOP 1
STXM "" CE21 2 NOP 1
SUB !,@,@ 1088 2 T1 1 8 0F00
SUB !,@ 1080 2 T1 1 8 0F00
SUB ! 1080 2 NOP 1
SUB @,@ 1000 2 TDMA 1 8 0F00
SUB @ 1000 2 T1 1 0 007F
SUBB !,@ 4F88 2 T1 1 0 07
SUBB ! 4F80 2 NOP 1
SUBB @ 4F00 2 T1 1 0 7F
SUBC !,@ 4788 2 T1 1 0 07
SUBC ! 4780 2 NOP 1
SUBC @ 4700 2 T1 1 0 7F
SUBH !,@ 4488 2 T1 1 0 07
SUBH ! 4480 2 NOP 1
SUBH @ 4400 2 T1 1 0 7F
SUBK @ CD00 2 T1 1 0 00FF
SUBS !,@ 4588 2 T1 1 0 07
SUBS ! 4580 2 NOP 1
SUBS @ 4500 2 T1 1 0 7F
SUBT !,@ 4688 2 T1 1 0 07
SUBT ! 4680 2 NOP 1
SUBT @ 4600 2 T1 1 0 7F
SXF "" CE0D 2 NOP 1
TBLR !,@ 5888 2 T1 1 0 07
TBLR ! 5880 2 NOP 1
TBLR @ 5800 2 T1 1 0 7F
TBLW !,@ 5988 2 T1 1 0 07
TBLW ! 5980 2 NOP 1
TBLW @ 5900 2 T1 1 0 7F
TRAP "" CE1E 2 NOP 1
XOR !,@ 4C88 2 T1 1 0 07
XOR ! 4C80 2 NOP 1
XOR @ 4C00 2 T1 1 0 7F
XORK @,@ D006 4 TLK 1 8 0F00
XORK @ D006 4 TLK 1
ZAC "" CA00 2 NOP 1
ZALH !,@ 4088 2 T1 1 0 07
ZALH ! 4080 2 NOP 1
ZALH @ 4000 2 T1 1 0 7F
ZALR !,@ 7B88 2 T1 1 0 07
ZALR ! 7B80 2 NOP 1
ZALR @ 7B00 2 T1 1 0 7F
ZALS !,@ 4188 2 T1 1 0 07
ZALS ! 4180 2 NOP 1
ZALS @ 4100 2 T1 1 0 7F

281
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"TASM 8048 Assembler. "
/****************************************************************************
/* $Id: tasm48.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 8048 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, June 1987.
/* CLASS bits are assigned as follows:
/* bit 0 = 8X48, 8035, 8039, 8049 instructions
/* bit 1 = 8X41A
/* bit 2 = 8022
/* bit 3 = 8021
/* Note that some of the base instructions should be disabled for the
/* 8041, 8022, and 8021, but are not.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ADD A,R0 68 1 NOP 1
ADD A,R1 69 1 NOP 1
ADD A,R2 6A 1 NOP 1
ADD A,R3 6B 1 NOP 1
ADD A,R4 6C 1 NOP 1
ADD A,R5 6D 1 NOP 1
ADD A,R6 6E 1 NOP 1
ADD A,R7 6F 1 NOP 1
ADD A,@R0 60 1 NOP 1
ADD A,@R1 61 1 NOP 1
ADD A,#* 03 2 NOP 1
ADDC A,R0 78 1 NOP 1
ADDC A,R1 79 1 NOP 1
ADDC A,R2 7A 1 NOP 1
ADDC A,R3 7B 1 NOP 1
ADDC A,R4 7C 1 NOP 1
ADDC A,R5 7D 1 NOP 1
ADDC A,R6 7E 1 NOP 1
ADDC A,R7 7F 1 NOP 1
ADDC A,@R0 70 1 NOP 1
ADDC A,@R1 71 1 NOP 1
ADDC A,#* 13 2 NOP 1
ANL A,R0 58 1 NOP 1
ANL A,R1 59 1 NOP 1
ANL A,R2 5A 1 NOP 1
ANL A,R3 5B 1 NOP 1
ANL A,R4 5C 1 NOP 1
ANL A,R5 5D 1 NOP 1
ANL A,R6 5E 1 NOP 1
ANL A,R7 5F 1 NOP 1
ANL A,@R0 50 1 NOP 1
ANL A,@R1 51 1 NOP 1
ANL A,#* 53 2 NOP 1
ANL BUS,#* 98 2 NOP 1
ANL P1,#* 99 2 NOP 1
ANL P2,#* 9A 2 NOP 1
ANLD P4,A 9C 1 NOP 1
ANLD P5,A 9D 1 NOP 1
ANLD P6,A 9E 1 NOP 1
ANLD P7,A 9F 1 NOP 1
CALL * 14 2 JMP 1
CLR A 27 1 NOP 1
CLR C 97 1 NOP 1
CLR F0 85 1 NOP 1
CLR F1 A5 1 NOP 1
CPL A 37 1 NOP 1
CPL C A7 1 NOP 1
CPL F0 95 1 NOP 1
CPL F1 B5 1 NOP 1
DA A 57 1 NOP 1
DEC A 07 1 NOP 1
DEC R0 C8 1 NOP 1
DEC R1 C9 1 NOP 1
DEC R2 CA 1 NOP 1
DEC R3 CB 1 NOP 1
DEC R4 CC 1 NOP 1
DEC R5 CD 1 NOP 1
DEC R6 CE 1 NOP 1
DEC R7 CF 1 NOP 1
DIS I 15 1 NOP 1
DIS TCNTI 35 1 NOP 1
DJNZ R0,* E8 2 JTHISPAGE 1
DJNZ R1,* E9 2 JTHISPAGE 1
DJNZ R2,* EA 2 JTHISPAGE 1
DJNZ R3,* EB 2 JTHISPAGE 1
DJNZ R4,* EC 2 JTHISPAGE 1
DJNZ R5,* ED 2 JTHISPAGE 1
DJNZ R6,* EE 2 JTHISPAGE 1
DJNZ R7,* EF 2 JTHISPAGE 1
EN DMA E5 1 NOP 2 ;8041
EN FLAGS F5 1 NOP 2 ;8041
EN I 05 1 NOP 1
EN TCNTI 25 1 NOP 1
ENT0 CLK 75 1 NOP 1
IN A,DBB 22 1 NOP 2 ;8041
IN A,P0 08 1 NOP 8 ;8021
IN A,P1 09 1 NOP 1
IN A,P2 0A 1 NOP 1
INC A 17 1 NOP 1
INC R0 18 1 NOP 1
INC R1 19 1 NOP 1
INC R2 1A 1 NOP 1
INC R3 1B 1 NOP 1
INC R4 1C 1 NOP 1
INC R5 1D 1 NOP 1
INC R6 1E 1 NOP 1
INC R7 1F 1 NOP 1
INC @R0 10 1 NOP 1
INC @R1 11 1 NOP 1
INS A,BUS 08 1 NOP 1
JB0 * 12 2 JTHISPAGE 1
JB1 * 32 2 JTHISPAGE 1
JB2 * 52 2 JTHISPAGE 1
JB3 * 72 2 JTHISPAGE 1
JB4 * 92 2 JTHISPAGE 1
JB5 * B2 2 JTHISPAGE 1
JB6 * D2 2 JTHISPAGE 1
JB7 * F2 2 JTHISPAGE 1
JMP * 04 2 JMP 1
JC * F6 2 JTHISPAGE 1
JF0 * B6 2 JTHISPAGE 1
JF1 * 76 2 JTHISPAGE 1
JNC * E6 2 JTHISPAGE 1
JNI * 86 2 JTHISPAGE 1
JNIBF * D6 2 JTHISPAGE 2 ;8041
JNT0 * 26 2 JTHISPAGE 1
JNT1 * 46 2 JTHISPAGE 1
JNZ * 96 2 JTHISPAGE 1
JOBF * 86 2 JTHISPAGE 2 ;8041
JTF * 16 2 JTHISPAGE 1
JT0 * 36 2 JTHISPAGE 1
JT1 * 56 2 JTHISPAGE 1
JZ * C6 2 JTHISPAGE 1
JMPP @A B3 1 NOP 1
MOV A,PSW C7 1 NOP 1
MOV A,R0 F8 1 NOP 1
MOV A,R1 F9 1 NOP 1
MOV A,R2 FA 1 NOP 1
MOV A,R3 FB 1 NOP 1
MOV A,R4 FC 1 NOP 1
MOV A,R5 FD 1 NOP 1
MOV A,R6 FE 1 NOP 1
MOV A,R7 FF 1 NOP 1
MOV A,T 42 1 NOP 1
MOV A,@R0 F0 1 NOP 1
MOV A,@R1 F1 1 NOP 1
MOV A,#* 23 2 NOP 1
MOV PSW,A D7 1 NOP 1
MOV R0,A A8 1 NOP 1
MOV R1,A A9 1 NOP 1
MOV R2,A AA 1 NOP 1
MOV R3,A AB 1 NOP 1
MOV R4,A AC 1 NOP 1
MOV R5,A AD 1 NOP 1
MOV R6,A AE 1 NOP 1
MOV R7,A AF 1 NOP 1
MOV R0,#* B8 2 NOP 1
MOV R1,#* B9 2 NOP 1
MOV R2,#* BA 2 NOP 1
MOV R3,#* BB 2 NOP 1
MOV R4,#* BC 2 NOP 1
MOV R5,#* BD 2 NOP 1
MOV R6,#* BE 2 NOP 1
MOV R7,#* BF 2 NOP 1
MOV STS,A 90 1 NOP 2 ;8041
MOV T,A 62 1 NOP 1
MOV @R0,A A0 1 NOP 1
MOV @R1,A A1 1 NOP 1
MOV @R0,#* B0 2 NOP 1
MOV @R1,#* B1 2 NOP 1
MOVD A,P4 0C 1 NOP 1
MOVD A,P5 0D 1 NOP 1
MOVD A,P6 0E 1 NOP 1
MOVD A,P7 0F 1 NOP 1
MOVD P4,A 3C 1 NOP 1
MOVD P5,A 3D 1 NOP 1
MOVD P6,A 3E 1 NOP 1
MOVD P7,A 3F 1 NOP 1
MOVP A,@A A3 1 NOP 1
MOVP3 A,@A E3 1 NOP 1
MOVX A,@R0 80 1 NOP 1
MOVX A,@R1 81 1 NOP 1
MOVX @R0,A 90 1 NOP 1
MOVX @R1,A 91 1 NOP 1
NOP "" 00 1 NOP 1
ORL A,R0 48 1 NOP 1
ORL A,R1 49 1 NOP 1
ORL A,R2 4A 1 NOP 1
ORL A,R3 4B 1 NOP 1
ORL A,R4 4C 1 NOP 1
ORL A,R5 4D 1 NOP 1
ORL A,R6 4E 1 NOP 1
ORL A,R7 4F 1 NOP 1
ORL A,@R0 40 1 NOP 1
ORL A,@R1 41 1 NOP 1
ORL A,#* 43 2 NOP 1
ORL BUS,#* 88 2 NOP 1
ORL P1,#* 89 2 NOP 1
ORL P2,#* 8A 2 NOP 1
ORLD P4,A 8C 1 NOP 1
ORLD P5,A 8D 1 NOP 1
ORLD P6,A 8E 1 NOP 1
ORLD P7,A 8F 1 NOP 1
OUTL BUS,A 02 1 NOP 1
OUT DBB,A 02 1 NOP 2 ;8041
OUTL P0,A 90 1 NOP 8 ;8021
OUTL P1,A 39 1 NOP 1
OUTL P2,A 3A 1 NOP 1
RAD "" 80 1 NOP 4 ;8022
RET "" 83 1 NOP 1
RETI "" 93 1 NOP 4 ;8022
RETR "" 93 1 NOP 1
RL A E7 1 NOP 1
RLC A F7 1 NOP 1
RR A 77 1 NOP 1
RRC A 67 1 NOP 1
SEL AN0 85 1 NOP 4 ;8022
SEL AN1 95 1 NOP 4 ;8022
SEL MB0 E5 1 NOP 1
SEL MB1 F5 1 NOP 1
SEL RB0 C5 1 NOP 1
SEL RB1 D5 1 NOP 1
STOP TCNT 65 1 NOP 1
STRT CNT 45 1 NOP 1
STRT T 55 1 NOP 1
SWAP A 47 1 NOP 1
XCH A,R0 28 1 NOP 1
XCH A,R1 29 1 NOP 1
XCH A,R2 2A 1 NOP 1
XCH A,R3 2B 1 NOP 1
XCH A,R4 2C 1 NOP 1
XCH A,R5 2D 1 NOP 1
XCH A,R6 2E 1 NOP 1
XCH A,R7 2F 1 NOP 1
XCH A,@R0 20 1 NOP 1
XCH A,@R1 21 1 NOP 1
XCHD A,@R0 30 1 NOP 1
XCHD A,@R1 31 1 NOP 1
XRL A,R0 D8 1 NOP 1
XRL A,R1 D9 1 NOP 1
XRL A,R2 DA 1 NOP 1
XRL A,R3 DB 1 NOP 1
XRL A,R4 DC 1 NOP 1
XRL A,R5 DD 1 NOP 1
XRL A,R6 DE 1 NOP 1
XRL A,R7 DF 1 NOP 1
XRL A,@R0 D0 1 NOP 1
XRL A,@R1 D1 1 NOP 1
XRL A,#* D3 2 NOP 1

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"TASM 8051 Assembler. "
/****************************************************************************
/* $Id: tasm51.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 8051 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, June 1987.
/*
.NOARGSHIFT
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ACALL * 11 2 JMP 1 0 F800
ADD A,R0 28 1 NOP 1
ADD A,R1 29 1 NOP 1
ADD A,R2 2A 1 NOP 1
ADD A,R3 2B 1 NOP 1
ADD A,R4 2C 1 NOP 1
ADD A,R5 2D 1 NOP 1
ADD A,R6 2E 1 NOP 1
ADD A,R7 2F 1 NOP 1
ADD A,@R0 26 1 NOP 1
ADD A,@R1 27 1 NOP 1
ADD A,#* 24 2 NOP 1
ADD A,* 25 2 NOP 1
ADDC A,R0 38 1 NOP 1
ADDC A,R1 39 1 NOP 1
ADDC A,R2 3A 1 NOP 1
ADDC A,R3 3B 1 NOP 1
ADDC A,R4 3C 1 NOP 1
ADDC A,R5 3D 1 NOP 1
ADDC A,R6 3E 1 NOP 1
ADDC A,R7 3F 1 NOP 1
ADDC A,@R0 36 1 NOP 1
ADDC A,@R1 37 1 NOP 1
ADDC A,#* 34 2 NOP 1
ADDC A,* 35 2 NOP 1
AJMP * 01 2 JMP 1 0 F800
ANL A,R0 58 1 NOP 1
ANL A,R1 59 1 NOP 1
ANL A,R2 5A 1 NOP 1
ANL A,R3 5B 1 NOP 1
ANL A,R4 5C 1 NOP 1
ANL A,R5 5D 1 NOP 1
ANL A,R6 5E 1 NOP 1
ANL A,R7 5F 1 NOP 1
ANL A,@R0 56 1 NOP 1
ANL A,@R1 57 1 NOP 1
ANL A,#* 54 2 NOP 1
ANL A,* 55 2 NOP 1
ANL C,/* b0 2 NOP 1
ANL C,* 82 2 NOP 1
ANL *,A 52 2 NOP 1
ANL *,#* 53 3 COMBINE 1
CJNE A,#*,* b4 3 CR 1
CJNE A,*,* b5 3 CR 1
CJNE R0,#*,* b8 3 CR 1
CJNE R1,#*,* b9 3 CR 1
CJNE R2,#*,* ba 3 CR 1
CJNE R3,#*,* bb 3 CR 1
CJNE R4,#*,* bc 3 CR 1
CJNE R5,#*,* bd 3 CR 1
CJNE R6,#*,* be 3 CR 1
CJNE R7,#*,* bf 3 CR 1
CJNE @R0,#*,* b6 3 CR 1
CJNE @R1,#*,* b7 3 CR 1
CLR A e4 1 NOP 1
CLR C c3 1 NOP 1
CLR * c2 2 NOP 1
CPL A f4 1 NOP 1
CPL C b3 1 NOP 1
CPL * b2 2 NOP 1
DA A d4 1 NOP 1
DEC A 14 1 NOP 1
DEC R0 18 1 NOP 1
DEC R1 19 1 NOP 1
DEC R2 1A 1 NOP 1
DEC R3 1B 1 NOP 1
DEC R4 1C 1 NOP 1
DEC R5 1D 1 NOP 1
DEC R6 1E 1 NOP 1
DEC R7 1F 1 NOP 1
DEC @R0 16 1 NOP 1
DEC @R1 17 1 NOP 1
DEC * 15 2 NOP 1
DIV AB 84 1 NOP 1
DJNZ R0,* d8 2 R1 1
DJNZ R1,* d9 2 R1 1
DJNZ R2,* dA 2 R1 1
DJNZ R3,* dB 2 R1 1
DJNZ R4,* dC 2 R1 1
DJNZ R5,* dD 2 R1 1
DJNZ R6,* dE 2 R1 1
DJNZ R7,* dF 2 R1 1
DJNZ *,* d5 3 CR 1
INC A 04 1 NOP 1
INC R0 08 1 NOP 1
INC R1 09 1 NOP 1
INC R2 0A 1 NOP 1
INC R3 0B 1 NOP 1
INC R4 0C 1 NOP 1
INC R5 0D 1 NOP 1
INC R6 0E 1 NOP 1
INC R7 0F 1 NOP 1
INC @R0 06 1 NOP 1
INC @R1 07 1 NOP 1
INC DPTR a3 1 NOP 1
INC * 05 2 NOP 1
JB *,* 20 3 CR 1
JBC *,* 10 3 CR 1
JC * 40 2 R1 1
JMP @A+DPTR 73 1 NOP 1
JNB *,* 30 3 CR 1
JNC * 50 2 R1 1
JNZ * 70 2 R1 1
JZ * 60 2 R1 1
LCALL * 12 3 SWAP 1
LJMP * 02 3 SWAP 1
MOV A,R0 e8 1 NOP 1
MOV A,R1 e9 1 NOP 1
MOV A,R2 eA 1 NOP 1
MOV A,R3 eB 1 NOP 1
MOV A,R4 eC 1 NOP 1
MOV A,R5 eD 1 NOP 1
MOV A,R6 eE 1 NOP 1
MOV A,R7 eF 1 NOP 1
MOV A,@R0 e6 1 NOP 1
MOV A,@R1 e7 1 NOP 1
MOV A,#* 74 2 NOP 1
MOV A,* e5 2 NOP 1
MOV C,* a2 2 NOP 1
MOV DPTR,#* 90 3 SWAP 1
MOV R0,A f8 1 NOP 1
MOV R1,A f9 1 NOP 1
MOV R2,A fA 1 NOP 1
MOV R3,A fB 1 NOP 1
MOV R4,A fC 1 NOP 1
MOV R5,A fD 1 NOP 1
MOV R6,A fE 1 NOP 1
MOV R7,A fF 1 NOP 1
MOV R0,#* 78 2 NOP 1
MOV R1,#* 79 2 NOP 1
MOV R2,#* 7A 2 NOP 1
MOV R3,#* 7B 2 NOP 1
MOV R4,#* 7C 2 NOP 1
MOV R5,#* 7D 2 NOP 1
MOV R6,#* 7E 2 NOP 1
MOV R7,#* 7F 2 NOP 1
MOV R0,* a8 2 NOP 1
MOV R1,* a9 2 NOP 1
MOV R2,* aA 2 NOP 1
MOV R3,* aB 2 NOP 1
MOV R4,* aC 2 NOP 1
MOV R5,* aD 2 NOP 1
MOV R6,* aE 2 NOP 1
MOV R7,* aF 2 NOP 1
MOV @R0,A f6 1 NOP 1
MOV @R1,A f7 1 NOP 1
MOV @R0,#* 76 2 NOP 1
MOV @R1,#* 77 2 NOP 1
MOV @R0,* a6 2 NOP 1
MOV @R1,* a7 2 NOP 1
MOV *,A f5 2 NOP 1
MOV *,C 92 2 NOP 1
MOV *,R0 88 2 NOP 1
MOV *,R1 89 2 NOP 1
MOV *,R2 8A 2 NOP 1
MOV *,R3 8B 2 NOP 1
MOV *,R4 8C 2 NOP 1
MOV *,R5 8D 2 NOP 1
MOV *,R6 8E 2 NOP 1
MOV *,R7 8F 2 NOP 1
MOV *,@R0 86 2 NOP 1
MOV *,@R1 87 2 NOP 1
MOV *,#* 75 3 COMBINE 1
MOV *,* 85 3 CSWAP 1
MOVC A,@A+DPTR 93 1 NOP 1
MOVC A,@A+PC 83 1 NOP 1
MOVX A,@R0 e2 1 NOP 1
MOVX A,@R1 e3 1 NOP 1
MOVX A,@DPTR e0 1 NOP 1
MOVX @R0,A f2 1 NOP 1
MOVX @R1,A f3 1 NOP 1
MOVX @DPTR,A f0 1 NOP 1
MUL AB a4 1 NOP 1
NOP "" 00 1 NOP 1
ORL A,R0 48 1 NOP 1
ORL A,R1 49 1 NOP 1
ORL A,R2 4A 1 NOP 1
ORL A,R3 4B 1 NOP 1
ORL A,R4 4C 1 NOP 1
ORL A,R5 4D 1 NOP 1
ORL A,R6 4E 1 NOP 1
ORL A,R7 4F 1 NOP 1
ORL A,@R0 46 1 NOP 1
ORL A,@R1 47 1 NOP 1
ORL A,#* 44 2 NOP 1
ORL A,* 45 2 NOP 1
ORL C,/* a0 2 NOP 1
ORL C,* 72 2 NOP 1
ORL *,A 42 2 NOP 1
ORL *,#* 43 3 COMBINE 1
POP * d0 2 NOP 1
PUSH * c0 2 NOP 1
RET "" 22 1 NOP 1
RETI "" 32 1 NOP 1
RL A 23 1 NOP 1
RLC A 33 1 NOP 1
RR A 03 1 NOP 1
RRC A 13 1 NOP 1
SETB C d3 1 NOP 1
SETB * d2 2 NOP 1
SJMP * 80 2 R1 1
SUBB A,R0 98 1 NOP 1
SUBB A,R1 99 1 NOP 1
SUBB A,R2 9A 1 NOP 1
SUBB A,R3 9B 1 NOP 1
SUBB A,R4 9C 1 NOP 1
SUBB A,R5 9D 1 NOP 1
SUBB A,R6 9E 1 NOP 1
SUBB A,R7 9F 1 NOP 1
SUBB A,@R0 96 1 NOP 1
SUBB A,@R1 97 1 NOP 1
SUBB A,#* 94 2 NOP 1
SUBB A,* 95 2 NOP 1
SWAP A c4 1 NOP 1
XCH A,R0 c8 1 NOP 1
XCH A,R1 c9 1 NOP 1
XCH A,R2 cA 1 NOP 1
XCH A,R3 cB 1 NOP 1
XCH A,R4 cC 1 NOP 1
XCH A,R5 cD 1 NOP 1
XCH A,R6 cE 1 NOP 1
XCH A,R7 cF 1 NOP 1
XCH A,@R0 c6 1 NOP 1
XCH A,@R1 c7 1 NOP 1
XCH A,* c5 2 NOP 1
XCHD A,@R0 d6 1 NOP 1
XCHD A,@R1 d7 1 NOP 1
XRL A,R0 68 1 NOP 1
XRL A,R1 69 1 NOP 1
XRL A,R2 6A 1 NOP 1
XRL A,R3 6B 1 NOP 1
XRL A,R4 6C 1 NOP 1
XRL A,R5 6D 1 NOP 1
XRL A,R6 6E 1 NOP 1
XRL A,R7 6F 1 NOP 1
XRL A,@R0 66 1 NOP 1
XRL A,@R1 67 1 NOP 1
XRL A,#* 64 2 NOP 1
XRL A,* 65 2 NOP 1
XRL *,A 62 2 NOP 1
XRL *,#* 63 3 COMBINE 1

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"TASM 6502 Assembler. "
/****************************************************************************
/* $Id: tasm65.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 6502 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, June 1987.
/* Note that there are two classes of extended instructions beyond
/* the standard set. The classes are assigned bits as follows:
/* bit 0 = standard set
/* bit 1 = extended instructions for R65C02
/* bit 2 = extended instructions for R65C00/21
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ADC #* 69 2 NOP 1
ADC (*,X) 61 2 NOP 1
ADC (*),Y 71 2 NOP 1
ADC (*) 72 2 NOP 2
ADC *,X 7D 3 ZP 1
ADC *,Y 79 3 NOP 1
ADC * 6D 3 ZP 1
AND #* 29 2 NOP 1
AND (*,X) 21 2 NOP 1
AND (*),Y 31 2 NOP 1
AND (*) 32 2 NOP 2
AND *,X 3D 3 ZP 1
AND *,Y 39 3 NOP 1
AND * 2D 3 ZP 1
ASL A 0A 1 NOP 1
ASL *,X 1E 3 ZP 1
ASL * 0E 3 ZP 1
BBR0 *,* 0f 3 CR 6
BBR1 *,* 1f 3 CR 6
BBR2 *,* 2f 3 CR 6
BBR3 *,* 3f 3 CR 6
BBR4 *,* 4f 3 CR 6
BBR5 *,* 5f 3 CR 6
BBR6 *,* 6f 3 CR 6
BBR7 *,* 7f 3 CR 6
BBS0 *,* 8f 3 CR 6
BBS1 *,* 9f 3 CR 6
BBS2 *,* af 3 CR 6
BBS3 *,* bf 3 CR 6
BBS4 *,* cf 3 CR 6
BBS5 *,* df 3 CR 6
BBS6 *,* ef 3 CR 6
BBS7 *,* ff 3 CR 6
BCC * 90 2 R1 1
BCS * B0 2 R1 1
BEQ * F0 2 R1 1
BMI * 30 2 R1 1
BNE * D0 2 R1 1
BPL * 10 2 R1 1
BRA * 80 2 R1 6
BVC * 50 2 R1 1
BVS * 70 2 R1 1
BIT #* 89 2 NOP 2
BIT *,X 3C 3 ZP 2
BIT * 2C 3 ZP 1
BRK "" 00 1 NOP 1
CLC "" 18 1 NOP 1
CLD "" D8 1 NOP 1
CLI "" 58 1 NOP 1
CLV "" B8 1 NOP 1
CMP #* C9 2 NOP 1
CMP (*,X) C1 2 NOP 1
CMP (*),Y D1 2 NOP 1
CMP (*) D2 2 NOP 2
CMP *,X DD 3 ZP 1
CMP *,Y D9 3 NOP 1
CMP * CD 3 ZP 1
CPX #* E0 2 NOP 1
CPX * EC 3 ZP 1
CPY #* C0 2 NOP 1
CPY * CC 3 ZP 1
DEC A 3A 1 NOP 2
DEC *,X DE 3 ZP 1
DEC * CE 3 ZP 1
DEX "" CA 1 NOP 1
DEY "" 88 1 NOP 1
EOR #* 49 2 NOP 1
EOR (*,X) 41 2 NOP 1
EOR (*),Y 51 2 NOP 1
EOR (*) 52 2 NOP 2
EOR *,X 5D 3 ZP 1
EOR *,Y 59 3 NOP 1
EOR * 4D 3 ZP 1
INC A 1A 1 NOP 2
INC *,X FE 3 ZP 1
INC * EE 3 ZP 1
INX "" E8 1 NOP 1
INY "" C8 1 NOP 1
JMP (*,X) 7C 3 NOP 2
JMP (*) 6C 3 NOP 1
JMP * 4C 3 NOP 1
JSR * 20 3 NOP 1
LDA #* A9 2 NOP 1
LDA (*,X) A1 2 NOP 1
LDA (*),Y B1 2 NOP 1
LDA (*) B2 2 NOP 2
LDA *,X BD 3 ZP 1
LDA *,Y B9 3 NOP 1
LDA * AD 3 ZP 1
LDX #* A2 2 NOP 1
LDX *,Y BE 3 ZP 1
LDX * AE 3 ZP 1
LDY #* A0 2 NOP 1
LDY *,X BC 3 ZP 1
LDY * AC 3 ZP 1
LSR A 4A 1 NOP 1
LSR *,X 5E 3 ZP 1
LSR * 4E 3 ZP 1
MUL "" 02 1 NOP 4 /* R65C00/21 only*/
NOP "" EA 1 NOP 1
ORA #* 09 2 NOP 1
ORA (*,X) 01 2 NOP 1
ORA (*),Y 11 2 NOP 1
ORA (*) 12 2 NOP 2
ORA *,X 1D 3 ZP 1
ORA *,Y 19 3 NOP 1
ORA * 0D 3 ZP 1
PHA "" 48 1 NOP 1
PHP "" 08 1 NOP 1
PHX "" DA 1 NOP 6
PHY "" 5A 1 NOP 6
PLA "" 68 1 NOP 1
PLP "" 28 1 NOP 1
PLX "" FA 1 NOP 6
PLY "" 7A 1 NOP 6
RMB0 * 07 2 NOP 6
RMB1 * 17 2 NOP 6
RMB2 * 27 2 NOP 6
RMB3 * 37 2 NOP 6
RMB4 * 47 2 NOP 6
RMB5 * 57 2 NOP 6
RMB6 * 67 2 NOP 6
RMB7 * 77 2 NOP 6
ROL A 2A 1 NOP 1
ROL *,X 3E 3 ZP 1
ROL * 2E 3 ZP 1
ROR A 6A 1 NOP 1
ROR *,X 7E 3 ZP 1
ROR * 6E 3 ZP 1
RTI "" 40 1 NOP 1
RTS "" 60 1 NOP 1
SBC #* E9 2 NOP 1
SBC (*,X) E1 2 NOP 1
SBC (*),Y F1 2 NOP 1
SBC (*) F2 2 NOP 2
SBC *,X FD 3 ZP 1
SBC *,Y F9 3 NOP 1
SBC * ED 3 ZP 1
SEC "" 38 1 NOP 1
SED "" F8 1 NOP 1
SEI "" 78 1 NOP 1
SMB0 * 87 2 NOP 6
SMB1 * 97 2 NOP 6
SMB2 * a7 2 NOP 6
SMB3 * b7 2 NOP 6
SMB4 * c7 2 NOP 6
SMB5 * d7 2 NOP 6
SMB6 * e7 2 NOP 6
SMB7 * f7 2 NOP 6
STA (*,X) 81 2 NOP 1
STA (*),Y 91 2 NOP 1
STA (*) 92 2 NOP 2
STA *,X 9D 3 ZP 1
STA *,Y 99 3 NOP 1
STA * 8D 3 ZP 1
STX *,Y 96 2 ZP 1
STX * 8E 3 ZP 1
STY *,X 94 2 NOP 1
STY * 8C 3 ZP 1
STZ *,X 9e 3 ZP 2
STZ * 9c 3 ZP 2
TAX "" AA 1 NOP 1
TAY "" A8 1 NOP 1
TRB * 1c 3 ZP 2
TSB * 0c 3 ZP 2
TSX "" BA 1 NOP 1
TXA "" 8A 1 NOP 1
TXS "" 9A 1 NOP 1
TYA "" 98 1 NOP 1

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"TASM 6800-6811 Assembler"
/****************************************************************************
/* $Id: tasm68.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* Originally submitted by Richard P. White, June 4,1989 */
/* Corrected and enhanced by T.N. Anderson, STI */
/* Enhanced for the 68HC11 by George Blat, Nov 3, 1990
/* Class bits defined as follows:
/*
/* bit 0 for 6800
/* bit 1 for 6801/6803
/* bit 2 for 68HC11
/*
/* Note that TASM deviates from motorola syntax for BCLR, BSET,
/* BRCLR, and BRSET instructions. TASM requires commas between
/* each arg. Motorola requires white space before the make and
/* label args.
.MSFIRST
ABA "" 1B 1 NOP 1
ABX "" 3A 1 NOP 2
ABY "" 183A 2 NOP 4
ADCA #* 89 2 NOP 1
ADCA *,Y 18A9 3 NOP 4
ADCA *,X A9 2 NOP 1
ADCA * B9 3 MZERO 1
ADCB #* C9 2 NOP 1
ADCB *,Y 18E9 3 NOP 4
ADCB *,X E9 2 NOP 1
ADCB * F9 3 MZERO 1
ADDA #* 8B 2 NOP 1
ADDA *,Y 18AB 3 NOP 4
ADDA *,X AB 2 NOP 1
ADDA * BB 3 MZERO 1
ADDB #* CB 2 NOP 1
ADDB *,Y 18EB 3 NOP 4
ADDB *,X EB 2 NOP 1
ADDB * FB 3 MZERO 1
ADDD #* C3 3 SWAP 2
ADDD *,Y 18E3 3 NOP 4
ADDD *,X E3 2 NOP 2
ADDD * F3 3 MZERO 2
ANDA #* 84 2 NOP 1
ANDA *,Y 18A4 3 NOP 4
ANDA *,X A4 2 NOP 1
ANDA * B4 3 MZERO 1
ANDB #* C4 2 NOP 1
ANDB *,Y 18E4 3 NOP 4
ANDB *,X E4 2 NOP 1
ANDB * F4 3 MZERO 1
ASL *,Y 1868 3 NOP 4
ASL *,X 68 2 NOP 1
ASL * 78 3 SWAP 1
ASLA "" 48 1 NOP 1
ASLB "" 58 1 NOP 1
ASLD "" 05 1 NOP 2
ASR *,Y 1867 3 NOP 4
ASR *,X 67 2 NOP 1
ASR * 77 3 SWAP 1
ASRA "" 47 1 NOP 1
ASRB "" 57 1 NOP 1
BCC * 24 2 R1 1
BCLR *,X,* 1D 3 COMB 4
BCLR *,Y,* 181D 4 COMB 4
BCLR *,#* 15 3 COMB 4 /* allow # since mask is immediate data
BCLR *,* 15 3 COMB 4
BCS * 25 2 R1 1
BEQ * 27 2 R1 1
BGE * 2C 2 R1 1
BGT * 2E 2 R1 1
BHI * 22 2 R1 1
BHS * 24 2 R1 1
BITA #* 85 2 NOP 1
BITA *,Y 18A5 3 NOP 4
BITA *,X A5 2 NOP 1
BITA * B5 3 MZERO 1
BITB #* C5 2 NOP 1
BITB *,Y 18E5 3 NOP 4
BITB *,X E5 2 NOP 1
BITB * F5 3 MZERO 1
BLE * 2F 2 R1 1
BLO * 25 2 R1 1
BLS * 23 2 R1 1
BLT * 2D 2 R1 1
BMI * 2B 2 R1 1
BNE * 26 2 R1 1
BPL * 2A 2 R1 1
BRA * 20 2 R1 1
BRCLR *,X,*,* 1F 4 3REL 4
BRCLR *,Y,*,* 181F 5 3REL 4
BRCLR *,*,* 13 4 3REL 4
BRN * 21 2 R1 2 /* NOT SURE ABOUT 6803 */
BRSET *,X,*,* 1E 4 3REL 4
BRSET *,Y,*,* 181E 5 3REL 4
BRSET *,*,* 12 4 3REL 4
BSET *,X,* 1C 3 COMB 4
BSET *,Y,* 181C 4 COMB 4
BSET *,#* 14 3 COMB 4 /* allow #
BSET *,* 14 3 COMB 4
BSR * 8D 2 R1 1
BVC * 28 2 R1 1
BVS * 29 2 R1 1
CBA "" 11 1 NOP 1
CLC "" 0C 1 NOP 1
CLI "" 0E 1 NOP 1
CLR *,Y 186F 3 NOP 4
CLR *,X 6F 2 NOP 1
CLR * 7F 3 SWAP 1
CLRA "" 4F 1 NOP 1
CLRB "" 5F 1 NOP 1
CLV "" 0A 1 NOP 1
CMPA #* 81 2 NOP 1
CMPA *,X A1 2 NOP 1
CMPA *,Y 18A1 3 NOP 4
CMPA * B1 3 MZERO 1
CMPB #* C1 2 NOP 1
CMPB *,Y 18E1 3 NOP 4
CMPB *,X E1 2 NOP 1
CMPB * F1 3 MZERO 1
CMPD #* 1A83 4 SWAP 4 /* alias for CPD */
CMPD *,X 1AA3 3 NOP 4
CMPD *,Y CDA3 3 NOP 4
CMPD * 1AB3 4 MZERO 4
COM *,X 63 2 NOP 1
COM *,Y 1863 3 NOP 4
COM * 73 3 SWAP 1
COMA "" 43 1 NOP 1
COMB "" 53 1 NOP 1
CPD #* 1A83 4 SWAP 4
CPD *,X 1AA3 3 NOP 4
CPD *,Y CDA3 3 NOP 4
CPD * 1AB3 4 MZERO 4
CPX #* 8C 3 SWAP 1
CPX *,X AC 2 NOP 1
CPX *,Y CDAC 3 NOP 4
CPX * BC 3 MZERO 1
CPY #* 188C 4 SWAP 4
CPY *,Y 18AC 3 NOP 4
CPY *,X 1AAC 3 NOP 4
CPY * 18BC 4 MZERO 4
DAA "" 19 1 NOP 1
DEC *,Y 186A 3 NOP 4
DEC *,X 6A 2 NOP 1
DEC * 7A 3 SWAP 1
DECA "" 4A 1 NOP 1
DECB "" 5A 1 NOP 1
DES "" 34 1 NOP 1
DEX "" 09 1 NOP 1
DEY "" 1809 2 NOP 4
EORA #* 88 2 NOP 1
EORA *,Y 18A8 3 NOP 4
EORA *,X A8 2 NOP 1
EORA * B8 3 MZERO 1
EORB #* C8 2 NOP 1
EORB *,Y 18E8 3 NOP 4
EORB *,X E8 2 NOP 1
EORB * F8 3 MZERO 1
FDIV "" 03 1 NOP 4
IDIV "" 02 1 NOP 4
INC *,Y 186C 3 NOP 4
INC *,X 6C 2 NOP 1
INC * 7C 3 SWAP 1
INCA "" 4C 1 NOP 1
INCB "" 5C 1 NOP 1
INS "" 31 1 NOP 1
INX "" 08 1 NOP 1
INY "" 1808 2 NOP 4
JMP *,Y 186E 3 NOP 4
JMP *,X 6E 2 NOP 1
JMP * 7E 3 SWAP 1
JSR *,Y 18AD 3 NOP 4
JSR *,X AD 2 NOP 1
JSR * BD 3 MZERO 1
LDAA #* 86 2 NOP 1
LDAA *,Y 18A6 3 NOP 4
LDAA *,X A6 2 NOP 1
LDAA >* B6 3 SWAP 1 /* Force EXT mode */
LDAA * B6 3 MZERO 1
LDAB #* C6 2 NOP 1
LDAB *,Y 18E6 3 NOP 4
LDAB *,X E6 2 NOP 1
LDAB >* F6 3 SWAP 1 /* Force EXT mode */
LDAB * F6 3 MZERO 1
LDD #* CC 3 SWAP 2
LDD *,Y 18EC 3 NOP 4
LDD *,X EC 2 NOP 2
LDD >* FC 3 SWAP 2 /* Force EXT mode */
LDD * FC 3 MZERO 2
LDS #* 8E 3 SWAP 1
LDS *,Y 18AE 3 NOP 4
LDS *,X AE 2 NOP 1
LDS >* BE 3 SWAP 1 /* Force EXT mode */
LDS * BE 3 MZERO 1
LDX #* CE 3 SWAP 1
LDX *,X EE 2 NOP 1
LDX *,Y CDEE 3 NOP 4
LDX >* FE 3 SWAP 1 /* Force EXT mode */
LDX * FE 3 MZERO 1
LDY #* 18CE 4 SWAP 4
LDY *,Y 18EE 3 NOP 4
LDY *,X 1AEE 3 NOP 4
LDY >* 18FE 4 SWAP 4 /* Force EXT mode */
LDY * 18FE 4 MZERO 4
LSL *,Y 1868 3 NOP 4
LSL *,X 68 2 NOP 1 /*SAME AS ASL */
LSL * 78 3 SWAP 1
LSLA "" 48 1 NOP 1
LSLB "" 58 1 NOP 1
LSLD "" 05 1 NOP 2
LSR *,Y 1864 3 NOP 4
LSR *,X 64 2 NOP 1
LSR * 74 3 SWAP 1
LSRA "" 44 1 NOP 1
LSRB "" 54 1 NOP 1
LSRD "" 04 1 NOP 2
MUL "" 3D 1 NOP 2
NEG *,Y 1860 3 NOP 4
NEG *,X 60 2 NOP 1
NEG * 70 3 SWAP 1
NEGA "" 40 1 NOP 1
NEGB "" 50 1 NOP 1
NOP "" 01 1 NOP 1
ORAA #* 8A 2 NOP 1
ORAA *,Y 18AA 3 NOP 4
ORAA *,X AA 2 NOP 1
ORAA * BA 3 MZERO 1
ORAB #* CA 2 NOP 1
ORAB *,Y 18EA 3 NOP 4
ORAB *,X EA 2 NOP 1
ORAB * FA 3 MZERO 1
PSHA "" 36 1 NOP 1
PSHB "" 37 1 NOP 1
PSHX "" 3C 1 NOP 2
PSHY "" 183C 2 NOP 4
PULA "" 32 1 NOP 1
PULB "" 33 1 NOP 1
PULX "" 38 1 NOP 2
PULY "" 1838 2 NOP 4
ROL *,Y 1869 3 NOP 4
ROL *,X 69 2 NOP 1
ROL * 79 3 SWAP 1
ROLA "" 49 1 NOP 1
ROLB "" 59 1 NOP 1
ROR *,Y 1866 3 NOP 4
ROR *,X 66 2 NOP 1
ROR * 76 3 SWAP 1
RORA "" 46 1 NOP 1
RORB "" 56 1 NOP 1
RTI "" 3B 1 NOP 1
RTS "" 39 1 NOP 1
SBA "" 10 1 NOP 1
SBCA #* 82 2 NOP 1
SBCA *,Y 18A2 3 NOP 4
SBCA *,X A2 2 NOP 1
SBCA * B2 3 MZERO 1
SBCB #* C2 2 NOP 1
SBCB *,Y 18E2 3 NOP 4
SBCB *,X E2 2 NOP 1
SBCB * F2 3 MZERO 1
SEC "" 0D 1 NOP 1
SEI "" 0F 1 NOP 1
SEV "" 0B 1 NOP 1
STAA *,Y 18A7 3 NOP 4
STAA *,X A7 2 NOP 1
STAA >* B7 3 SWAP 1 /* Force EXT mode */
STAA * B7 3 MZERO 1
STAB *,Y 18E7 3 NOP 4
STAB *,X E7 2 NOP 1
STAB >* F7 3 SWAP 1 /* Force EXT mode */
STAB * F7 3 MZERO 1
STD *,Y 18ED 3 NOP 4
STD *,X ED 2 NOP 2
STD >* FD 3 SWAP 2 /* Force EXT mode */
STD * FD 3 MZERO 2
STOP "" CF 1 NOP 1
STS *,X AF 2 NOP 1
STS *,Y 18AF 3 NOP 4
STS >* BF 3 SWAP 1 /* Force EXT mode */
STS * BF 3 MZERO 1
STX *,X EF 2 NOP 1
STX *,Y CDEF 3 NOP 4
STX >* FF 3 SWAP 1 /* Force EXT mode */
STX * FF 3 MZERO 1
STY *,Y 18EF 3 NOP 4
STY *,X 1AEF 3 NOP 4
STY >* 18FF 4 SWAP 4 /* Force EXT mode */
STY * 18FF 4 MZERO 4
SUBA #* 80 2 NOP 1
SUBA *,Y 18A0 3 NOP 4
SUBA *,X A0 2 NOP 1
SUBA * B0 3 MZERO 1
SUBB #* C0 2 NOP 1
SUBB *,Y 18E0 3 NOP 4
SUBB *,X E0 2 NOP 1
SUBB * F0 3 MZERO 1
SUBD #* 83 3 SWAP 2
SUBD *,Y 18A3 3 NOP 4
SUBD *,X A3 2 NOP 2
SUBD * B3 3 MZERO 2
SWI "" 3F 1 NOP 1
TAB "" 16 1 NOP 1
TAP "" 06 1 NOP 1
TBA "" 17 1 NOP 1
TEST "" 00 1 NOP 1
TPA "" 07 1 NOP 1
TST *,Y 186D 3 NOP 4
TST *,X 6D 2 NOP 1
TST * 7D 3 SWAP 1
TSTA "" 4D 1 NOP 1
TSTB "" 5D 1 NOP 1
TSX "" 30 1 NOP 1
TSY "" 1830 2 NOP 4
TXS "" 35 1 NOP 1
TYS "" 1835 2 NOP 4
WAI "" 3E 1 NOP 1
XGDX "" 8F 1 NOP 4
XGDY "" 188F 2 NOP 4
/* That's all folks */

290
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"TASM 7000 Assembler. "
/****************************************************************************
/* $Id: tasm70.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* Table for TMS7000 micros
/* Note that the table does not require the 'Rnn' nomenclature
/* for reference of locations in the register file. Any expression
/* will do, the value of which indicates the register. This is more
/* flexible then making an entry like "ADC R*,A".
/*
/* TASM has trouble with the MOVD +(B),+ instruction so
/* we convert it to MOVD +[B],+
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
.ALTWILD+
ADC B,A 69 1 NOP 1
ADC %+,A 29 2 NOP 1
ADC %+,B 59 2 NOP 1
ADC %+,+ 79 3 COMB 1
ADC +,A 19 2 NOP 1
ADC +,B 39 2 NOP 1
ADC +,+ 49 3 COMB 1
ADD B,A 68 1 NOP 1
ADD %+,A 28 2 NOP 1
ADD %+,B 58 2 NOP 1
ADD %+,+ 78 3 COMB 1
ADD +,A 18 2 NOP 1
ADD +,B 38 2 NOP 1
ADD +,+ 48 3 COMB 1
AND B,A 63 1 NOP 1
AND %+,A 23 2 NOP 1
AND %+,B 53 2 NOP 1
AND %+,+ 73 3 COMB 1
AND +,A 13 2 NOP 1
AND +,B 33 2 NOP 1
AND +,+ 43 3 COMB 1
ANDP A,+ 83 2 NOP 1
ANDP B,+ 93 2 NOP 1
ANDP %+,+ A3 3 COMB 1
BTJO B,A,+ 66 2 R1 1
BTJO %+,A,+ 26 3 CREL 1
BTJO %+,B,+ 56 3 CREL 1
BTJO %+,+,+ 76 4 3REL 1
BTJO +,A,+ 16 3 CREL 1
BTJO +,B,+ 36 3 CREL 1
BTJO +,+,+ 46 4 3REL 1
BTJOP A,+,+ 86 3 CREL 1
BTJOP B,+,+ 96 3 CREL 1
BTJOP %+,+,+ A6 4 3REL 1
BTJZ B,A,+ 67 2 R1 1
BTJZ %+,A,+ 27 3 CREL 1
BTJZ %+,B,+ 57 3 CREL 1
BTJZ %+,+,+ 77 4 3REL 1
BTJZ +,A,+ 17 3 CREL 1
BTJZ +,B,+ 37 3 CREL 1
BTJZ +,+,+ 47 4 3REL 1
BTJZP A,+,+ 87 3 CREL 1
BTJZP B,+,+ 97 3 CREL 1
BTJZP %+,+,+ A7 4 3REL 1
BR @+(B) AC 3 SWAP 1
BR @+[B] AC 3 SWAP 1
BR @+ 8C 3 SWAP 1
BR *+ 9C 2 NOP 1
CALL @+(B) AE 3 SWAP 1
CALL @+[B] AE 3 SWAP 1
CALL @+ 8E 3 SWAP 1
CALL *+ 9E 2 NOP 1
CLR A B5 1 NOP 1
CLR B C5 1 NOP 1
CLR + D5 2 NOP 1
CLRC "" B0 1 NOP 1
CMP B,A 6D 1 NOP 1
CMP %+,A 2D 2 NOP 1
CMP %+,B 5D 2 NOP 1
CMP %+,+ 7D 3 COMB 1
CMP +,A 1D 2 NOP 1
CMP +,B 3D 2 NOP 1
CMP +,+ 4D 3 COMB 1
CMPA @+(B) AD 3 SWAP 1
CMPA @+[B] AD 3 SWAP 1
CMPA @+ 8D 3 SWAP 1
CMPA *+ 9D 2 NOP 1
DAC B,A 6E 1 NOP 1
DAC %+,A 2E 2 NOP 1
DAC %+,B 5E 2 NOP 1
DAC %+,+ 7E 3 COMB 1
DAC +,A 1E 2 NOP 1
DAC +,B 3E 2 NOP 1
DAC +,+ 4E 3 COMB 1
DEC A B2 1 NOP 1
DEC B C2 1 NOP 1
DEC + D2 2 NOP 1
DECD A BB 1 NOP 1
DECD B CB 1 NOP 1
DECD + DB 2 NOP 1
DINT "" 06 1 NOP 1
DJNZ A,+ BA 2 R1 1
DJNZ B,+ CA 2 R1 1
DJNZ +,+ DA 3 CREL 1
DSB B,A 6F 1 NOP 1
DSB %+,A 2F 2 NOP 1
DSB %+,B 5F 2 NOP 1
DSB %+,+ 7F 3 COMB 1
DSB +,A 1F 2 NOP 1
DSB +,B 3F 2 NOP 1
DSB +,+ 4F 3 COMB 1
EINT "" 05 1 NOP 1
IDLE "" 01 1 NOP 1
INC A B3 1 NOP 1
INC B C3 1 NOP 1
INC + D3 2 NOP 1
INV A B4 1 NOP 1
INV B C4 1 NOP 1
INV + D4 2 NOP 1
JMP + E0 2 R1 1
JC + E3 2 R1 1
JEQ + E2 2 R1 1
JGE + E5 2 R1 1
JGT + E4 2 R1 1
JHS + E3 2 R1 1
JL + E7 2 R1 1
JN + E1 2 R1 1 /+ ??
JNC + E7 2 R1 1
JNE + E6 2 R1 1
JNZ + E6 2 R1 1
JP + E4 2 R1 1
JPZ + E5 2 R1 1
JZ + E2 2 R1 1
LDA @+(B) AA 3 SWAP 1
LDA @+[B] AA 3 SWAP 1
LDA @+ 8A 3 SWAP 1
LDA *+ 9A 2 NOP 1
LDSP "" 0D 1 NOP 1
MOV A,B C0 1 NOP 1
MOV B,A 62 1 NOP 1
MOV A,+ D0 2 NOP 1
MOV B,+ D1 2 NOP 1
MOV %+,A 22 2 NOP 1
MOV %+,B 52 2 NOP 1
MOV %+,+ 72 3 COMB 1
MOV +,A 12 2 NOP 1
MOV +,B 32 2 NOP 1
MOV +,+ 42 3 COMB 1
MOVD %+[B],+ A8 4 CSWAP 1
MOVD %+,+ 88 4 CSWAP 1
MOVD +,+ 98 3 COMB 1
MOVP A,+ 82 2 NOP 1
MOVP B,+ 92 2 NOP 1
MOVP %+,+ A2 3 COMB 1
MOVP +,A 80 2 NOP 1
MOVP +,B 91 2 NOP 1
MPY B,A 6C 1 NOP 1
MPY %+,A 2C 2 NOP 1
MPY %+,B 5C 2 NOP 1
MPY %+,+ 7C 3 COMB 1
MPY +,A 1C 2 NOP 1
MPY +,B 3C 2 NOP 1
MPY +,+ 4C 3 COMB 1
NOP "" 00 1 NOP 1
OR B,A 64 1 NOP 1
OR %+,A 24 2 NOP 1
OR %+,B 54 2 NOP 1
OR %+,+ 74 3 COMB 1
OR +,A 14 2 NOP 1
OR +,B 34 2 NOP 1
OR +,+ 44 3 COMB 1
ORP A,+ 84 2 NOP 1
ORP B,+ 94 2 NOP 1
ORP %+,+ A4 3 COMB 1
POP A B9 1 NOP 1
POP B C9 1 NOP 1
POP ST 08 1 NOP 1
POP + D9 2 NOP 1
POPST "" 08 1 NOP 1
PUSH A B8 1 NOP 1
PUSH B C8 1 NOP 1
PUSH ST 0E 1 NOP 1
PUSH + D8 2 NOP 1
PUSHST "" 0E 1 NOP 1
RETI "" 0B 1 NOP 1
RETS "" 0A 1 NOP 1
RL A BE 1 NOP 1
RL B CE 1 NOP 1
RL + DE 2 NOP 1
RLC A BF 1 NOP 1
RLC B CF 1 NOP 1
RLC + DF 2 NOP 1
RR A BC 1 NOP 1
RR B CC 1 NOP 1
RR + DC 2 NOP 1
RRC A BD 1 NOP 1
RRC B CD 1 NOP 1
RRC + DD 2 NOP 1
SBB B,A 6B 1 NOP 1
SBB %+,A 2B 2 NOP 1
SBB %+,B 5B 2 NOP 1
SBB %+,+ 7B 3 COMB 1
SBB +,A 1B 2 NOP 1
SBB +,B 3B 2 NOP 1
SBB +,+ 4B 3 COMB 1
SETC "" 07 1 NOP 1
STA @+(B) AB 3 SWAP 1
STA @+[B] AB 3 SWAP 1
STA @+ 8B 3 SWAP 1
STA *+ 9B 2 NOP 1
STSP "" 09 1 NOP 1
SUB B,A 6A 1 NOP 1
SUB %+,A 2A 2 NOP 1
SUB %+,B 5A 2 NOP 1
SUB %+,+ 7A 3 COMB 1
SUB +,A 1A 2 NOP 1
SUB +,B 3A 2 NOP 1
SUB +,+ 4A 3 COMB 1
SWAP A B7 1 NOP 1
SWAP B C7 1 NOP 1
SWAP + D7 2 NOP 1
TRAP + FF 1 SUB 1
TST A B0 1 NOP 1
TSTA "" B0 1 NOP 1
TST B C1 1 NOP 1
TSTB "" C1 1 NOP 1
XCHB A B6 1 NOP 1
XCHB + D6 2 NOP 1
XOR B,A 65 1 NOP 1
XOR %+,A 25 2 NOP 1
XOR %+,B 55 2 NOP 1
XOR %+,+ 75 3 COMB 1
XOR +,A 15 2 NOP 1
XOR +,B 35 2 NOP 1
XOR +,+ 45 3 COMB 1
XORP A,+ 85 2 NOP 1
XORP B,+ 95 2 NOP 1
XORP %+,+ A5 3 COMB 1

594
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"TASM Z80 Assembler. "
/****************************************************************************
/* $Id: tasm80.tab 1.2 1998/02/28 14:31:22 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the Z80 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/* This table authored and submitted by Carl A. Wall, VE3APY.
/*
/* Class bits assigned as follows:
/* Bit-0 = Z80 (base instruction set)
/* Bit-1 = HD64180 (extended instructions)
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */
/*-------------------------------------------*/
ADC A,(HL) 8E 1 NOP 1
ADC A,(IX*) 8EDD 3 ZIX 1
ADC A,(IY*) 8EFD 3 ZIX 1
ADC A,A 8F 1 NOP 1
ADC A,B 88 1 NOP 1
ADC A,C 89 1 NOP 1
ADC A,D 8A 1 NOP 1
ADC A,E 8B 1 NOP 1
ADC A,H 8C 1 NOP 1
ADC A,L 8D 1 NOP 1
ADC A,* CE 2 NOP 1
ADC HL,BC 4AED 2 NOP 1
ADC HL,DE 5AED 2 NOP 1
ADC HL,HL 6AED 2 NOP 1
ADC HL,SP 7AED 2 NOP 1
ADD A,(HL) 86 1 NOP 1
ADD A,(IX*) 86DD 3 ZIX 1
ADD A,(IY*) 86FD 3 ZIX 1
ADD A,A 87 1 NOP 1
ADD A,B 80 1 NOP 1
ADD A,C 81 1 NOP 1
ADD A,D 82 1 NOP 1
ADD A,E 83 1 NOP 1
ADD A,H 84 1 NOP 1
ADD A,L 85 1 NOP 1
ADD A,* C6 2 NOP 1
ADD HL,BC 09 1 NOP 1
ADD HL,DE 19 1 NOP 1
ADD HL,HL 29 1 NOP 1
ADD HL,SP 39 1 NOP 1
ADD IX,BC 09DD 2 NOP 1
ADD IX,DE 19DD 2 NOP 1
ADD IX,IX 29DD 2 NOP 1
ADD IX,SP 39DD 2 NOP 1
ADD IY,BC 09FD 2 NOP 1
ADD IY,DE 19FD 2 NOP 1
ADD IY,IY 29FD 2 NOP 1
ADD IY,SP 39FD 2 NOP 1
AND (HL) A6 1 NOP 1
AND (IX*) A6DD 3 ZIX 1
AND (IY*) A6FD 3 ZIX 1
AND A A7 1 NOP 1
AND B A0 1 NOP 1
AND C A1 1 NOP 1
AND D A2 1 NOP 1
AND E A3 1 NOP 1
AND H A4 1 NOP 1
AND L A5 1 NOP 1
AND * E6 2 NOP 1
BIT *,(HL) 46CB 2 ZBIT 1
BIT *,(IX*) CBDD 4 ZBIT 1 0 4600
BIT *,(IY*) CBFD 4 ZBIT 1 0 4600
BIT *,A 47CB 2 ZBIT 1
BIT *,B 40CB 2 ZBIT 1
BIT *,C 41CB 2 ZBIT 1
BIT *,D 42CB 2 ZBIT 1
BIT *,E 43CB 2 ZBIT 1
BIT *,H 44CB 2 ZBIT 1
BIT *,L 45CB 2 ZBIT 1
CALL C,* DC 3 NOP 1
CALL M,* FC 3 NOP 1
CALL NC,* D4 3 NOP 1
CALL NZ,* C4 3 NOP 1
CALL P,* F4 3 NOP 1
CALL PE,* EC 3 NOP 1
CALL PO,* E4 3 NOP 1
CALL Z,* CC 3 NOP 1
CALL * CD 3 NOP 1
CCF "" 3F 1 NOP 1
CP (HL) BE 1 NOP 1
CP (IX*) BEDD 3 ZIX 1
CP (IY*) BEFD 3 ZIX 1
CP A BF 1 NOP 1
CP B B8 1 NOP 1
CP C B9 1 NOP 1
CP D BA 1 NOP 1
CP E BB 1 NOP 1
CP H BC 1 NOP 1
CP L BD 1 NOP 1
CP * FE 2 NOP 1
CPD "" A9ED 2 NOP 1
CPDR "" B9ED 2 NOP 1
CPIR "" B1ED 2 NOP 1
CPI "" A1ED 2 NOP 1
CPL "" 2F 1 NOP 1
DAA "" 27 1 NOP 1
DEC (HL) 35 1 NOP 1
DEC (IX*) 35DD 3 ZIX 1
DEC (IY*) 35FD 3 ZIX 1
DEC A 3D 1 NOP 1
DEC B 05 1 NOP 1
DEC BC 0B 1 NOP 1
DEC C 0D 1 NOP 1
DEC D 15 1 NOP 1
DEC DE 1B 1 NOP 1
DEC E 1D 1 NOP 1
DEC H 25 1 NOP 1
DEC HL 2B 1 NOP 1
DEC IX 2BDD 2 NOP 1
DEC IY 2BFD 2 NOP 1
DEC L 2D 1 NOP 1
DEC SP 3B 1 NOP 1
DI "" F3 1 NOP 1
DJNZ * 10 2 R1 1
EI "" FB 1 NOP 1
EX (SP),HL E3 1 NOP 1
EX (SP),IX E3DD 2 NOP 1
EX (SP),IY E3FD 2 NOP 1
EX AF,AF' 08 1 NOP 1
EX DE,HL EB 1 NOP 1
EXX "" D9 1 NOP 1
HALT "" 76 1 NOP 1
IM 0 46ED 2 NOP 1
IM 1 56ED 2 NOP 1
IM 2 5EED 2 NOP 1
/* Alternate form of above
IM0 46ED 2 NOP 1
IM1 56ED 2 NOP 1
IM2 5EED 2 NOP 1
IN A,(C) 78ED 2 NOP 1
IN B,(C) 40ED 2 NOP 1
IN C,(C) 48ED 2 NOP 1
IN D,(C) 50ED 2 NOP 1
IN E,(C) 58ED 2 NOP 1
IN H,(C) 60ED 2 NOP 1
IN L,(C) 68ED 2 NOP 1
IN A,(*) DB 2 NOP 1
IN0 A,(*) 38ED 3 NOP 2
IN0 B,(*) 00ED 3 NOP 2
IN0 C,(*) 08ED 3 NOP 2
IN0 D,(*) 10ED 3 NOP 2
IN0 E,(*) 18ED 3 NOP 2
IN0 H,(*) 20ED 3 NOP 2
IN0 L,(*) 28ED 3 NOP 2
INC (HL) 34 1 NOP 1
INC (IX*) 34DD 3 ZIX 1
INC (IY*) 34FD 3 ZIX 1
INC A 3C 1 NOP 1
INC B 04 1 NOP 1
INC BC 03 1 NOP 1
INC C 0C 1 NOP 1
INC D 14 1 NOP 1
INC DE 13 1 NOP 1
INC E 1C 1 NOP 1
INC H 24 1 NOP 1
INC HL 23 1 NOP 1
INC IX 23DD 2 NOP 1
INC IY 23FD 2 NOP 1
INC L 2C 1 NOP 1
INC SP 33 1 NOP 1
IND "" AAED 2 NOP 1
INDR "" BAED 2 NOP 1
INI "" A2ED 2 NOP 1
INIR "" B2ED 2 NOP 1
JP (HL) E9 1 NOP 1
JP (IX) E9DD 2 NOP 1
JP (IY) E9FD 2 NOP 1
JP C,* DA 3 NOP 1
JP M,* FA 3 NOP 1
JP NC,* D2 3 NOP 1
JP NZ,* C2 3 NOP 1
JP P,* F2 3 NOP 1
JP PE,* EA 3 NOP 1
JP PO,* E2 3 NOP 1
JP Z,* CA 3 NOP 1
JP * C3 3 NOP 1
JR C,* 38 2 R1 1
JR NC,* 30 2 R1 1
JR NZ,* 20 2 R1 1
JR Z,* 28 2 R1 1
JR * 18 2 R1 1
LD (BC),A 02 1 NOP 1
LD (DE),A 12 1 NOP 1
LD (HL),A 77 1 NOP 1
LD (HL),B 70 1 NOP 1
LD (HL),C 71 1 NOP 1
LD (HL),D 72 1 NOP 1
LD (HL),E 73 1 NOP 1
LD (HL),H 74 1 NOP 1
LD (HL),L 75 1 NOP 1
LD (HL),* 36 2 NOP 1
LD (IX*),A 77DD 3 ZIX 1
LD (IX*),B 70DD 3 ZIX 1
LD (IX*),C 71DD 3 ZIX 1
LD (IX*),D 72DD 3 ZIX 1
LD (IX*),E 73DD 3 ZIX 1
LD (IX*),H 74DD 3 ZIX 1
LD (IX*),L 75DD 3 ZIX 1
LD (IX*),* 36DD 4 ZIX 1
LD (IY*),A 77FD 3 ZIX 1
LD (IY*),B 70FD 3 ZIX 1
LD (IY*),C 71FD 3 ZIX 1
LD (IY*),D 72FD 3 ZIX 1
LD (IY*),E 73FD 3 ZIX 1
LD (IY*),H 74FD 3 ZIX 1
LD (IY*),L 75FD 3 ZIX 1
LD (IY*),* 36FD 4 ZIX 1
LD (*),A 32 3 NOP 1
LD (*),BC 43ED 4 NOP 1
LD (*),DE 53ED 4 NOP 1
LD (*),HL 22 3 NOP 1
LD (*),IX 22DD 4 NOP 1
LD (*),IY 22FD 4 NOP 1
LD (*),SP 73ED 4 NOP 1
LD A,(BC) 0A 1 NOP 1
LD A,(DE) 1A 1 NOP 1
LD A,(HL) 7E 1 NOP 1
LD A,(IX*) 7EDD 3 ZIX 1
LD A,(IY*) 7EFD 3 ZIX 1
LD A,A 7F 1 NOP 1
LD A,B 78 1 NOP 1
LD A,C 79 1 NOP 1
LD A,D 7A 1 NOP 1
LD A,E 7B 1 NOP 1
LD A,H 7C 1 NOP 1
LD A,I 57ED 2 NOP 1
LD A,L 7D 1 NOP 1
LD A,R 5FED 2 NOP 1
LD A,(*) 3A 3 NOP 1
LD A,* 3E 2 NOP 1
LD B,(HL) 46 1 NOP 1
LD B,(IX*) 46DD 3 ZIX 1
LD B,(IY*) 46FD 3 ZIX 1
LD B,A 47 1 NOP 1
LD B,B 40 1 NOP 1
LD B,C 41 1 NOP 1
LD B,D 42 1 NOP 1
LD B,E 43 1 NOP 1
LD B,H 44 1 NOP 1
LD B,L 45 1 NOP 1
LD B,* 06 2 NOP 1
LD BC,(*) 4BED 4 NOP 1
LD BC,* 01 3 NOP 1
LD C,(HL) 4E 1 NOP 1
LD C,(IX*) 4EDD 3 ZIX 1
LD C,(IY*) 4EFD 3 ZIX 1
LD C,A 4F 1 NOP 1
LD C,B 48 1 NOP 1
LD C,C 49 1 NOP 1
LD C,D 4A 1 NOP 1
LD C,E 4B 1 NOP 1
LD C,H 4C 1 NOP 1
LD C,L 4D 1 NOP 1
LD C,* 0E 2 NOP 1
LD D,(HL) 56 1 NOP 1
LD D,(IX*) 56DD 3 ZIX 1
LD D,(IY*) 56FD 3 ZIX 1
LD D,A 57 1 NOP 1
LD D,B 50 1 NOP 1
LD D,C 51 1 NOP 1
LD D,D 52 1 NOP 1
LD D,E 53 1 NOP 1
LD D,H 54 1 NOP 1
LD D,L 55 1 NOP 1
LD D,* 16 2 NOP 1
LD DE,(*) 5BED 4 NOP 1
LD DE,* 11 3 NOP 1
LD E,(HL) 5E 1 NOP 1
LD E,(IX*) 5EDD 3 ZIX 1
LD E,(IY*) 5EFD 3 ZIX 1
LD E,A 5F 1 NOP 1
LD E,B 58 1 NOP 1
LD E,C 59 1 NOP 1
LD E,D 5A 1 NOP 1
LD E,E 5B 1 NOP 1
LD E,H 5C 1 NOP 1
LD E,L 5D 1 NOP 1
LD E,* 1E 2 NOP 1
LD H,(HL) 66 1 NOP 1
LD H,(IX*) 66DD 3 ZIX 1
LD H,(IY*) 66FD 3 ZIX 1
LD H,A 67 1 NOP 1
LD H,B 60 1 NOP 1
LD H,C 61 1 NOP 1
LD H,D 62 1 NOP 1
LD H,E 63 1 NOP 1
LD H,H 64 1 NOP 1
LD H,L 65 1 NOP 1
LD H,* 26 2 NOP 1
LD HL,(*) 2A 3 NOP 1
LD HL,* 21 3 NOP 1
LD I,A 47ED 2 NOP 1
LD IX,(*) 2ADD 4 NOP 1
LD IX,* 21DD 4 NOP 1
LD IY,(*) 2AFD 4 NOP 1
LD IY,* 21FD 4 NOP 1
LD L,(HL) 6E 1 NOP 1
LD L,(IX*) 6EDD 3 ZIX 1
LD L,(IY*) 6EFD 3 ZIX 1
LD L,A 6F 1 NOP 1
LD L,B 68 1 NOP 1
LD L,C 69 1 NOP 1
LD L,D 6A 1 NOP 1
LD L,E 6B 1 NOP 1
LD L,H 6C 1 NOP 1
LD L,L 6D 1 NOP 1
LD L,* 2E 2 NOP 1
LD R,A 4FED 2 NOP 1
LD SP,(*) 7BED 4 NOP 1
LD SP,HL F9 1 NOP 1
LD SP,IX F9DD 2 NOP 1
LD SP,IY F9FD 2 NOP 1
LD SP,* 31 3 NOP 1
LDD "" A8ED 2 NOP 1
LDDR "" B8ED 2 NOP 1
LDI "" A0ED 2 NOP 1
LDIR "" B0ED 2 NOP 1
NEG "" 44ED 2 NOP 1
NOP "" 00 1 NOP 1
MLT BC 4CED 2 NOP 2
MLT DE 5CED 2 NOP 2
MLT HL 6CED 2 NOP 2
MLT SP 7CED 2 NOP 2
OR (HL) B6 1 NOP 1
OR (IX*) B6DD 3 ZIX 1
OR (IY*) B6FD 3 ZIX 1
OR A B7 1 NOP 1
OR B B0 1 NOP 1
OR C B1 1 NOP 1
OR D B2 1 NOP 1
OR E B3 1 NOP 1
OR H B4 1 NOP 1
OR L B5 1 NOP 1
OR * F6 2 NOP 1
OTDM "" 8BED 2 NOP 2
OTDMR "" 9BED 2 NOP 2
OTDR "" BBED 2 NOP 1
OTIM "" 83ED 2 NOP 2
OTIMR "" 93ED 2 NOP 2
OTIR "" B3ED 2 NOP 1
OUT (C),A 79ED 2 NOP 1
OUT (C),B 41ED 2 NOP 1
OUT (C),C 49ED 2 NOP 1
OUT (C),D 51ED 2 NOP 1
OUT (C),E 59ED 2 NOP 1
OUT (C),H 61ED 2 NOP 1
OUT (C),L 69ED 2 NOP 1
OUT (*),A D3 2 NOP 1
OUT0 (*),A 39ED 3 NOP 2
OUT0 (*),B 01ED 3 NOP 2
OUT0 (*),C 09ED 3 NOP 2
OUT0 (*),D 11ED 3 NOP 2
OUT0 (*),E 19ED 3 NOP 2
OUT0 (*),H 21ED 3 NOP 2
OUT0 (*),L 29ED 3 NOP 2
OUTD "" ABED 2 NOP 1
OUTI "" A3ED 2 NOP 1
POP AF F1 1 NOP 1
POP BC C1 1 NOP 1
POP DE D1 1 NOP 1
POP HL E1 1 NOP 1
POP IX E1DD 2 NOP 1
POP IY E1FD 2 NOP 1
PUSH AF F5 1 NOP 1
PUSH BC C5 1 NOP 1
PUSH DE D5 1 NOP 1
PUSH HL E5 1 NOP 1
PUSH IX E5DD 2 NOP 1
PUSH IY E5FD 2 NOP 1
RES *,(HL) 86CB 2 ZBIT 1
RES *,(IX*) CBDD 4 ZBIT 1 0 8600
RES *,(IY*) CBFD 4 ZBIT 1 0 8600
RES *,A 87CB 2 ZBIT 1
RES *,B 80CB 2 ZBIT 1
RES *,C 81CB 2 ZBIT 1
RES *,D 82CB 2 ZBIT 1
RES *,E 83CB 2 ZBIT 1
RES *,H 84CB 2 ZBIT 1
RES *,L 85CB 2 ZBIT 1
RET "" C9 1 NOP 1
RET C D8 1 NOP 1
RET M F8 1 NOP 1
RET NC D0 1 NOP 1
RET NZ C0 1 NOP 1
RET P F0 1 NOP 1
RET PE E8 1 NOP 1
RET PO E0 1 NOP 1
RET Z C8 1 NOP 1
RETI "" 4DED 2 NOP 1
RETN "" 45ED 2 NOP 1
RL (HL) 16CB 2 NOP 1
RL (IX*) CBDD 4 ZIX 1 0 1600
RL (IY*) CBFD 4 ZIX 1 0 1600
RL A 17CB 2 NOP 1
RL B 10CB 2 NOP 1
RL C 11CB 2 NOP 1
RL D 12CB 2 NOP 1
RL E 13CB 2 NOP 1
RL H 14CB 2 NOP 1
RL L 15CB 2 NOP 1
RLA "" 17 1 NOP 1
RLC (HL) 06CB 2 NOP 1
RLC (IX*) CBDD 4 ZIX 1 0 0600
RLC (IY*) CBFD 4 ZIX 1 0 0600
RLC A 07CB 2 NOP 1
RLC B 00CB 2 NOP 1
RLC C 01CB 2 NOP 1
RLC D 02CB 2 NOP 1
RLC E 03CB 2 NOP 1
RLC H 04CB 2 NOP 1
RLC L 05CB 2 NOP 1
RLCA "" 07 1 NOP 1
RLD "" 6FED 2 NOP 1
RR (HL) 1ECB 2 NOP 1
RR (IX*) CBDD 4 ZIX 1 0 1E00
RR (IY*) CBFD 4 ZIX 1 0 1E00
RR A 1FCB 2 NOP 1
RR B 18CB 2 NOP 1
RR C 19CB 2 NOP 1
RR D 1ACB 2 NOP 1
RR E 1BCB 2 NOP 1
RR H 1CCB 2 NOP 1
RR L 1DCB 2 NOP 1
RRA "" 1F 1 NOP 1
RRC (HL) 0ECB 2 NOP 1
RRC (IX*) CBDD 4 ZIX 1 0 0E00
RRC (IY*) CBFD 4 ZIX 1 0 0E00
RRC A 0FCB 2 NOP 1
RRC B 08CB 2 NOP 1
RRC C 09CB 2 NOP 1
RRC D 0ACB 2 NOP 1
RRC E 0BCB 2 NOP 1
RRC H 0CCB 2 NOP 1
RRC L 0DCB 2 NOP 1
RRCA "" 0F 1 NOP 1
RRD "" 67ED 2 NOP 1
RST 00H C7 1 NOP 1
RST 08H CF 1 NOP 1
RST 10H D7 1 NOP 1
RST 18H DF 1 NOP 1
RST 20H E7 1 NOP 1
RST 28H EF 1 NOP 1
RST 30H F7 1 NOP 1
RST 38H FF 1 NOP 1
/* Alternate form of above
RST 00 C7 1 NOP 1
RST 08 CF 1 NOP 1
RST 10 D7 1 NOP 1
RST 18 DF 1 NOP 1
RST 20 E7 1 NOP 1
RST 28 EF 1 NOP 1
RST 30 F7 1 NOP 1
RST 38 FF 1 NOP 1
SBC A,(HL) 9E 1 NOP 1
SBC A,(IX*) 9EDD 3 ZIX 1
SBC A,(IY*) 9EFD 3 ZIX 1
SBC A,A 9F 1 NOP 1
SBC A,B 98 1 NOP 1
SBC A,C 99 1 NOP 1
SBC A,D 9A 1 NOP 1
SBC A,E 9B 1 NOP 1
SBC A,H 9C 1 NOP 1
SBC A,L 9D 1 NOP 1
SBC HL,BC 42ED 2 NOP 1
SBC HL,DE 52ED 2 NOP 1
SBC HL,HL 62ED 2 NOP 1
SBC HL,SP 72ED 2 NOP 1
SBC A,* DE 2 NOP 1
SCF "" 37 1 NOP 1
SET *,(HL) C6CB 2 ZBIT 1
SET *,(IX*) CBDD 4 ZBIT 1 0 C600
SET *,(IY*) CBFD 4 ZBIT 1 0 C600
SET *,A C7CB 2 ZBIT 1
SET *,B C0CB 2 ZBIT 1
SET *,C C1CB 2 ZBIT 1
SET *,D C2CB 2 ZBIT 1
SET *,E C3CB 2 ZBIT 1
SET *,H C4CB 2 ZBIT 1
SET *,L C5CB 2 ZBIT 1
SLA (HL) 26CB 2 NOP 1
SLA (IX*) CBDD 4 ZIX 1 0 2600
SLA (IY*) CBFD 4 ZIX 1 0 2600
SLA A 27CB 2 NOP 1
SLA B 20CB 2 NOP 1
SLA C 21CB 2 NOP 1
SLA D 22CB 2 NOP 1
SLA E 23CB 2 NOP 1
SLA H 24CB 2 NOP 1
SLA L 25CB 2 NOP 1
SLP "" 76ED 2 NOP 2
SRA (HL) 2ECB 2 NOP 1
SRA (IX*) CBDD 4 ZIX 1 0 2E00
SRA (IY*) CBFD 4 ZIX 1 0 2E00
SRA A 2FCB 2 NOP 1
SRA B 28CB 2 NOP 1
SRA C 29CB 2 NOP 1
SRA D 2ACB 2 NOP 1
SRA E 2BCB 2 NOP 1
SRA H 2CCB 2 NOP 1
SRA L 2DCB 2 NOP 1
SRL (HL) 3ECB 2 NOP 1
SRL (IX*) CBDD 4 ZIX 1 0 3E00
SRL (IY*) CBFD 4 ZIX 1 0 3E00
SRL A 3FCB 2 NOP 1
SRL B 38CB 2 NOP 1
SRL C 39CB 2 NOP 1
SRL D 3ACB 2 NOP 1
SRL E 3BCB 2 NOP 1
SRL H 3CCB 2 NOP 1
SRL L 3DCB 2 NOP 1
SUB (HL) 96 1 NOP 1
SUB (IX*) 96DD 3 ZIX 1
SUB (IY*) 96FD 3 ZIX 1
SUB A 97 1 NOP 1
SUB B 90 1 NOP 1
SUB C 91 1 NOP 1
SUB D 92 1 NOP 1
SUB E 93 1 NOP 1
SUB H 94 1 NOP 1
SUB L 95 1 NOP 1
SUB * D6 2 NOP 1
TST A 3CED 2 NOP 2
TST B 04ED 2 NOP 2
TST C 0CED 2 NOP 2
TST D 14ED 2 NOP 2
TST E 1CED 2 NOP 2
TST H 24ED 2 NOP 2
TST L 2CED 2 NOP 2
TST (HL) 34ED 2 NOP 2
TST * 64ED 3 NOP 2
TSTIO * 74ED 3 NOP 2
XOR (HL) AE 1 NOP 1
XOR (IX*) AEDD 3 ZIX 1
XOR (IY*) AEFD 3 ZIX 1
XOR A AF 1 NOP 1
XOR B A8 1 NOP 1
XOR C A9 1 NOP 1
XOR D AA 1 NOP 1
XOR E AB 1 NOP 1
XOR H AC 1 NOP 1
XOR L AD 1 NOP 1
XOR * EE 2 NOP 1

257
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"TASM 8085 Assembler. "
/****************************************************************************
/* $Id: tasm85.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 8085 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/* This table authored and submitted by Gary Kirk Bach.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS */
/*-----------------*/
ACI * CE 2 NOP 1
ADC B 88 1 NOP 1
ADC C 89 1 NOP 1
ADC D 8A 1 NOP 1
ADC E 8B 1 NOP 1
ADC H 8C 1 NOP 1
ADC L 8D 1 NOP 1
ADC M 8E 1 NOP 1
ADC A 8F 1 NOP 1
ADD B 80 1 NOP 1
ADD C 81 1 NOP 1
ADD D 82 1 NOP 1
ADD E 83 1 NOP 1
ADD H 84 1 NOP 1
ADD L 85 1 NOP 1
ADD M 86 1 NOP 1
ADD A 87 1 NOP 1
ADI * C6 2 NOP 1
ANA B A0 1 NOP 1
ANA C A1 1 NOP 1
ANA D A2 1 NOP 1
ANA E A3 1 NOP 1
ANA H A4 1 NOP 1
ANA L A5 1 NOP 1
ANA M A6 1 NOP 1
ANA A A7 1 NOP 1
ANI * E6 2 NOP 1
CALL * CD 3 NOP 1
CC * DC 3 NOP 1
CM * FC 3 NOP 1
CMA "" 2F 1 NOP 1
CMC "" 3F 1 NOP 1
CMP B B8 1 NOP 1
CMP C B9 1 NOP 1
CMP D BA 1 NOP 1
CMP E BB 1 NOP 1
CMP H BC 1 NOP 1
CMP L BD 1 NOP 1
CMP M BE 1 NOP 1
CMP A BF 1 NOP 1
CNC * D4 3 NOP 1
CNZ * C4 3 NOP 1
CP * F4 3 NOP 1
CPE * EC 3 NOP 1
CPI * FE 2 NOP 1
CPO * E4 3 NOP 1
CZ * CC 3 NOP 1
DAA "" 27 1 NOP 1
DAD B 09 1 NOP 1
DAD D 19 1 NOP 1
DAD H 29 1 NOP 1
DAD SP 39 1 NOP 1
DCR B 05 1 NOP 1
DCR C 0D 1 NOP 1
DCR D 15 1 NOP 1
DCR E 1D 1 NOP 1
DCR H 25 1 NOP 1
DCR L 2D 1 NOP 1
DCR M 35 1 NOP 1
DCR A 3D 1 NOP 1
DCX B 0B 1 NOP 1
DCX D 1B 1 NOP 1
DCX H 2B 1 NOP 1
DCX SP 3B 1 NOP 1
DI "" F3 1 NOP 1
EI "" FB 1 NOP 1
HLT "" 76 1 NOP 1
IN * DB 2 NOP 1
INR B 04 1 NOP 1
INR C 0C 1 NOP 1
INR D 14 1 NOP 1
INR E 1C 1 NOP 1
INR H 24 1 NOP 1
INR L 2C 1 NOP 1
INR M 34 1 NOP 1
INR A 3C 1 NOP 1
INX B 03 1 NOP 1
INX D 13 1 NOP 1
INX H 23 1 NOP 1
INX SP 33 1 NOP 1
JC * DA 3 NOP 1
JM * FA 3 NOP 1
JMP * C3 3 NOP 1
JNC * D2 3 NOP 1
JNZ * C2 3 NOP 1
JP * F2 3 NOP 1
JPE * EA 3 NOP 1
JPO * E2 3 NOP 1
JZ * CA 3 NOP 1
LDA * 3A 3 NOP 1
LDAX B 0A 1 NOP 1
LDAX D 1A 1 NOP 1
LHLD * 2A 3 NOP 1
LXI B,* 01 3 NOP 1
LXI D,* 11 3 NOP 1
LXI H,* 21 3 NOP 1
LXI SP,* 31 3 NOP 1
MOV B,B 40 1 NOP 1
MOV B,C 41 1 NOP 1
MOV B,D 42 1 NOP 1
MOV B,E 43 1 NOP 1
MOV B,H 44 1 NOP 1
MOV B,L 45 1 NOP 1
MOV B,M 46 1 NOP 1
MOV B,A 47 1 NOP 1
MOV C,B 48 1 NOP 1
MOV C,C 49 1 NOP 1
MOV C,D 4A 1 NOP 1
MOV C,E 4B 1 NOP 1
MOV C,H 4C 1 NOP 1
MOV C,L 4D 1 NOP 1
MOV C,M 4E 1 NOP 1
MOV C,A 4F 1 NOP 1
MOV D,B 50 1 NOP 1
MOV D,C 51 1 NOP 1
MOV D,D 52 1 NOP 1
MOV D,E 53 1 NOP 1
MOV D,H 54 1 NOP 1
MOV D,L 55 1 NOP 1
MOV D,M 56 1 NOP 1
MOV D,A 57 1 NOP 1
MOV E,B 58 1 NOP 1
MOV E,C 59 1 NOP 1
MOV E,D 5A 1 NOP 1
MOV E,E 5B 1 NOP 1
MOV E,H 5C 1 NOP 1
MOV E,L 5D 1 NOP 1
MOV E,M 5E 1 NOP 1
MOV E,A 5F 1 NOP 1
MOV H,B 60 1 NOP 1
MOV H,C 61 1 NOP 1
MOV H,D 62 1 NOP 1
MOV H,E 63 1 NOP 1
MOV H,H 64 1 NOP 1
MOV H,L 65 1 NOP 1
MOV H,M 66 1 NOP 1
MOV H,A 67 1 NOP 1
MOV L,B 68 1 NOP 1
MOV L,C 69 1 NOP 1
MOV L,D 6A 1 NOP 1
MOV L,E 6B 1 NOP 1
MOV L,H 6C 1 NOP 1
MOV L,L 6D 1 NOP 1
MOV L,M 6E 1 NOP 1
MOV L,A 6F 1 NOP 1
MOV M,B 70 1 NOP 1
MOV M,C 71 1 NOP 1
MOV M,D 72 1 NOP 1
MOV M,E 73 1 NOP 1
MOV M,H 74 1 NOP 1
MOV M,L 75 1 NOP 1
MOV M,A 77 1 NOP 1
MOV A,B 78 1 NOP 1
MOV A,C 79 1 NOP 1
MOV A,D 7A 1 NOP 1
MOV A,E 7B 1 NOP 1
MOV A,H 7C 1 NOP 1
MOV A,L 7D 1 NOP 1
MOV A,M 7E 1 NOP 1
MOV A,A 7F 1 NOP 1
MVI B,* 06 2 NOP 1
MVI C,* 0E 2 NOP 1
MVI D,* 16 2 NOP 1
MVI E,* 1E 2 NOP 1
MVI H,* 26 2 NOP 1
MVI L,* 2E 2 NOP 1
MVI M,* 36 2 NOP 1
MVI A,* 3E 2 NOP 1
NOP "" 00 1 NOP 1
ORA B B0 1 NOP 1
ORA C B1 1 NOP 1
ORA D B2 1 NOP 1
ORA E B3 1 NOP 1
ORA H B4 1 NOP 1
ORA L B5 1 NOP 1
ORA M B6 1 NOP 1
ORA A B7 1 NOP 1
ORI * F6 2 NOP 1
OUT * D3 2 NOP 1
PCHL "" E9 1 NOP 1
POP B C1 1 NOP 1
POP D D1 1 NOP 1
POP H E1 1 NOP 1
POP PSW F1 1 NOP 1
PUSH B C5 1 NOP 1
PUSH D D5 1 NOP 1
PUSH H E5 1 NOP 1
PUSH PSW F5 1 NOP 1
RAL "" 17 1 NOP 1
RAR "" 1F 1 NOP 1
RC "" D8 1 NOP 1
RET "" C9 1 NOP 1
RIM "" 20 1 NOP 1
RLC "" 07 1 NOP 1
RM "" F8 1 NOP 1
RNC "" D0 1 NOP 1
RNZ "" C0 1 NOP 1
RP "" F0 1 NOP 1
RPE "" E8 1 NOP 1
RPO "" E0 1 NOP 1
RRC "" 0F 1 NOP 1
RST 0 C7 1 NOP 1
RST 1 CF 1 NOP 1
RST 2 D7 1 NOP 1
RST 3 DF 1 NOP 1
RST 4 E7 1 NOP 1
RST 5 EF 1 NOP 1
RST 6 F7 1 NOP 1
RST 7 FF 1 NOP 1
RZ "" C8 1 NOP 1
SBB B 98 1 NOP 1
SBB C 99 1 NOP 1
SBB D 9A 1 NOP 1
SBB E 9B 1 NOP 1
SBB H 9C 1 NOP 1
SBB L 9D 1 NOP 1
SBB M 9E 1 NOP 1
SBB A 9F 1 NOP 1
SBI * DE 2 NOP 1
SHLD * 22 3 NOP 1
SIM "" 30 1 NOP 1
SPHL "" F9 1 NOP 1
STA * 32 3 NOP 1
STAX B 02 1 NOP 1
STAX D 12 1 NOP 1
STC "" 37 1 NOP 1
SUB B 90 1 NOP 1
SUB C 91 1 NOP 1
SUB D 92 1 NOP 1
SUB E 93 1 NOP 1
SUB H 94 1 NOP 1
SUB L 95 1 NOP 1
SUB M 96 1 NOP 1
SUB A 97 1 NOP 1
SUI * D6 2 NOP 1
XCHG "" EB 1 NOP 1
XRA B A8 1 NOP 1
XRA C A9 1 NOP 1
XRA D AA 1 NOP 1
XRA E AB 1 NOP 1
XRA H AC 1 NOP 1
XRA L AD 1 NOP 1
XRA M AE 1 NOP 1
XRA A AF 1 NOP 1
XRI * EE 2 NOP 1
XTHL "" E3 1 NOP 1

393
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"TASM 8096 Assembler."
/****************************************************************************
/* $Id: tasm96.tab 1.5 1997/09/28 22:14:30 toma Exp $
/****************************************************************************
;* This is the instruction set definition table
;* for the 8096 version of TASM.
;* Thomas N. Anderson, Speech Technology Incorporated
;*
;* See TASM manual for info on table structure.
;*
;*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT MASK
;*-------------------------------------------*
; Revisions:
; Added I7 rule for single arg direct/far (PUSH/POP)
; Changed ADDB *,*,*[*] entry from rule I1 to I6.
;
; Generate opcodes high byte first/
.MSFIRST
.NOARGSHIFT
;
; Note:
; The I1 rule uses ARGVAL for arg validation. If the combined
; args AND ARGVAL is not equal to the combined args then an
; error message is generated.
;
; The I1 rule also uses ARGOR. The value of that mask is OR'd
; with the first byte of the args.
;
; ARGOR
; BYTES CLASS |
; | | |
;INST ARGS OP v RULE v v ARGVAL
;-----------------------------------------;
;OK ADD
ADD *,*,[*]+ 46 4 I1 1 01 00FeFeFe ;
ADD *,*,[*] 46 4 I1 1 00 00FeFeFe ;
ADD *,*,*[*] 47 6 I6 1 00 00FeFeFe ;
ADD *,*,#* 45 5 I1 1 00 FeFeFFFF ;
ADD *,[*]+ 66 3 I1 1 01 0000FFFe ; 1st arg must be even, make odd
ADD *,[*] 66 3 I1 1 00 0000FFFe ; 1st arg must be even
ADD *,*[*] 67 5 I6 1 00 00FFFFFF ;
ADD *,*,* 4701 6 I3 1 00 0000FeFe ; 3rd arg may be far
ADD *,#* 65 4 I1 1 00 00FeFFFF ; 1st arg must be even
ADD *,* 6701 5 I2 1 00 0000FeFe ; 2nd arg may be far
;OK ADDB
ADDB *,*,[*]+ 56 4 I1 1 01 00000000 ; no validation yet
ADDB *,*,[*] 56 4 I1 1 00 00000000 ; no validation yet
ADDB *,*,*[*] 57 6 I6 1 00 00000000 ; no validation yet
ADDB *,*,#* 55 4 I1 1 00 00000000 ; no validation yet
ADDB *,[*]+ 76 3 I1 1 01 0000FFFe ; 1st arg must be even, make odd
ADDB *,[*] 76 3 I1 1 00 0000FFFe ; 1st arg must be even
ADDB *,*[*] 77 5 I6 1 00 00FeFFFe ; 1st,3rd must be even
ADDB *,*,* 5701 6 I3 1 00 00000000 ; 3rd arg may be far
ADDB *,#* 75 3 I1 1 00 00FFFFFF ; odd args ok for byte operations
ADDB *,* 7701 5 I2 1 00 00000000 ; 2nd arg may be far
; No three arg forms for ADDC or ADDCB
ADDC *,[*]+ A6 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ADDC *,[*] A6 3 I1 1 00 0000FFFe ;1st arg must be even
ADDC *,*[*] A7 5 I6 1 00 00FFFFFF ;
ADDC *,#* A5 4 I1 1 00 00FeFFFF ;1st arg must be even
ADDC *,* A701 5 I2 1 00 00000000 ;2nd arg may be far
ADDCB *,[*]+ B6 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ADDCB *,[*] B6 3 I1 1 00 0000FFFe ;1st arg must be even
ADDCB *,*[*] B7 5 I6 1 00 00FFFFFF ;
ADDCB *,#* B5 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
ADDCB *,* B701 5 I2 1 00 00000000 ;2nd arg may be far
; OK AND
AND *,*,[*]+ 42 4 I1 1 01 00000000 ;no validation yet
AND *,*,[*] 42 4 I1 1 00 00000000 ;no validation yet
AND *,*,*[*] 43 6 I6 1 00 00000000 ;no validation yet
AND *,*,#* 41 5 I1 1 00 00000000 ;no validation yet
AND *,[*]+ 62 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
AND *,[*] 62 3 I1 1 00 0000FFFe ;1st arg must be even
AND *,*[*] 63 5 I6 1 00 00FeFFFe ;1st,3rd must be even
AND *,*,* 4301 6 I3 1 00 00000000 ;3rd arg may be far
AND *,#* 61 4 I1 1 00 00FeFFFF ;1st arg must be even
AND *,* 6301 5 I2 1 00 00000000 ;2nd arg may be far
ANDB *,*,[*]+ 52 4 I1 1 01 00000000 ;no validation yet
ANDB *,*,[*] 52 4 I1 1 00 00000000 ;no validation yet
ANDB *,*,*[*] 53 6 I6 1 00 00000000 ;no validation yet
ANDB *,*,#* 51 4 I1 1 00 00000000 ;no validation yet
ANDB *,[*]+ 72 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ANDB *,[*] 72 3 I1 1 00 0000FFFe ;1st arg must be even
ANDB *,*[*] 73 5 I6 1 00 00FFFFFF ;
ANDB *,*,* 5301 6 I3 1 00 00000000 ;3rd arg may be far
ANDB *,#* 71 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
ANDB *,* 7301 5 I2 1 00 00000000 ;2nd arg may be far
BMOV *,* C1 3 I1 2 00 0000FcFF ;long word ptr to two words
BMOVI *,* AD 3 I1 2 00 0000FcFF ;long word ptr to two words
BR [*] E3 2 I1 1 00 00000000 ;
BR * 2000 2 I5 1 00 00000000 ; Same As SJMP
CLR * 01 2 NOP 1 00 00000000 ;
CLRB * 11 2 NOP 1 00 00000000 ;
CLRC "" F8 1 NOP 1 00 00000000 ;
CLRVT "" FC 1 NOP 1 00 00000000 ;
CMP *,[*]+ 8A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
CMP *,[*] 8A 3 I1 1 00 0000FFFe ;1st arg must be even
CMP *,*[*] 8B 5 I6 1 00 00FFFFFF ;
CMP *,#* 89 4 I1 1 00 00FeFFFF ;1st arg must be even
CMP *,* 8B01 5 I2 1 00 00000000 ;2nd arg may be far
CMPB *,[*]+ 9A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
CMPB *,[*] 9A 3 I1 1 00 0000FFFe ;1st arg must be even
CMPB *,*[*] 9B 5 I6 1 00 00FFFFFF ;
CMPB *,#* 99 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
CMPB *,* 9B01 5 I2 1 00 00000000 ;2nd arg may be far
CMPL *,* C5 3 I1 2 00 0000FcFc ;long align multiple of 4
DEC * 05 2 NOP 1 00 00000000 ;
DECB * 15 2 NOP 1 00 00000000 ;
DJNZ *,* E0 3 CREL 1 00 00000000 ;
DJNZW *,* E1 3 CREL 2 00 00000000 ;
DI "" FA 1 NOP 1 00 00000000 ;
DIVU *,[*]+ 8E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIVU *,[*] 8E 3 I1 1 00 0000FFFe ;1st arg must be even
DIVU *,*[*] 8F 5 I6 1 00 0000FFFe ;1st arg must be even
DIVU *,#* 8D 4 I1 1 00 00FeFFFF ;1st arg must be even
DIVU *,* 8F01 5 I2 1 00 00000000 ;2nd arg may be far
DIVUB *,[*]+ 9E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIVUB *,[*] 9E 3 I1 1 00 0000FFFe ;1st arg must be even
DIVUB *,*[*] 9F 5 I6 1 00 0000FFFF ;
DIVUB *,#* 9D 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
DIVUB *,* 9F01 5 I2 1 00 00000000 ;2nd arg may be far
DIV *,[*]+ FE8E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIV *,[*] FE8E 4 I1 1 00 0000FFFe ;1st arg must be even
DIV *,*[*] FE8F 6 I6 1 00 0000FFFe ;1st arg must be even
DIV *,#* FE8D 5 I1 1 00 00FeFFFF ;1st arg must be even
DIV *,* FE8F01 6 I2 1 00 00000000 ;2nd arg may be far
DIVB *,[*]+ FE9E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIVB *,[*] FE9E 4 I1 1 00 0000FFFe ;1st arg must be even
DIVB *,*[*] FE9F 6 I6 1 00 0000FFFF ;
DIVB *,#* FE9D 4 I1 1 00 00FFFFFF ;odd args ok for byte operations;
DIVB *,* FE9F01 6 I2 1 00 00000000 ;2nd arg may be far
DPTS "" EC 1 NOP 2 00 00000000 ;
EPTS "" ED 1 NOP 2 00 00000000 ;
EI "" FB 1 NOP 1 00 00000000 ;
EXT * 06 2 NOP 1 00 00000000 ;
EXTB * 16 2 NOP 1 00 00000000 ;
IDLPD #* F6 2 NOP 2 00 00000000 ;
INC * 07 2 NOP 1 00 00000000 ;
INCB * 17 2 NOP 1 00 00000000 ;
JC * DB 2 R1 1 00 00000000
JNC * D3 2 R1 1 00 00000000
JH * D9 2 R1 1 00 00000000
JNH * D1 2 R1 1 00 00000000
JE * DF 2 R1 1 00 00000000
JNE * D7 2 R1 1 00 00000000
JV * DD 2 R1 1 00 00000000
JNV * D5 2 R1 1 00 00000000
JGE * D6 2 R1 1 00 00000000
JLT * DE 2 R1 1 00 00000000
JVT * DC 2 R1 1 00 00000000
JNVT * D4 2 R1 1 00 00000000
JGT * D2 2 R1 1 00 00000000
JLE * DA 2 R1 1 00 00000000
JST * D8 2 R1 1 00 00000000
JNST * D0 2 R1 1 00 00000000
JBC *,*,* 30 3 I4 1 00 00000000
JBS *,*,* 38 3 I4 1 00 00000000
LJMP * E7 3 R2 1 00 00000000
LCALL * EF 3 R2 1 00 00000000
LD *,[*]+ A2 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LD *,[*] A2 3 I1 1 00 0000FFFe ;1st arg must be even
LD *,*[*] A3 5 I6 1 00 00FFFFFF ;
LD *,#* A1 4 I1 1 00 00FFFFFF ;
LD *,* A301 5 I2 1 00 00000000 ;2nd arg may be far
LDB *,[*]+ B2 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LDB *,[*] B2 3 I1 1 00 0000FFFe ;1st arg must be even
LDB *,*[*] B3 5 I6 1 00 00FFFFFF ;
LDB *,#* B1 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
LDB *,* B301 5 I2 1 00 00000000 ;2nd arg may be far
LDBSE *,[*]+ BE 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LDBSE *,[*] BE 3 I1 1 00 0000FFFe ;1st arg must be even
LDBSE *,*[*] BF 5 I6 1 00 00FeFFFe ;1st,3rd must be even
LDBSE *,#* BD 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
LDBSE *,* BF01 5 I2 1 00 00000000 ;2nd arg may be far
LDBZE *,[*]+ AE 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LDBZE *,[*] AE 3 I1 1 00 0000FFFe ;1st arg must be even
LDBZE *,*[*] AF 5 I6 1 00 00FeFFFe ;1st,3rd must be even
LDBZE *,#* AD 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
LDBZE *,* AF01 5 I2 1 00 00000000 ;2nd arg may be far
MULU *,*,[*]+ 4E 4 I1 1 01 00000000 ;no validation yet
MULU *,*,[*] 4E 4 I1 1 00 00000000 ;no validation yet
MULU *,*,*[*] 4F 6 I6 1 00 00000000 ;no validation yet
MULU *,*,#* 4D 5 I1 1 00 00000000 ;no validation yet
MULU *,[*]+ 6E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
MULU *,[*] 6E 3 I1 1 00 0000FFFe ;1st arg must be even
MULU *,*[*] 6F 5 I6 1 00 00FeFFFe ;1st,3rd must be even
MULU *,*,* 4F01 6 I3 1 00 00000000 ;3rd arg may be far
MULU *,#* 6D 4 I1 1 00 00FeFFFF ;1st arg must be even
MULU *,* 6F01 5 I2 1 00 00000000 ;2nd arg may be far
MULUB *,*,[*]+ 5E 4 I1 1 01 00000000 ;no validation yet
MULUB *,*,[*] 5E 4 I1 1 00 00000000 ;no validation yet
MULUB *,*,*[*] 5F 6 I6 1 00 00000000 ;no validation yet
MULUB *,*,#* 5D 4 I1 1 00 00000000 ;no validation yet
MULUB *,[*]+ 7E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
MULUB *,[*] 7E 3 I1 1 00 0000FFFe ;1st arg must be even
MULUB *,*[*] 7F 5 I6 1 00 00FFFFFF ;
MULUB *,*,* 5F01 6 I3 1 00 00000000 ;3rd arg may be far
MULUB *,#* 7D 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
MULUB *,* 7F01 5 I2 1 00 00000000 ;2nd arg may be far
MUL *,*,[*]+ FE4E 5 I1 1 01 00000000 ;no validation yet
MUL *,*,[*] FE4E 5 I1 1 00 00000000 ;no validation yet
MUL *,*,*[*] FE4F 7 I6 1 00 00000000 ;no validation yet
MUL *,*,#* FE4D 6 I1 1 00 00000000 ;no validation yet
MUL *,[*]+ FE6E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
MUL *,[*] FE6E 4 I1 1 00 0000FFFe ;1st arg must be even
MUL *,*[*] FE6F 6 I6 1 00 00FeFFFe ;1st,3rd must be even
MUL *,*,* FE4F01 7 I3 1 00 00000000 ;3rd arg may be far
MUL *,#* FE6D 5 I1 1 00 00FFFFFF ;odd args ok for byte operations
MUL *,* FE6F01 6 I2 1 00 00000000 ;2nd arg may be far
MULB *,*,[*]+ FE5E 5 I1 1 01 00000000 ;no validation yet
MULB *,*,[*] FE5E 5 I1 1 00 00000000 ;no validation yet
MULB *,*,*[*] FE5F 7 I6 1 00 00000000 ;no validation yet
MULB *,*,#* FE5D 5 I1 1 00 00000000 ;no validation yet
MULB *,[*]+ FE7E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
MULB *,[*] FE7E 4 I1 1 00 0000FFFe ;1st arg must be even
MULB *,*[*] FE7F 6 I6 1 00 00FFFFFF ;
MULB *,*,* FE5F01 7 I3 1 00 00000000 ;3rd arg may be far
MULB *,#* FE7D 4 I1 1 00 00FFFFFF ;odd args ok for byte operations
MULB *,* FE7F01 6 I2 1 00 00000000 ;2nd arg may be far
NEG * 03 2 I1 1 00 000000FE ;arg must be even
NEGB * 13 2 I1 1 00 000000FF ;
NOP "" FD 1 NOP 1 00 00000000 ;
NORML *,* 0F 3 I1 1 00 0000FFFF ;long align
NOT * 02 2 NOP 1 00 00000000 ;
NOTB * 12 2 NOP 1 00 00000000 ;
OR *,[*]+ 82 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
OR *,[*] 82 3 I1 1 00 0000FFFe ;1st arg must be even
OR *,*[*] 83 5 I6 1 00 00FeFFFe ;1st,3rd must be even
OR *,#* 81 4 I1 1 00 00FeFFFF ;1st arg must be even
OR *,* 8301 5 I2 1 00 00000000 ;2nd arg may be far
ORB *,[*]+ 92 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ORB *,[*] 92 3 I1 1 00 0000FFFe ;1st arg must be even
ORB *,*[*] 93 5 I6 1 00 00FFFFFF ;
ORB *,#* 91 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
ORB *,* 9301 5 I2 1 00 00000000 ;2nd arg may be far
PUSH #* C9 3 I1 1 00 00000000 ;
PUSH [*]+ CA 2 I1 1 01 000000Fe ;arg must be even
PUSH [*] CA 2 I1 1 00 000000Fe ;arg must be even
PUSH *[*] CB 4 I6 1 00 00FFFFFe ;arg must be even
PUSH * CB01 4 I7 1 00 0000FFFe ;arg must be even
PUSHF "" F2 1 NOP 1 00 00000000 ;
PUSHA "" F4 1 NOP 1 00 00000000 ;
POP [*]+ CE 2 I1 1 01 000000Fe ;arg must be even
POP [*] CE 2 I1 1 00 000000Fe ;arg must be even
POP *[*] CF 4 I6 1 00 00FFFFFE ;
POP * CF01 4 I7 1 00 0000FFFe ;arg must be even
POPF "" F3 1 NOP 1 00 00000000 ;
POPA "" F5 1 NOP 1 00 00000000 ;
RET "" F0 1 NOP 1 00 00000000 ;
RST "" FF 1 NOP 1 00 00000000 ;
SJMP * 2000 2 I5 1 00 00000000
SCALL * 2800 2 I5 1 00 00000000
SUB *,*,[*]+ 4A 4 I1 1 01 00000000 ;no validation yet
SUB *,*,[*] 4A 4 I1 1 00 00000000 ;no validation yet
SUB *,*,*[*] 4B 6 I6 1 00 00000000 ;no validation yet
SUB *,*,#* 49 5 I1 1 00 00000000 ;no validation yet
SUB *,[*]+ 6A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUB *,[*] 6A 3 I1 1 00 0000FFFe ;1st arg must be even
SUB *,*[*] 6B 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUB *,*,* 4B01 6 I3 1 00 00000000 ;3rd arg may be far
SUB *,#* 69 4 I1 1 00 00FeFFFF ;1st arg must be even
SUB *,* 6B01 5 I2 1 00 00000000 ;2nd arg may be far
SUBB *,*,[*]+ 5A 4 I1 1 01 00000000 ;no validation yet
SUBB *,*,[*] 5A 4 I1 1 00 00000000 ;no validation yet
SUBB *,*,*[*] 5B 6 I6 1 00 00000000 ;no validation yet
SUBB *,*,#* 59 4 I1 1 00 00000000 ;no validation yet
SUBB *,[*]+ 7A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUBB *,[*] 7A 3 I1 1 00 0000FFFe ;1st arg must be even
SUBB *,*[*] 7B 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUBB *,*,* 5B01 6 I3 1 00 00000000 ;3rd arg may be far
SUBB *,#* 79 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
SUBB *,* 7B01 5 I2 1 00 00000000 ;2nd arg may be far
SUBC *,[*]+ AA 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUBC *,[*] AA 3 I1 1 00 0000FFFe ;1st arg must be even
SUBC *,*[*] AB 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUBC *,#* A9 4 I1 1 00 00FeFFFF ;1st arg must be even
SUBC *,* AB01 5 I2 1 00 00000000 ;2nd arg may be far
SUBCB *,[*]+ BA 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUBCB *,[*] BA 3 I1 1 00 0000FFFe ;1st arg must be even
SUBCB *,*[*] BB 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUBCB *,#* B9 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
SUBCB *,* BB01 5 I2 1 00 00000000 ;2nd arg may be far
SHL *,#* 09 3 I1 1 00 0000FE0F ; F
SHL *,* 09 3 I1 1 00 0000FEFF ;
SHLB *,#* 19 3 I1 1 00 0000FF0F ;
SHLB *,* 19 3 I1 1 00 0000FFFF ;
SHLL *,#* 0D 3 I1 1 00 0000FF0F ;
SHLL *,* 0D 3 I1 1 00 0000FFFF ;
SHR *,#* 08 3 I1 1 00 0000FF0F ;word align
SHR *,* 08 3 I1 1 00 0000FFFF ;word align
SHRB *,#* 18 3 I1 1 00 0000FF0F ;byte align
SHRB *,* 18 3 I1 1 00 0000FFFF ;byte align
SHRL *,#* 0C 3 I1 1 00 0000FF0F ;long align
SHRL *,* 0C 3 I1 1 00 0000FFFF ;long align
SHRA *,#* 0A 3 I1 1 00 0000FF0F ;word align
SHRA *,* 0A 3 I1 1 00 0000FFFF ;word align
SHRAB *,#* 1A 3 I1 1 00 0000FF0F ;byte align
SHRAB *,* 1A 3 I1 1 00 0000FFFF ;byte align
SHRAL *,#* 0E 3 I1 1 00 0000FF0F ;long align
SHRAL *,* 0E 3 I1 1 00 0000FFFF ;long align
SETC "" F9 1 NOP 1 00 00000000 ;
SKIP "" 0000 2 NOP 1 00 00000000 ;
SKIP * 00 2 I1 1 00 00000000 ;
ST *,[*]+ C2 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ST *,[*] C2 3 I1 1 00 0000FFFe ;1st arg must be even
ST *,*[*] C3 5 I6 1 00 FFFFFFFe ;1st,3rd must be even
ST *,* C301 5 I2 1 00 00000000 ;2nd arg may be far
STB *,[*]+ C6 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
STB *,[*] C6 3 I1 1 00 0000FFFe ;1st arg must be even
STB *,*[*] C7 5 I6 1 00 FFFFFFFe ;1st,3rd must be even
STB *,* C701 5 I2 1 00 00000000 ;2nd arg may be far
TRAP "" F7 1 NOP 1 00 00000000 ;
TIJMP *,[*],#* E2 4 I8 2 00 00FEFEFF ;
XCH *,*[*] 0B 5 I6 2 00 00FeFFFe ;1st,3rd must be even
XCH *,* 0B01 5 I2 2 0C 00000000 ;2nd arg may be far
XCHB *,*[*] 1B 5 I6 2 00 00FFFFFF ;
XCHB *,* 1B01 5 I2 2 0C 00000000 ;2nd arg may be far
XOR *,[*]+ 86 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
XOR *,[*] 86 3 I1 1 00 0000FFFe ;1st arg must be even
XOR *,*[*] 87 5 I6 1 00 00FeFFFe ;1st,3rd must be even
XOR *,#* 85 4 I1 1 00 00FeFFFF ;1st arg must be even
XOR *,* 8701 5 I2 1 00 00000000 ;2nd arg may be far
XORB *,[*]+ 96 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
XORB *,[*] 96 3 I1 1 00 0000FFFe ;1st arg must be even
XORB *,*[*] 97 5 I6 1 00 00FFFFFF ;
XORB *,#* 95 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
XORB *,* 9701 5 I2 1 00 00000000 ;2nd arg may be far

2865
trunk/XSource/bin/TASMMAN.HTM Normal file
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File diff suppressed because it is too large Load Diff

2989
trunk/XSource/bin/TASMTABS.HTM Normal file
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File diff suppressed because it is too large Load Diff

251
trunk/XSource/bin/TEST05.ASM Normal file
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@@ -0,0 +1,251 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test05.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 6805
;
.org 0
bit3 .equ 3
data .equ $12
.block $46
addz .equ $46
.org $1007
addr:
ADC #data ;A9 2 NOP 1
ADC ,X ;F9 1 NOP 1
ADC addr,X ;D9 3 MZERO 1
ADC addz,X ;D9 3 MZERO 1
ADC addr ;C9 3 MZERO 1
ADC addz ;C9 3 MZERO 1
ADD #data ;AB 2 NOP 1
ADD ,X ;FB 1 NOP 1
ADD addr,X ;DB 3 MZERO 1
ADD addz,X ;DB 3 MZERO 1
ADD addr ;CB 3 MZERO 1
ADD addz ;CB 3 MZERO 1
AND #data ;A4 2 NOP 1
AND ,X ;F4 1 NOP 1
AND addr,X ;D4 3 MZERO 1
AND addz,X ;D4 3 MZERO 1
AND addr ;C4 3 MZERO 1
AND addz ;C4 3 MZERO 1
ASLA ;48 1 NOP 1
ASLX ;58 1 NOP 1
ASL ,X ;78 1 NOP 1
ASL addz,X ;68 2 NOP 1
ASL addz ;38 2 NOP 1
ASRA ;47 1 NOP 1
ASRX ;57 1 NOP 1
ASR ,X ;77 1 NOP 1
ASR addz,X ;37 2 NOP 1
ASR addz ;37 2 NOP 1
loop1:
BCC loop1 ;24 2 R1 1
BCS loop1 ;25 2 R1 1
BEQ loop1 ;27 2 R1 1
BHCC loop1 ;28 2 R1 1
BHCS loop1 ;29 2 R1 1
BHI loop1 ;22 2 R1 1
BHS loop1 ;24 2 R1 1
BIH loop1 ;2F 2 R1 1
BIL loop1 ;2E 2 R1 1
BIT #data ;A5 2 NOP 1
BIT ,X ;F5 1 NOP 1
BIT addr,X ;D5 3 MZERO 1
BIT addz,X ;C5 3 MZERO 1
BIT addr ;C5 3 MZERO 1
BIT addz ;C5 3 MZERO 1
BLO loop1 ;25 2 R1 1
BLS loop1 ;23 2 R1 1
BMC loop1 ;2C 2 R1 1
BMI loop1 ;2B 2 R1 1
BMS loop1 ;2D 2 R1 1
BNE loop1 ;26 2 R1 1
BPL loop1 ;2A 2 R1 1
BRA loop1 ;20 2 R1 1
BRN loop1 ;21 2 R1 1
BSR loop1 ;AD 2 R1 1
BRCLR bit3,addz,loop1 ;01 3 MBIT 1
BRSET bit3,addz,loop1 ;00 3 MBIT 1
BCLR bit3,addz ;11 2 MBIT 1
BSET bit3,addz ;10 2 MBIT 1
CLC ;98 1 NOP 1
CLI ;9A 1 NOP 1
CLRA ;4F 1 NOP 1
CLRX ;5F 1 NOP 1
CLR ,X ;7F 1 NOP 1
CLR addz,X ;6F 2 NOP 1
CLR addz ;3F 2 NOP 1
CMP #data ;A1 2 NOP 1
CMP ,X ;F1 1 NOP 1
CMP addr,X ;D1 3 MZERO 1
CMP addz,X ;D1 3 MZERO 1
CMP addr ;C1 3 MZERO 1
CMP addz ;C1 3 MZERO 1
COMA ;43 1 NOP 1
COMX ;53 1 NOP 1
COM ,X ;73 1 NOP 1
COM addz,X ;63 2 NOP 1
COM addz ;33 2 NOP 1
CPX #data ;A3 2 NOP 1
CPX ,X ;F3 1 NOP 1
CPX addr,X ;D3 3 MZERO 1
CPX addz,X ;D3 3 MZERO 1
CPX addr ;C3 3 MZERO 1
CPX addz ;C3 3 MZERO 1
DECA ;4A 1 NOP 1
DECX ;5A 1 NOP 1
DEX ;5A 1 NOP 1
DEC ,X ;7A 1 NOP 1
DEC addz,X ;6A 2 NOP 1
DEC addz ;3A 2 NOP 1
EOR #data ;A8 2 NOP 1
EOR ,X ;F8 1 NOP 1
EOR addr,X ;D8 3 MZERO 1
EOR addz,X ;D8 3 MZERO 1
EOR addr ;C8 3 MZERO 1
EOR addz ;C8 3 MZERO 1
INCA ;4C 1 NOP 1
INCX ;5C 1 NOP 1
INX ;5C 1 NOP 1
INC ,X ;7C 1 NOP 1
INC addz,X ;6C 2 NOP 1
INC addz ;3C 2 NOP 1
JMP ,X ;FC 1 NOP 1
JMP addr,X ;DC 3 MZERO 1
JMP addz,X ;DC 3 MZERO 1
JMP addr ;CC 3 MZERO 1
JMP addz ;CC 3 MZERO 1
JSR ,X ;FD 1 NOP 1
JSR addr,X ;DD 3 MZERO 1
JSR addz,X ;DD 3 MZERO 1
JSR addr ;CD 3 MZERO 1
JSR addz ;CD 3 MZERO 1
LDA #data ;A6 2 NOP 1
LDA ,X ;F6 1 NOP 1
LDA addr,X ;D6 3 MZERO 1
LDA addz,X ;D6 3 MZERO 1
LDA addr ;C6 3 MZERO 1
LDA addz ;C6 3 MZERO 1
LDX #data ;AE 2 NOP 1
LDX ,X ;FE 1 NOP 1
LDX addr,X ;DE 3 MZERO 1
LDX addz,X ;DE 3 MZERO 1
LDX addr ;CE 3 MZERO 1
LDX addz ;CE 3 MZERO 1
LSLA ;48 1 NOP 1
LSLX ;58 1 NOP 1
LSL ,X ;78 1 NOP 1
LSL addz,X ;68 2 NOP 1
LSL addz ;38 2 NOP 1
LSRA ;44 1 NOP 1
LSRX ;54 1 NOP 1
LSR ,X ;74 1 NOP 1
LSR addz,X ;64 2 NOP 1
LSR addz ;34 2 NOP 1
NEGA ;40 1 NOP 1
NEGX ;50 1 NOP 1
NEG ,X ;70 1 NOP 1
NEG addz,X ;60 2 NOP 1
NEG addz ;30 2 NOP 1
NOP ;9D 1 NOP 1
ORA #data ;AA 2 NOP 1
ORA ,X ;FA 1 NOP 1
ORA addr,X ;DA 3 MZERO 1
ORA addz,X ;DA 3 MZERO 1
ORA addr ;CA 3 MZERO 1
ORA addz ;CA 3 MZERO 1
ROLA ;49 1 NOP 1
ROLX ;59 1 NOP 1
ROL ,X ;79 1 NOP 1
ROL addz,X ;69 2 NOP 1
ROL addz ;39 2 NOP 1
RORA ;46 1 NOP 1
RORX ;56 1 NOP 1
ROR ,X ;76 1 NOP 1
ROR addz,X ;66 2 NOP 1
ROR addz ;36 2 NOP 1
RSP ;9C 1 NOP 1
RTI ;80 1 NOP 1
RTS ;81 1 NOP 1
SBC #data ;A2 2 NOP 1
SBC ,X ;F2 1 NOP 1
SBC addr,X ;D2 3 MZERO 1
SBC addz,X ;D2 3 MZERO 1
SBC addr ;C2 3 MZERO 1
SBC addz ;C2 3 MZERO 1
SEC ;99 1 NOP 1
SEI ;9B 1 NOP 1
STA ,X ;F7 1 NOP 1
STA addr,X ;D7 3 MZERO 1
STA addz,X ;D7 3 MZERO 1
STA addr ;C7 3 MZERO 1
STA addz ;C7 3 MZERO 1
STOP ;8E 1 NOP 1
STX ,X ;FF 1 NOP 1
STX addr,X ;DF 3 MZERO 1
STX addz,X ;DF 3 MZERO 1
STX addr ;CF 3 MZERO 1
STX addz ;CF 3 MZERO 1
SUB #data ;A0 2 NOP 1
SUB ,X ;F0 1 NOP 1
SUB addr,X ;D0 3 MZERO 1
SUB addz,X ;D0 3 MZERO 1
SUB addr ;C0 3 MZERO 1
SUB addz ;C0 3 MZERO 1
SWI ;83 1 NOP 1
TAX ;97 1 NOP 1
TSTA ;4D 1 NOP 1
TSTX ;5D 1 NOP 1
TST ,X ;7D 1 NOP 1
TST addz,X ;6D 2 NOP 1
TST addz ;3D 2 NOP 1
TXA ;9F 1 NOP 1
WAIT ;8F 1 NOP 1
.end

328
trunk/XSource/bin/TEST3210.ASM Normal file
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@@ -0,0 +1,328 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test3210.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: TMS32010
;
.org 100h
shift .equ 4
shift0 .equ 0
addr .equ 12h
port .equ 2
arp .equ 1
ar .equ 1
const .equ 34h
const1 .equ 1h
ABS ;7F88 2 NOP 1
ADD *+,shift,arp ;00A0 2 T1 1 8 0F00
ADD *-,shift,arp ;0090 2 T1 1 8 0F00
ADD *,shift,arp ;0080 2 T1 1 8 0F00
ADD *+,shift ;00A8 2 T1 1 8 0F00
ADD *-,shift ;0098 2 T1 1 8 0F00
ADD *,shift ;0088 2 T1 1 8 0F00
ADD *+ ;00A8 2 NOP 1
ADD *- ;0098 2 NOP 1
ADD * ;0088 2 NOP 1
ADD addr,shift ;0000 2 TDMA 1 8 0F00
ADD addr ;0000 2 T1 1 0 007F
ADDH *+,arp ;60A0 2 T1 1 0 01
ADDH *-,arp ;6090 2 T1 1 0 01
ADDH *,arp ;6080 2 T1 1 0 01
ADDH *+ ;60A8 2 NOP 1
ADDH *- ;6098 2 NOP 1
ADDH * ;6088 2 NOP 1
ADDH addr ;6000 2 T1 1 0 007F
ADDS *+,arp ;61A0 2 T1 1 0 01
ADDS *-,arp ;6190 2 T1 1 0 01
ADDS *,arp ;6180 2 T1 1 0 01
ADDS *+ ;61A8 2 NOP 1
ADDS *- ;6198 2 NOP 1
ADDS * ;6188 2 NOP 1
ADDS addr ;6100 2 T1 1 0 007F
AND *+,arp ;79A0 2 T1 1 0 01
AND *-,arp ;7990 2 T1 1 0 01
AND *,arp ;7980 2 T1 1 0 01
AND *+ ;79A8 2 NOP 1
AND *- ;7998 2 NOP 1
AND * ;7988 2 NOP 1
AND addr ;7900 2 T1 1 0 7F
APAC ;7F8F 2 NOP 1
loop1:
B loop1 ;F900 4 SWAP 1
BANZ loop1 ;F400 4 SWAP 1
BGEZ loop1 ;FD00 4 SWAP 1
BGZ loop1 ;FC00 4 SWAP 1
BIOZ loop1 ;F600 4 SWAP 1
BLEZ loop1 ;FB00 4 SWAP 1
BLZ loop1 ;FA00 4 SWAP 1
BNZ loop1 ;FE00 4 SWAP 1
BV loop1 ;F500 4 SWAP 1
BZ loop1 ;FF00 4 SWAP 1
CALA ;7F8C 2 NOP 1
CALL loop1 ;F800 4 SWAP 1
DINT ;7F81 2 NOP 1
DMOV *+,arp ;69A0 2 T1 1 0 01
DMOV *-,arp ;6990 2 T1 1 0 01
DMOV *,arp ;6980 2 T1 1 0 01
DMOV *+ ;69A8 2 NOP 1
DMOV *- ;6998 2 NOP 1
DMOV * ;6988 2 NOP 1
DMOV addr ;6900 2 T1 1 0 007F
EINT ;7F82 2 NOP 1
IN *+,port ,arp ;40A0 2 T1 1 8 0700
IN *-,port ,arp ;4090 2 T1 1 8 0700
IN * ,port ,arp ;4080 2 T1 1 8 0700
IN *+,port ;40A8 2 T1 1 8 0700
IN *-,port ;4098 2 T1 1 8 0700
IN * ,port ;4088 2 T1 1 8 0700
IN addr,port ;4000 2 TDMA 1 8 0700
LAC *+,shift,arp ;20A0 2 T1 1 8 0F00
LAC *-,shift,arp ;2090 2 T1 1 8 0F00
LAC *,shift,arp ;2080 2 T1 1 8 0F00
LAC *+,shift ;20A8 2 T1 1 8 0F00
LAC *-,shift ;2098 2 T1 1 8 0F00
LAC *,shift ;2088 2 T1 1 8 0F00
LAC *+ ;20A8 2 NOP 1
LAC *- ;2098 2 NOP 1
LAC * ;2088 2 NOP 1
LAC addr,shift ;2000 2 TDMA 1 8 0F00
LAC addr ;2000 2 T1 1 0 007F
LACK const ;7E00 2 T1 1 0 00FF
LAR ar,*+,arp ;38A0 2 TAR 1 0 0001
LAR ar,*-,arp ;3890 2 TAR 1 0 0001
LAR ar,*,arp ;3880 2 TAR 1 0 0001
LAR ar,*+ ;38A8 2 TAR 1 0 0001
LAR ar,*- ;3898 2 TAR 1 0 0001
LAR ar,* ;3888 2 TAR 1 0 0001
LAR ar, addr ;3800 2 TAR 1 0 007F
LARK ar,const ;7000 2 TAR 1 0 00FF
LARP const1 ;6880 2 T1 1 0 0001
LDP *+,arp ;6FA0 2 T1 1 0 01
LDP *-,arp ;6F90 2 T1 1 0 01
LDP *,arp ;6F80 2 T1 1 0 01
LDP *+ ;6FA8 2 NOP 1
LDP *- ;6F98 2 NOP 1
LDP * ;6F88 2 NOP 1
LDP addr ;6F00 2 T1 1 0 007F
LDPK const1 ;6E00 2 T1 1 0 01
LST *+,arp ;7BA0 2 T1 1 0 01
LST *-,arp ;7B90 2 T1 1 0 01
LST *,arp ;7B80 2 T1 1 0 01
LST *+ ;7BA8 2 NOP 1
LST *- ;7B98 2 NOP 1
LST * ;7B88 2 NOP 1
LST addr ;7B00 2 T1 1 0 007F
LT *+,arp ;6AA0 2 T1 1 0 01
LT *-,arp ;6A90 2 T1 1 0 01
LT *,arp ;6A80 2 T1 1 0 01
LT *+ ;6AA8 2 NOP 1
LT *- ;6A98 2 NOP 1
LT * ;6A88 2 NOP 1
LT addr ;6A00 2 T1 1 0 007F
LTA *+,arp ;6CA0 2 T1 1 0 01
LTA *-,arp ;6C90 2 T1 1 0 01
LTA *,arp ;6C80 2 T1 1 0 01
LTA *+ ;6CA8 2 NOP 1
LTA *- ;6C98 2 NOP 1
LTA * ;6C88 2 NOP 1
LTA addr ;6C00 2 T1 1 0 007F
LTD *+,arp ;6BA0 2 T1 1 0 01
LTD *-,arp ;6B90 2 T1 1 0 01
LTD *,arp ;6B80 2 T1 1 0 01
LTD *+ ;6BA8 2 NOP 1
LTD *- ;6B98 2 NOP 1
LTD * ;6B88 2 NOP 1
LTD addr ;6B00 2 T1 1 0 007F
MAR *+,arp ;68A0 2 T1 1 0 01
MAR *-,arp ;6890 2 T1 1 0 01
MAR *,arp ;6880 2 T1 1 0 01
MAR *+ ;68A8 2 NOP 1
MAR *- ;6898 2 NOP 1
MAR * ;6888 2 NOP 1
MAR addr ;6800 2 T1 1 0 007F
MPY *+,arp ;6DA0 2 T1 1 0 01
MPY *-,arp ;6D90 2 T1 1 0 01
MPY *,arp ;6D80 2 T1 1 0 01
MPY *+ ;6DA8 2 NOP 1
MPY *- ;6D98 2 NOP 1
MPY * ;6D88 2 NOP 1
MPY addr ;6D00 2 T1 1 0 007F
MPYK const ;8000 2 T1 1 0 1FFF
NOP ;7F80 2 NOP 1
OR *+,arp ;7AA0 2 T1 1 0 01
OR *-,arp ;7A90 2 T1 1 0 01
OR *,arp ;7A80 2 T1 1 0 01
OR *+ ;7AA8 2 NOP 1
OR *- ;7A98 2 NOP 1
OR * ;7A88 2 NOP 1
OR addr ;7A00 2 T1 1 0 007F
OUT *+,port,arp ;48A0 2 T1 1 8 0700
OUT *-,port,arp ;4890 2 T1 1 8 0700
OUT *, port,arp ;4880 2 T1 1 8 0700
OUT *+,port ;48A8 2 T1 1 8 0700
OUT *-,port ;4898 2 T1 1 8 0700
OUT *, port ;4888 2 T1 1 8 0700
OUT addr,port ;4800 2 TDMA 1 8 0700
PAC ;7F8E 2 NOP 1
POP ;7F9D 2 NOP 1
PUSH ;7F9C 2 NOP 1
RET ;7F8D 2 NOP 1
ROVM ;7F8A 2 NOP 1
;Note that shift count can only be 0,1, or 4.
;Mask also allows 5. Beware.
SACH *+,shift,arp ;58A0 2 T1 1 8 0500
SACH *-,shift,arp ;5890 2 T1 1 8 0500
SACH *, shift,arp ;5880 2 T1 1 8 0500
SACH *+,shift ;58A8 2 T1 1 8 0500
SACH *-,shift ;5898 2 T1 1 8 0500
SACH *, shift ;5888 2 T1 1 8 0500
SACH *+ ;58A8 2 NOP 1
SACH *- ;5898 2 NOP 1
SACH * ;5888 2 NOP 1
SACH addr,shift ;5800 2 TDMA 1 8 0500
SACH addr ;5800 2 T1 1 0 007F
; Shift count must be zero for SACL
SACL *+,shift0,arp ;50A0 2 T1 1 8 0000
SACL *-,shift0,arp ;5090 2 T1 1 8 0000
SACL *, shift0,arp ;5080 2 T1 1 8 0000
SACL *+,shift0 ;50A8 2 T1 1 8 0000
SACL *-,shift0 ;5098 2 T1 1 8 0000
SACL *, shift0 ;5088 2 T1 1 8 0000
SACL *+ ;50A8 2 NOP 1
SACL *- ;5098 2 NOP 1
SACL * ;5088 2 NOP 1
SACL addr,shift0 ;5000 2 TDMA 1 8 0000
SACL addr ;5000 2 T1 1 0 007F
SAR ar,*+,arp ;30A0 2 TAR 1 0 0001
SAR ar,*-,arp ;3090 2 TAR 1 0 0001
SAR ar,*,arp ;3080 2 TAR 1 0 0001
SAR ar,*+ ;30A8 2 TAR 1 0 0001
SAR ar,*- ;3098 2 TAR 1 0 0001
SAR ar,* ;3088 2 TAR 1 0 0001
SAR ar,addr ;3000 2 TAR 1 0 007F
SOVM ;7F8B 2 NOP 1
SPAC ;7F90 2 NOP 1
SST *+,arp ;7CA0 2 T1 1 0 0001
SST *-,arp ;7C90 2 T1 1 0 0001
SST *,arp ;7C80 2 T1 1 0 0001
SST *+ ;7CA8 2 NOP 1
SST *- ;7C98 2 NOP 1
SST * ;7C88 2 NOP 1
SST addr ;7C00 2 T1 1 0 007F
SUB *+,shift,arp ;10A0 2 T1 1 8 0F00
SUB *-,shift,arp ;1090 2 T1 1 8 0F00
SUB *, shift,arp ;1080 2 T1 1 8 0F00
SUB *+,shift ;10A8 2 T1 1 8 0F00
SUB *-,shift ;1098 2 T1 1 8 0F00
SUB *, shift ;1088 2 T1 1 8 0F00
SUB *+ ;10A8 2 NOP 1
SUB *- ;1098 2 NOP 1
SUB * ;1088 2 NOP 1
SUB addr,shift ;1000 2 TDMA 1 8 0F00
SUB addr ;1000 2 T1 1 0 007F
SUBC *+,arp ;64A0 2 T1 1 0 01
SUBC *-,arp ;6490 2 T1 1 0 01
SUBC *,arp ;6480 2 T1 1 0 01
SUBC *+ ;64A8 2 NOP 1
SUBC *- ;6498 2 NOP 1
SUBC * ;6488 2 NOP 1
SUBC addr ;6400 2 T1 1 0 007F
SUBH *+,arp ;62A0 2 T1 1 0 01
SUBH *-,arp ;6290 2 T1 1 0 01
SUBH *,arp ;6280 2 T1 1 0 01
SUBH *+ ;62A8 2 NOP 1
SUBH *- ;6298 2 NOP 1
SUBH * ;6288 2 NOP 1
SUBH addr ;6200 2 T1 1 0 007F
SUBS *+,arp ;63A0 2 T1 1 0 01
SUBS *-,arp ;6390 2 T1 1 0 01
SUBS *,arp ;6380 2 T1 1 0 01
SUBS *+ ;63A8 2 NOP 1
SUBS *- ;6398 2 NOP 1
SUBS * ;6388 2 NOP 1
SUBS addr ;6300 2 T1 1 0 007F
TBLR *+,arp ;67A0 2 T1 1 0 01
TBLR *-,arp ;6790 2 T1 1 0 01
TBLR *,arp ;6780 2 T1 1 0 01
TBLR *+ ;67A8 2 NOP 1
TBLR *- ;6798 2 NOP 1
TBLR * ;6788 2 NOP 1
TBLR addr ;6700 2 T1 1 0 007F
TBLW *+,arp ;7DA0 2 T1 1 0 01
TBLW *-,arp ;7D90 2 T1 1 0 01
TBLW *,arp ;7D80 2 T1 1 0 01
TBLW *+ ;7DA8 2 NOP 1
TBLW *- ;7D98 2 NOP 1
TBLW * ;7D88 2 NOP 1
TBLW addr ;7D00 2 T1 1 0 007F
XOR *+,arp ;78A0 2 T1 1 0 01
XOR *-,arp ;7890 2 T1 1 0 01
XOR *,arp ;7880 2 T1 1 0 01
XOR *+ ;78A8 2 NOP 1
XOR *- ;7898 2 NOP 1
XOR * ;7888 2 NOP 1
XOR addr ;7800 2 T1 1 0 007F
ZAC ;7F89 2 NOP 1
ZALH *+,arp ;65A0 2 T1 1 0 01
ZALH *-,arp ;6590 2 T1 1 0 01
ZALH *,arp ;6580 2 T1 1 0 01
ZALH *+ ;65A8 2 NOP 1
ZALH *- ;6598 2 NOP 1
ZALH * ;6588 2 NOP 1
ZALH addr ;6500 2 T1 1 0 007F
ZALS *+,arp ;66A0 2 T1 1 0 01
ZALS *-,arp ;6690 2 T1 1 0 01
ZALS *,arp ;6680 2 T1 1 0 01
ZALS *+ ;66A8 2 NOP 1
ZALS *- ;6698 2 NOP 1
ZALS * ;6688 2 NOP 1
ZALS addr ;6600 2 T1 1 0 007F
.end

1363
trunk/XSource/bin/TEST3225.ASM Normal file
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279
trunk/XSource/bin/TEST48.ASM Normal file
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test48.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 8048
;
label1 .equ 12H
ADD A,R0
ADD A,R1
ADD A,R2
ADD A,R3
ADD A,R4
ADD A,R5
ADD A,R6
ADD A,R7
ADD A,@R0
ADD A,@R1
ADD A,#label1
ADDC A,R0
ADDC A,R1
ADDC A,R2
ADDC A,R3
ADDC A,R4
ADDC A,R5
ADDC A,R6
ADDC A,R7
ADDC A,@R0
ADDC A,@R1
ADDC A,#label1
ANL A,R0
ANL A,R1
ANL A,R2
ANL A,R3
ANL A,R4
ANL A,R5
ANL A,R6
ANL A,R7
ANL A,@R0
ANL A,@R1
ANL A,#label1
ANL BUS,#label1
ANL P1,#label1
ANL P2,#label1
ANLD P4,A
ANLD P5,A
ANLD P6,A
ANLD P7,A
CALL label1
CLR A
CLR C
CLR F0
CLR F1
CPL A
CPL C
CPL F0
CPL F1
DA A
DEC A
DEC R0
DEC R1
DEC R2
DEC R3
DEC R4
DEC R5
DEC R6
DEC R7
DIS I
DIS TCNTI
DJNZ R0,label1
DJNZ R1,label1
DJNZ R2,label1
DJNZ R3,label1
DJNZ R4,label1
DJNZ R5,label1
DJNZ R6,label1
DJNZ R7,label1
EN DMA
EN FLAGS
EN I
EN TCNTI
ENT0 CLK
IN A,DBB
IN A,P0
IN A,P1
IN A,P2
INC A
INC R0
INC R1
INC R2
INC R3
INC R4
INC R5
INC R6
INC R7
INC @R0
INC @R1
INS A,BUS
JB0 label1
JB1 label1
JB2 label1
JB3 label1
JB4 label1
JB5 label1
JB6 label1
JB7 label1
JMP label1
JC label1
JF0 label1
JF1 label1
JNC label1
JNI label1
JNIBF label1
JNT0 label1
JNT1 label1
JNZ label1
JOBF label1
JTF label1
JT0 label1
JT1 label1
JZ label1
JMPP @A
MOV A,PSW
MOV A,R0
MOV A,R1
MOV A,R2
MOV A,R3
MOV A,R4
MOV A,R5
MOV A,R6
MOV A,R7
MOV A,T
MOV A,@R0
MOV A,@R1
MOV A,#label1
MOV PSW,A
MOV R0,A
MOV R1,A
MOV R2,A
MOV R3,A
MOV R4,A
MOV R5,A
MOV R6,A
MOV R7,A
MOV R0,#label1
MOV R1,#label1
MOV R2,#label1
MOV R3,#label1
MOV R4,#label1
MOV R5,#label1
MOV R6,#label1
MOV R7,#label1
MOV STS,A
MOV T,A
MOV @R0,A
MOV @R1,A
MOV @R0,#label1
MOV @R1,#label1
MOVD A,P4
MOVD A,P5
MOVD A,P6
MOVD A,P7
MOVD P4,A
MOVD P5,A
MOVD P6,A
MOVD P7,A
MOVP A,@A
MOVP3 A,@A
MOVX A,@R0
MOVX A,@R1
MOVX @R0,A
MOVX @R1,A
NOP
ORL A,R0
ORL A,R1
ORL A,R2
ORL A,R3
ORL A,R4
ORL A,R5
ORL A,R6
ORL A,R7
ORL A,@R0
ORL A,@R1
ORL A,#label1
ORL BUS,#label1
ORL P1,#label1
ORL P2,#label1
ORLD P4,A
ORLD P5,A
ORLD P6,A
ORLD P7,A
OUTL BUS,A
OUT DBB,A
OUTL P0,A
OUTL P1,A
OUTL P2,A
RAD
RET
RETI
RETR
RL A
RLC A
RR A
RRC A
SEL AN0
SEL AN1
SEL MB0
SEL MB1
SEL RB0
SEL RB1
STOP TCNT
STRT CNT
STRT T
SWAP A
XCH A,R0
XCH A,R1
XCH A,R2
XCH A,R3
XCH A,R4
XCH A,R5
XCH A,R6
XCH A,R7
XCH A,@R0
XCH A,@R1
XCHD A,@R0
XCHD A,@R1
XRL A,R0
XRL A,R1
XRL A,R2
XRL A,R3
XRL A,R4
XRL A,R5
XRL A,R6
XRL A,R7
XRL A,@R0
XRL A,@R1
XRL A,#label1
.end

297
trunk/XSource/bin/TEST51.ASM Normal file
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test51.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 8051
;
.AVSYM
labimm: .EQU 56h
lab2: .EQU 12h
lab3: .EQU 1234h
lab5: .EQU 0feh
labbt_1: .EQU 34h
bit .equ 81h
ACALL lab4 ;11 2 JMP 1
lab4:
ADD A,R0 ;28 1 NOP 1
ADD A,R1 ;29 1 NOP 1
ADD A,R2 ;2A 1 NOP 1
ADD A,R3 ;2B 1 NOP 1
ADD A,R4 ;2C 1 NOP 1
ADD A,R5 ;2D 1 NOP 1
ADD A,R6 ;2E 1 NOP 1
ADD A,R7 ;2F 1 NOP 1
ADD A,@R0 ;26 1 NOP 1
ADD A,@R1 ;27 1 NOP 1
ADD A,#labimm ;24 2 NOP 1
ADD A,lab2 ;25 2 NOP 1
ADDC A,R0 ;38 1 NOP 1
ADDC A,R1 ;39 1 NOP 1
ADDC A,R2 ;3A 1 NOP 1
ADDC A,R3 ;3B 1 NOP 1
ADDC A,R4 ;3C 1 NOP 1
ADDC A,R5 ;3D 1 NOP 1
ADDC A,R6 ;3E 1 NOP 1
ADDC A,R7 ;3F 1 NOP 1
ADDC A,@R0 ;36 1 NOP 1
ADDC A,@R1 ;37 1 NOP 1
ADDC A,#labimm ;34 2 NOP 1
ADDC A,lab2 ;35 2 NOP 1
AJMP jlab ;01 2 JMP 1
ANL A,R0 ;58 1 NOP 1
ANL A,R1 ;59 1 NOP 1
ANL A,R2 ;5A 1 NOP 1
ANL A,R3 ;5B 1 NOP 1
ANL A,R4 ;5C 1 NOP 1
ANL A,R5 ;5D 1 NOP 1
ANL A,R6 ;5E 1 NOP 1
ANL A,R7 ;5F 1 NOP 1
ANL A,@R0 ;56 1 NOP 1
ANL A,@R1 ;57 1 NOP 1
ANL A,#labimm
ANL A,lab2
ANL C,/bit
ANL C,bit
ANL lab2,A
ANL lab2,#labimm
CJNE A,#labimm,jlab ;b4 3 CR 1
CJNE A,lab2,jlab ;b5 3 CR 1
CJNE R0,#labimm,jlab ;b8 3 CR 1
CJNE R1,#labimm,jlab ;b9 3 CR 1
CJNE R2,#labimm,jlab ;ba 3 CR 1
CJNE R3,#labimm,jlab ;bb 3 CR 1
CJNE R4,#labimm,jlab ;bc 3 CR 1
CJNE R5,#labimm,jlab ;bd 3 CR 1
CJNE R6,#labimm,jlab ;be 3 CR 1
CJNE R7,#labimm,jlab ;bf 3 CR 1
CJNE @R0,#labimm,jlab ;b6 3 CR 1
CJNE @R1,#labimm,jlab ;b7 3 CR 1
CLR A ;e4 1 NOP 1
CLR C ;c3 1 NOP 1
CLR bit
CPL A ;f4 1 NOP 1
CPL C ;b3 1 NOP 1
CPL bit
DA A ;d4 1 NOP 1
DEC A ;14 1 NOP 1
DEC R0 ;18 1 NOP 1
DEC R1 ;19 1 NOP 1
DEC R2 ;1A 1 NOP 1
DEC R3 ;1B 1 NOP 1
DEC R4 ;1C 1 NOP 1
DEC R5 ;1D 1 NOP 1
DEC R6 ;1E 1 NOP 1
DEC R7 ;1F 1 NOP 1
DEC @R0 ;16 1 NOP 1
DEC @R1 ;17 1 NOP 1
DEC lab2 ;15 2 NOP 1
DIV AB ;84 1 NOP 1
DJNZ R0,jlab ;d8 2 NOP 1
DJNZ R1,jlab ;d9 2 NOP 1
DJNZ R2,jlab ;dA 2 NOP 1
DJNZ R3,jlab ;dB 2 NOP 1
DJNZ R4,jlab ;dC 2 NOP 1
DJNZ R5,jlab ;dD 2 NOP 1
DJNZ R6,jlab ;dE 2 NOP 1
DJNZ R7,jlab ;dF 2 NOP 1
DJNZ lab2,jlab ;d5 3 CR 1
INC A ;04 1 NOP 1
INC R0 ;08 1 NOP 1
INC R1 ;09 1 NOP 1
INC R2 ;0A 1 NOP 1
INC R3 ;0B 1 NOP 1
INC R4 ;0C 1 NOP 1
INC R5 ;0D 1 NOP 1
INC R6 ;0E 1 NOP 1
INC R7 ;0F 1 NOP 1
INC @R0 ;06 1 NOP 1
INC @R1 ;07 1 NOP 1
INC DPTR ;a3 1 NOP 1
INC lab2 ;05 2 NOP 1
jlab:
JB labbt_1,jlab ;20 3 CR 1
JBC labbt_1,jlab ;10 3 CR 1
JC jlab ;40 2 R1 1
JMP @A+DPTR ;73 1 NOP 1
JNB labbt_1,jlab ;30 3 CR 1
JNC jlab ;50 2 R1 1
JNZ jlab ;70 2 R1 1
JZ jlab ;60 2 R1 1
LCALL lab3 ;12 3 SWAP 1
LJMP lab3 ;02 3 SWAP 1
MOV A,R0 ;e8 1 NOP 1
MOV A,R1 ;e9 1 NOP 1
MOV A,R2 ;eA 1 NOP 1
MOV A,R3 ;eB 1 NOP 1
MOV A,R4 ;eC 1 NOP 1
MOV A,R5 ;eD 1 NOP 1
MOV A,R6 ;eE 1 NOP 1
MOV A,R7 ;eF 1 NOP 1
MOV A,@R0 ;e6 1 NOP 1
MOV A,@R1 ;e7 1 NOP 1
MOV A,#labimm ;74 2 NOP 1
MOV A,lab2 ;e5 2 NOP 1
MOV C,bit ;a2 2 NOP 1
MOV DPTR,#labimm ;90 3 SWAP 1
MOV R0,A ;f8 1 NOP 1
MOV R1,A ;f9 1 NOP 1
MOV R2,A ;fA 1 NOP 1
MOV R3,A ;fB 1 NOP 1
MOV R4,A ;fC 1 NOP 1
MOV R5,A ;fD 1 NOP 1
MOV R6,A ;fE 1 NOP 1
MOV R7,A ;fF 1 NOP 1
MOV R0,#labimm ;78 2 NOP 1
MOV R1,#labimm ;79 2 NOP 1
MOV R2,#labimm ;7A 2 NOP 1
MOV R3,#labimm ;7B 2 NOP 1
MOV R4,#labimm ;7C 2 NOP 1
MOV R5,#labimm ;7D 2 NOP 1
MOV R6,#labimm ;7E 2 NOP 1
MOV R7,#labimm ;7F 2 NOP 1
MOV R0,lab2 ;a8 2 NOP 1
MOV R1,lab2 ;a9 2 NOP 1
MOV R2,lab2 ;aA 2 NOP 1
MOV R3,lab2 ;aB 2 NOP 1
MOV R4,lab2 ;aC 2 NOP 1
MOV R5,lab2 ;aD 2 NOP 1
MOV R6,lab2 ;aE 2 NOP 1
MOV R7,lab2 ;aF 2 NOP 1
MOV @R0,A ;f6 1 NOP 1
MOV @R1,A ;f7 1 NOP 1
MOV @R0,#labimm ;76 2 NOP 1
MOV @R1,#labimm ;77 2 NOP 1
MOV @R0,lab2 ;a6 2 NOP 1
MOV @R1,lab2 ;a7 2 NOP 1
MOV lab2,A ;f5 2 NOP 1
MOV bit,C ;92 2 NOP 1
MOV lab2,R0 ;88 2 NOP 1
MOV lab2,R1 ;89 2 NOP 1
MOV lab2,R2 ;8A 2 NOP 1
MOV lab2,R3 ;8B 2 NOP 1
MOV lab2,R4 ;8C 2 NOP 1
MOV lab2,R5 ;8D 2 NOP 1
MOV lab2,R6 ;8E 2 NOP 1
MOV lab2,R7 ;8F 2 NOP 1
MOV lab2,@R0 ;86 2 NOP 1
MOV lab2,@R1 ;87 2 NOP 1
MOV lab2,#labimm ;75 3 COMBINE 1
MOV lab5,lab2 ;85 3 COMBINE 1
MOVC A,@A+DPTR ;93 1 NOP 1
MOVC A,@A+PC ;83 1 NOP 1
MOVX A,@R0 ;e2 1 NOP 1
MOVX A,@R1 ;e3 1 NOP 1
MOVX A,@DPTR ;e0 1 NOP 1
MOVX @R0,A ;f2 1 NOP 1
MOVX @R1,A ;f3 1 NOP 1
MOVX @DPTR,A ;f0 1 NOP 1
MUL AB ;a4 1 NOP 1
NOP ;00 1 NOP 1
ORL A,R0 ;48 1 NOP 1
ORL A,R1 ;49 1 NOP 1
ORL A,R2 ;4A 1 NOP 1
ORL A,R3 ;4B 1 NOP 1
ORL A,R4 ;4C 1 NOP 1
ORL A,R5 ;4D 1 NOP 1
ORL A,R6 ;4E 1 NOP 1
ORL A,R7 ;4F 1 NOP 1
ORL A,@R0 ;46 1 NOP 1
ORL A,@R1 ;47 1 NOP 1
ORL A,#labimm ;44 2 NOP 1
ORL A,lab2 ;45 2 NOP 1
ORL C,/bit ;a0 2 NOP 1
ORL C,bit ;72 2 NOP 1
ORL lab2,A ;42 2 NOP 1
ORL lab2,#labimm ;43 3 COMBINE 1
POP lab2 ;d0 2 NOP 1
PUSH lab2 ;c0 2 NOP 1
RET ;22 1 NOP 1
RETI ;32 1 NOP 1
RL A ;23 1 NOP 1
RLC A ;33 1 NOP 1
RR A ;03 1 NOP 1
RRC A ;13 1 NOP 1
jlab5:
SETB C ;d3 1 NOP 1
SETB bit ;d2 2 NOP 1
SJMP jlab5 ;80 2 NOP 1
SUBB A,R0 ;98 1 NOP 1
SUBB A,R1 ;99 1 NOP 1
SUBB A,R2 ;9A 1 NOP 1
SUBB A,R3 ;9B 1 NOP 1
SUBB A,R4 ;9C 1 NOP 1
SUBB A,R5 ;9D 1 NOP 1
SUBB A,R6 ;9E 1 NOP 1
SUBB A,R7 ;9F 1 NOP 1
SUBB A,@R0 ;96 1 NOP 1
SUBB A,@R1 ;97 1 NOP 1
SUBB A,#labimm ;94 2 NOP 1
SUBB A,lab2 ;95 2 NOP 1
SWAP A ;c4 1 NOP 1
XCH A,R0 ;c8 1 NOP 1
XCH A,R1 ;c9 1 NOP 1
XCH A,R2 ;cA 1 NOP 1
XCH A,R3 ;cB 1 NOP 1
XCH A,R4 ;cC 1 NOP 1
XCH A,R5 ;cD 1 NOP 1
XCH A,R6 ;cE 1 NOP 1
XCH A,R7 ;cF 1 NOP 1
XCH A,@R0 ;c6 1 NOP 1
XCH A,@R1 ;c7 1 NOP 1
XCH A,lab2 ;c5 2 NOP 1
XCHD A,@R0 ;d6 1 NOP 1
XCHD A,@R1 ;d7 1 NOP 1
XRL A,R0 ;68 1 NOP 1
XRL A,R1 ;69 1 NOP 1
XRL A,R2 ;6A 1 NOP 1
XRL A,R3 ;6B 1 NOP 1
XRL A,R4 ;6C 1 NOP 1
XRL A,R5 ;6D 1 NOP 1
XRL A,R6 ;6E 1 NOP 1
XRL A,R7 ;6F 1 NOP 1
XRL A,@R0 ;66 1 NOP 1
XRL A,@R1 ;67 1 NOP 1
XRL A,#labimm ;64 2 NOP 1
XRL A,lab2 ;65 2 NOP 1
XRL lab2,A ;62 2 NOP 1
XRL lab2,#labimm ;63 3 COMBINE 1
.end

298
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test65.asm 1.2 1997/11/29 13:07:53 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 6502
;
#define FLAG1
#define TORG $1234
.org $56
zlabel .byte $12
.word $1234
.word $1234/3
.word 1234h
.word %0101010
.word 0101010b
.word @1234
.word 1234o
.word 1234
.word 1234d
.word 0d
.word 1d
.word 2d
.word 3d
.word 4d
.word 10d
.word 20d
.word 100d
.word *
.word $
.word 3 * 7
.word 3 + 7
.word 3 - 7
.word 73 % 7
.word $1234 >> 4
.word $1234 << 4
.word 1 = 1
.word 1 = 0
.word 1 >= 1
.word 1 >= 2
.word 1 >= 0
.word 1 <= 1
.word 1 <= 2
.word 1 <= 0
.word 1 <= -1
.word TORG
.org $0234
alabel
ADC #zlabel
ADC (zlabel,X)
ADC (zlabel),Y
ADC (zlabel)
ADC (alabel & $ff) ; suppress UNUSED DATA error
ADC zlabel,X
ADC zlabel,Y
ADC zlabel
ADC alabel
AND #zlabel
AND (zlabel,X)
AND (zlabel),Y
AND (zlabel)
AND zlabel,X
AND zlabel,Y
AND zlabel
AND alabel
ASL A
ASL zlabel,X
ASL zlabel
loop
BCC loop
BCS loop
BEQ loop
BNE loop
BMI loop
BPL loop
BVC loop
BVS loop
BIT #zlabel
BIT zlabel,X
BIT zlabel
BIT alabel
BRK
CLC
CLD
CLI
CLV
CMP #zlabel
CMP (zlabel,X)
CMP (zlabel),Y
CMP (zlabel)
CMP zlabel,X
CMP zlabel,Y
CMP zlabel
CMP alabel
CPX #zlabel
CPX zlabel
CPX alabel
CPY #zlabel
CPY zlabel
CPY alabel
DEC A
DEC zlabel,X
DEC alabel,X
DEC zlabel
DEC alabel
DEX
DEY
EOR #zlabel
EOR (zlabel,X)
EOR (zlabel),Y
EOR (zlabel)
EOR zlabel,X
EOR zlabel,Y
EOR zlabel
EOR alabel
INC A
INC zlabel,X
INC alabel,X
INC zlabel
INC alabel
INX
INY
JMP (zlabel,X)
JMP (zlabel)
JMP zlabel
JSR zlabel
JSR alabel
LDA #zlabel
LDA (zlabel,X)
LDA (zlabel),Y
LDA (zlabel)
LDA zlabel,X
LDA zlabel,Y
LDA zlabel
LDA alabel
LDX #zlabel
LDX zlabel,Y
LDX zlabel
LDX alabel
LDY #zlabel
LDY zlabel,X
LDY zlabel
LDY alabel
LSR A
LSR zlabel,X
LSR zlabel
LSR alabel
NOP
ORA #zlabel
ORA (zlabel,X)
ORA (zlabel),Y
ORA (zlabel)
ORA zlabel,X
ORA zlabel,Y
ORA zlabel
ORA alabel
PHA
PHP
PLA
PLP
ROL A
ROL zlabel,X
ROL zlabel
ROL alabel
ROR A
ROR zlabel,X
ROR alabel,X
ROR zlabel
ROR alabel
RTI
RTS
SBC #zlabel
SBC (zlabel,X)
SBC (zlabel),Y
SBC (zlabel)
SBC zlabel,X
SBC zlabel,Y
SBC zlabel
SBC alabel
SEC
SED
SEI
STA (zlabel,X)
STA (zlabel),Y
STA (zlabel)
STA zlabel,X
STA zlabel,Y
STA zlabel
STA alabel
STX zlabel,Y
STX zlabel
STX alabel
STY zlabel,X
STY zlabel
STY alabel
TAX
TAY
TSX
TXA
TXS
TYA
BRA loop2
loop2
BBR0 zlabel,loop2
BBR1 zlabel,loop2
BBR2 zlabel,loop2
BBR3 zlabel,loop2
BBR4 zlabel,loop2
BBR5 zlabel,loop2
BBR6 zlabel,loop2
BBR7 zlabel,loop2
BBS0 zlabel,loop2
BBS1 zlabel,loop2
BBS2 zlabel,loop2
BBS3 zlabel,loop2
BBS4 zlabel,loop2
BBS5 zlabel,loop2
BBS6 zlabel,loop2
BBS7 zlabel,loop2
MUL
PHX
PHY
PLX
PLY
RMB0 zlabel
RMB1 zlabel
RMB2 zlabel
RMB3 zlabel
RMB4 zlabel
RMB5 zlabel
RMB6 zlabel
RMB7 zlabel
SMB0 zlabel
SMB1 zlabel
SMB2 zlabel
SMB3 zlabel
SMB4 zlabel
SMB5 zlabel
SMB6 zlabel
SMB7 zlabel
STZ zlabel,X
STZ zlabel
STZ alabel
TRB zlabel
TSB zlabel
.end

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test68.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 6801/6803/68HC11
;
data1 .equ $12
data2 .equ $1234
ABA
ABX
ADDA #data1 ;8B
ADDA data1,X ;AB
ADDA data1 ;9B
ADDA data2 ;BB
ADDB #data1 ;CB
ADDB data1,X ;EB
ADDB data1 ;DB
ADDB data2 ;FB
ADCA #data1 ;89
ADCA data1,X ;A9
ADCA data1 ;99
ADCA data2 ;B9
ADCB #data1 ;C9
ADCB data1,X ;E9
ADCB data1 ;D9
ADCB data2 ;F9
ADDD #data1 ;C3
ADDD data1,X ;E3
ADDD data1 ;D3
ADDD data2 ;F3
ANDA #data1 ;84
ANDA data1,X ;A4
ANDA data1 ;94
ANDA data2 ;B4
ANDB #data1 ;C4
ANDB data1,X ;E4
ANDB data1 ;D4
ANDB data2 ;F4
ASL data1,X ;68
ASL data1 ;78
ASL data2 ;78
ASLA ;48
ASLB ;58
ASLD ;05
ASR data1,X ;
ASR data1 ;
ASR data2 ;
ASRA ;
ASRB ;
loop1:
BRA loop1 ;20
BRN loop1 ;21
BCC loop1 ;24
BCS loop1 ;25
BEQ loop1 ;27
BGE loop1 ;2C
BGT loop1 ;2E
BHI loop1 ;22
BHS loop1 ;24
BITA #data1 ;85
BITA data1,X ;A5
BITA data1 ;B5
BITA data2 ;B5
BITB #data1 ;C5
BITB data1,X ;E5
BITB data1 ;F5
BITB data2 ;F5
BLE loop1 ;2F
BLO loop1 ;25
BLS loop1 ;23
BLT loop1 ;2D
BMI loop1 ;2B
BNE loop1 ;26
BVC loop1 ;28
BVS loop1 ;29
BPL loop1 ;2A
BSR loop1 ;8D
CBA
CLC ;0C
CLI ;0E
CLR data1,X ;6F
CLR data1 ;7F
CLR data2 ;7F
CLRA ;4F
CLRB ;5F
CLV ;0A
COM data1,X ;63
COM data1 ;73
COM data2 ;73
COMA ;43
COMB ;53
CPX #data1 ;8C
CPX data1,X ;AC
CPX data1 ;9C
CPX data2 ;BC
CMPA #data1 ;
CMPA data1,X ;
CMPA data1 ;
CMPA data2 ;
CMPB #data1 ;
CMPB data1,X ;
CMPB data1 ;
CMPB data2 ;
DAA ;19
DEC data1,X
DEC data1
DEC data2
DECA ;4A
DECB ;5A
DES ;34
DEX ;09
EORA #data1 ;
EORA data1,X ;
EORA data1 ;
EORA data2 ;
EORB #data1 ;
EORB data1,X ;
EORB data1 ;
EORB data2 ;
INC data1,X
INC data1
INC data2
INCA ;4C
INCB ;5C
INS ;31
INX ;08
JMP data1,X ;63
JMP data1 ;7E
JMP data2 ;7E
JSR data1,X ;AD
JSR data1 ;9D
JSR data2 ;BD
LDAA #data1 ;86
LDAA data1,X ;A6
LDAA data1 ;96
LDAA data2 ;B6
LDAB #data1 ;C6
LDAB data1,X ;E6
LDAB data1 ;D6
LDAB data2 ;F6
LDD #data1 ;CC
LDD data1,X ;EC
LDD data1 ;DC
LDD data2 ;FC
LDS #data1 ;8E
LDS data1,X ;AE
LDS data1 ;9E
LDS data2 ;BE
LDX #data1 ;CE
LDX data1,X ;EE
LDX data1 ;DE
LDX data2 ;FE
LSLA ;48
LSLB ;58
LSLD ;05
LSRA ;44
LSRB ;54
LSRD ;04
LSR data1,X ;64
LSR data1 ;74
LSR data2 ;74
MUL ;3D
NEG data1,X ;60
NEG data1 ;70
NEG data2 ;70
NEGA ;40
NEGB ;50
NOP ;01
ORAA #data1 ;8A
ORAA data1,X ;AA
ORAA data1 ;BA
ORAA data2 ;9A
ORAB #data1 ;CA
ORAB data1,X ;EA
ORAB data1 ;DA
ORAB data2 ;FA
PSHA ;36
PSHB ;37
PSHX ;3C
PULA ;32
PULB ;33
PULX ;38
ROL data1,X ;69
ROL data1 ;79
ROLA ;49
ROLB ;59
ROR data1,X ;66
ROR data1 ;76
RORA ;46
RORB ;56
RTI ;3B
RTS ;39
SBA ;10
SBCA #data1 ;82
SBCA data1,X ;A2
SBCA data1 ;92
SBCA data2 ;B2
SBCB #data1 ;C2
SBCB data1,X ;E2
SBCB data1 ;D2
SBCB data2 ;F2
SEI ;0F
SEV ;0B
SEC
STS data1,X
STS data1
STS data2
STAA data1,X ;A7
STAA data1 ;97
STAA data2 ;B7
STAB data1,X ;E7
STAB data1 ;D7
STAB data2 ;F7
STD data1,X ;ED
STD data1 ;DD
STD data2 ;FD
STX data1,X ;EF
STX data1 ;FF
SUBA #data1 ;80
SUBA data1,X ;A0
SUBA data1 ;90
SUBA data2 ;B0
SUBB #data1 ;C0
SUBB data1,X ;E0
SUBB data1 ;D0
SUBB data2 ;F0
SUBD #data1 ;83
SUBD data1,X ;A3
SUBD data1 ;93
SUBD data2 ;B3
SWI ;3F
TAB ;16
TAP ;06
TPA ;07
TBA ;17
TST data1,X
TST data1
TST data2
TSTA ;4D
TSTB ;5D
TXS ;35
TSX ;30
WAI ;3E
;
; Test all the new 68HC11 instructions
;
bmsk .equ 12h
addr1 .equ 34h
addr2 .equ 5678h
imm .equ 55h
ABY ;183A
ADCA addr1,Y ;18A9
ADCB addr1,Y ;18E9
ADDA addr1,Y ;18AB
ADDB addr1,Y ;18EB
ADDD addr1,Y ;18E3
ANDA addr1,Y ;18A4
ANDB addr1,Y ;18E4
ASL addr1,Y ;1868
ASR addr1,Y ;1867
lab1
BCLR addr1,Y,bmsk
BCLR addr1,X,bmsk
BCLR addr1,bmsk
BITA addr1,Y ;18A5
BITB addr1,Y ;18E5
BRCLR addr1,Y,bmsk,lab1
BRCLR addr1,X,bmsk,lab1
BRCLR addr1,bmsk,lab1
BRCLR addr2,bmsk,lab1
BRSET addr1,Y,bmsk,lab1
BRSET addr1,X,bmsk,lab1
BRSET addr1,bmsk,lab1
BRSET addr2,bmsk,lab1
BSET addr1,Y,bmsk
BSET addr1,X,bmsk
BSET addr1,bmsk
CLR addr1,Y ;186F
CMPA addr1,Y ;18A1
CMPB addr1,Y ;18E1
COM addr1,Y ;1863
CPD #imm ;1A83
CPD addr1,X ;1AA3
CPD addr1,Y ;CDA3
CPD addr1 ;1AB3
CPD addr2 ;1AB3
CPX addr1,Y ;CDAC
CPY #imm ;188C
CPY addr1,Y ;18AC
CPY addr1,X ;1AAC
CPY addr1 ;18BC
CPY addr2 ;18BC
DEC addr1,Y ;186A
DEY ;1809
EORA addr1,Y ;18A8
EORB addr1,Y ;18E8
FDIV ;03
IDIV ;02
INC addr1,Y ;186C
INY ;1808
JMP addr1,Y ;186E
JSR addr1,Y ;18AD
LDAA addr1,Y ;18A6
LDAB addr1,Y ;18E6
LDD addr1,Y ;18EC
LDS addr1,Y ;18AE
LDX addr1,Y ;CDEE
LDY #imm ;18CE
LDY addr1,Y ;18EE
LDY addr1,X ;1AEE
LDY addr1 ;18FE
LDY addr2 ;18FE
LSL addr1,Y ;1868
LSR addr1,Y ;1864
NEG addr1,Y ;1860
ORAA addr1,Y ;18AA
ORAB addr1,Y ;18EA
PSHY ;183C
PULY ;1838
ROL addr1,Y ;1869
ROR addr1,Y ;1866
SBCA addr1,Y ;18A2
SBCB addr1,Y ;18E2
STAA addr1,Y ;18A7
STAB addr1,Y ;18E7
STD addr1,Y ;18ED
STS addr1,Y ;CDAF
STX addr1,Y ;CDEF
STY addr1,Y ;18EF
STY addr1,X ;1AEF
STY addr1 ;18FF
STY addr2 ;18FF
SUBA addr1,Y ;18A0
SUBB addr1,Y ;18E0
SUBD addr1,Y ;18A3
TST addr1,Y ;186D
; TEST ;
TSY ;1830 2 NOP 4
TYS ;1835 2 NOP 4
XGDX ;8F 1 NOP 4
XGDY ;188F 2 NOP 4
.end

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test70.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: TMS7000
;
R0 .equ 0
R1 .equ 1
R2 .equ 2
R3 .equ 3
R12 .equ 12
R13 .equ 13
R7 .equ 7
data1 .equ $34
data2 .equ $1287
table .equ $1234
P7 .equ 7
.org $f000
start:
ADC B,A
ADC %data1,A
ADC %data1,B
ADC %data1,R7
ADC R12,A
ADC R13,B
ADC R12,R7
ADD B,A
ADD %data1,A
ADD %data1,B
ADD %data1,R7
ADD R12,A
ADD R13,B
ADD R12,R7
AND B,A
AND %data1,A
AND %data1,B
AND %data1,R7
AND R12,A
AND R13,B
AND R12,R7
ANDP A,R7
ANDP B,R7
ANDP %data1,R7
BTJO B,A,start
BTJO %data1,A,start
BTJO %data1,B,start
BTJO %data1,R7,start
BTJO R12,A,start
BTJO R13,B,start
BTJO R12,R7,start
loop1
BTJOP A,P7,loop1
BTJOP B,P7,loop1
BTJOP %data1,P7,loop1
BTJZ B,A,loop1
BTJZ %data1,A,loop1
BTJZ %data1,B,loop1
BTJZ %data1,R7,loop1
BTJZ R12,A,loop1
BTJZ R12,B,loop1
BTJZ R12,R7,loop1
BTJZP A,P7,loop1
BTJZP B,P7,loop1
BTJZP %data1,P7,loop1
BR @start(B)
BR @start[B]
BR @start
BR *R7
CALL @sub1(B)
CALL @sub1
CALL *R7
sub1: CLR A
CLR B
CLR R12
CLRC
CMP B,A
CMP %data1,A
CMP %data1,B
CMP %data1,R7
CMP R12,A
CMP R12,B
CMP R12,R7
CMPA @R7(B)
CMPA @R7[B]
CMPA @R7
CMPA *R7
DAC B,A
DAC %data1,A
DAC %data1,B
DAC %data1,R7
DAC R12,A
DAC R12,B
DAC R12,R7
DEC A
DEC B
DEC R7
DECD A
DECD B
DECD R7
DINT
DJNZ A,loop2
DJNZ B,loop2
DJNZ R12,loop2
DSB B,A
DSB %data1,A
DSB %data1,B
DSB %data1,R7
DSB R12,A
DSB R12,B
DSB R12,R7
EINT
IDLE
INC A
INC B
INC R7
INV A
INV B
INV R7
loop2:
JMP loop2
JC loop2
JEQ loop2
JGE loop2
JGT loop2
JHS loop2
JL loop2
JN loop2
JNC loop2
JNE loop2
JNZ loop2
JP loop2
JPZ loop2
JZ loop2
LDA @table(B)
LDA @table
LDA *R7
LDSP
MOV A,B
MOV B,A
MOV A,R7
MOV B,R7
MOV %data1,A
MOV %data1,B
MOV %data1,R7
MOV R12,A
MOV R12,B
MOV R12,R7
MOVD %data2,R7
MOVD %data2[B],R7
MOVD R12,R7
MOVP A,P7
MOVP B,P7
MOVP %data1,P7
MOVP P7,A
MOVP P7,B
MPY B,A
MPY %data1,A
MPY %data1,B
MPY %data1,R7
MPY R12,A
MPY R12,B
MPY R12,R7
NOP
OR B,A
OR %data1,A
OR %data1,B
OR %data1,R7
OR R12,A
OR R12,B
OR R12,R7
ORP A,P7
ORP B,P7
ORP %data1,P7
POP A
POP B
POP R7
POPST
POP ST
PUSH A
PUSH B
PUSH R7
PUSHST
PUSH ST
RETI
RETS
RL A
RL B
RL R7
RLC A
RLC B
RLC R7
RR A
RR B
RR R7
RRC A
RRC B
RRC R7
SBB B,A
SBB %data1,A
SBB %data1,B
SBB %data1,R7
SBB R12,A
SBB R12,B
SBB R12,R7
SETC
STA @table(B)
STA @table
STA *R7
STSP
SUB B,A
SUB %data1,A
SUB %data1,B
SUB %data1,R7
SUB R12,A
SUB R12,B
SUB R12,R7
SWAP A
SWAP B
SWAP R7
TRAP 0
TRAP 1
TRAP 6
TRAP 12
TRAP 23
TST A
TSTA
TST B
TSTB
XCHB A
XCHB R7
XOR B,A
XOR %data1,A
XOR %data1,B
XOR %data1,R7
XOR R12,A
XOR R12,B
XOR R12,R7
XORP A,P7
XORP B,P7
XORP %data1,P7
.end

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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test85.asm 1.1 1993/08/02 01:24:21 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 8080/8085
;
idata16 .equ 1234h
idata8 .equ 12h
port .equ 34h
addr16 .equ 5678h
.org 1000h
start:
nop
lxi b,idata16
stax b
inx b
inr b
dcr b
mvi b,idata8
rlc
dad b
ldax b
dcx b
inr c
dcr c
mvi c,idata8
rrc
; --- ; 10
lxi d,idata16
stax d
inx d
inr d
dcr d
mvi d,idata8
ral
; ---
dad d
ldax d
dcx d
inr e
dcr e
mvi e,idata8
rar
rim ; 20
lxi h,idata16
shld addr16
inx h
inr h
dcr h
mvi h,idata8
daa
; ---
dad h
lhld addr16
dcx h
inr l
dcr l
mvi l,idata8
cma
sim ; 30
lxi sp,idata16
sta addr16
inx sp
inr m
dcr m
mvi m,idata8
stc
; ---
dad sp
lda addr16
dcx sp
inr a
dcr a
mvi a,idata8
cmc
mov b,b ; 40
mov b,c
mov b,d
mov b,e
mov b,h
mov b,l
mov b,m
mov b,a
mov c,b
mov c,c
mov c,d
mov c,e
mov c,h
mov c,l
mov c,m
mov c,a
mov d,b ; 50
mov d,c
mov d,d
mov d,e
mov d,h
mov d,l
mov d,m
mov d,a
mov e,b
mov e,c
mov e,d
mov e,e
mov e,h
mov e,l
mov e,m
mov e,a
mov h,b ; 60
mov h,c
mov h,d
mov h,e
mov h,h
mov h,l
mov h,m
mov h,a
mov l,b
mov l,c
mov l,d
mov l,e
mov l,h
mov l,l
mov l,m
mov l,a
mov m,b ; 70
mov m,c
mov m,d
mov m,e
mov m,h
mov m,l
hlt
mov m,a
mov a,b
mov a,c
mov a,d
mov a,e
mov a,h
mov a,l
mov a,m
mov a,a
add b ; 80
add c
add d
add e
add h
add l
add m
add a
adc b ; 88
adc c
adc d
adc e
adc h
adc l
adc m
adc a
sub b ; 90
sub c
sub d
sub e
sub h
sub l
sub m
sub a
sbb b ; 98
sbb c
sbb d
sbb e
sbb h
sbb l
sbb m
sbb a
ana b ; a0
ana c
ana d
ana e
ana h
ana l
ana m
ana a
xra b ; a8
xra c
xra d
xra e
xra h
xra l
xra m
xra a
ora b ; b0
ora c
ora d
ora e
ora h
ora l
ora m
ora a
cmp b ; b8
cmp c
cmp d
cmp e
cmp h
cmp l
cmp m
cmp a
rnz ; c0
pop b
jnz start
jmp start
cnz start
push b
adi idata8
rst 0
rz
ret
jz start
; ---
cz start
call start
aci idata8
rst 1
rnc ; d0
pop d
jnc start
out port
cnc start
push d
sui idata8
rst 2
rc
; ---
jc start
in port
cc start
; ---
sbi idata8
rst 3
rpo ; e0
pop h
jpo start
xthl
cpo start
push h
ani idata8
rst 4
rpe
pchl
jpe start
xchg
cpe start
; ---
xri idata8
rst 5
rp ; f0
pop psw
jp start
di
cp start
push psw
ori idata8
rst 6
rm
sphl
jm start
ei
cm start
; ---
cpi idata8
rst 7
.END

887
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: test96.asm 1.1 1997/11/23 15:51:20 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: 8096/8XC196KC
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
; CPU "8096.TBL" ; CPU TABLE
; HOF "INT8" ; HEX FORMAT
#define EQU .equ
#define END .end
#define ORG .org
#define DWL .dw
#define IF #if
#define ENDI #endif
wreg: EQU 12h ; word register even address
wreg1: EQU 22h ; word register even address
wreg2: EQU 32h ; word register even address
wreg3: EQU 42h ; word register even address
lreg1: EQU 44h ; long register (32 bit)
lreg2: EQU 48h ; long register (32 bit)
breg: EQU wreg+1 ; low byte of reg. where odd is allowed
breg1: EQU wreg+3 ; low byte of reg. where odd is allowed
breg2: EQU wreg+5 ; low byte of reg. where odd is allowed
breg3: EQU wreg+7 ; low byte of reg. where odd is allowed
imm8: EQU 88H
imm16: EQU 4321H
addr8: EQU 12H
addr16: EQU 3456H
ishort: EQU 12H
ishrt: EQU 12H
ilong: EQU 4567H
count: EQU 7H
ORG 7418h
dtable: DWL $1234
DWL $5678
DWL $1234
;-------------------------------------
; ADD
add wreg1,#imm8
add wreg1,#imm16
add wreg1,wreg2
add wreg1,addr16
add wreg1,[wreg2]
add wreg1,[wreg2]+
add wreg1,addr8[wreg2]
add wreg1,addr16[wreg2]
add wreg1,wreg2,#imm8
add wreg1,wreg2,#imm16
add wreg1,wreg2,wreg3
add wreg1,wreg2,addr16
add wreg1,wreg2,[wreg3]
add wreg1,wreg2,[wreg3]+
add wreg1,wreg2,addr8[wreg3]
add wreg1,wreg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; ADDB
addb breg1,#imm8
addb breg1,breg2
addb breg1,addr16
addb breg1,[wreg2]
addb breg1,[wreg2]+
addb breg1,addr8[wreg2]
addb breg1,addr16[wreg2]
addb breg1,breg2,#imm8
addb breg1,breg2,breg3
addb breg1,breg2,addr16
addb breg1,breg2,[wreg3]
addb breg1,breg2,[wreg3]+
addb breg1,breg2,addr8[wreg3]
addb breg1,breg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; ADDB
addc wreg1,#imm8
addc wreg1,#imm16
addc wreg1,wreg2
addc wreg1,addr16
addc wreg1,[wreg2]
addc wreg1,[wreg2]+
addc wreg1,addr8[wreg2]
addc wreg1,addr16[wreg2]
; No three arg form for addc
;-------------------------------------
;-------------------------------------
; ADDCB
addcb breg1,#imm8
addcb breg1,breg2
addcb breg1,addr16
addcb breg1,[wreg2]
addcb breg1,[wreg2]+
addcb breg1,addr8[wreg2]
addcb breg1,addr16[wreg2]
; No three arg form for addcb
;-------------------------------------
;-------------------------------------
; AND
and wreg1,#imm8
and wreg1,#imm16
and wreg1,wreg2
and wreg1,addr16
and wreg1,[wreg2]
and wreg1,[wreg2]+
and wreg1,addr8[wreg2]
and wreg1,addr16[wreg2]
and wreg1,wreg2,#imm8
and wreg1,wreg2,#imm16
and wreg1,wreg2,wreg3
and wreg1,wreg2,addr16
and wreg1,wreg2,[wreg3]
and wreg1,wreg2,[wreg3]+
and wreg1,wreg2,addr8[wreg3]
and wreg1,wreg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; ANDB
andb breg1,#imm8
andb breg1,breg2
andb breg1,addr16
andb breg1,[wreg2]
andb breg1,[wreg2]+
andb breg1,addr8[wreg2]
andb breg1,addr16[wreg2]
andb breg1,breg2,#imm8
andb breg1,breg2,breg3
andb breg1,breg2,addr16
andb breg1,breg2,[wreg3]
andb breg1,breg2,[wreg3]+
andb breg1,breg2,addr8[wreg3]
andb breg1,breg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; BMOV
bmov lreg1,wreg1
bmov lreg1,wreg2
;-------------------------------------
;-------------------------------------
; BR
br [wreg1]
;-------------------------------------
;-------------------------------------
; MISC CLR
clr wreg1
clrb breg1
clrc
clrvt
;-------------------------------------
;-------------------------------------
; CMP
cmp wreg1,#imm8
cmp wreg1,#imm16
cmp wreg1,wreg2
cmp wreg1,addr16
cmp wreg1,[wreg2]
cmp wreg1,[wreg2]+
cmp wreg1,addr8[wreg2]
cmp wreg1,addr16[wreg2]
; No three arg form for cmp
;-------------------------------------
;-------------------------------------
; CMPB
cmpb breg1,#imm8
cmpb breg1,breg2
cmpb breg1,addr16
cmpb breg1,[wreg2]
cmpb breg1,[wreg2]+
cmpb breg1,addr8[wreg2]
cmpb breg1,addr16[wreg2]
; No three arg form for cmpb
;-------------------------------------
;-------------------------------------
; CMPL
cmpl lreg1,lreg2
;-------------------------------------
;-------------------------------------
; DEC
dec wreg1
decb breg1
;-------------------------------------
;-------------------------------------
; DEC
di
;-------------------------------------
;-------------------------------------
; DIV
div lreg1,#imm8
div lreg1,#imm16
div lreg1,wreg2
div lreg1,addr16
div lreg1,[wreg2]
div lreg1,[wreg2]+
div lreg1,addr8[wreg2]
div lreg1,addr16[wreg2]
; No three arg form for div
;-------------------------------------
;-------------------------------------
; DIVB
divb wreg1,#imm8
divb wreg1,breg2
divb wreg1,addr16
divb wreg1,[wreg2]
divb wreg1,[wreg2]+
divb wreg1,addr8[wreg2]
divb wreg1,addr16[wreg2]
; No three arg form for divb
;-------------------------------------
;-------------------------------------
; DIVU
divu lreg1,#imm8
divu lreg1,#imm16
divu lreg1,wreg2
divu lreg1,addr16
divu lreg1,[wreg2]
divu lreg1,[wreg2]+
divu lreg1,addr8[wreg2]
divu lreg1,addr16[wreg2]
; No three arg form for divu
;-------------------------------------
;-------------------------------------
; DIVUB
divub wreg1,#imm8
divub wreg1,breg2
divub wreg1,addr16
divub wreg1,[wreg2]
divub wreg1,[wreg2]+
divub wreg1,addr8[wreg2]
divub wreg1,addr16[wreg2]
; No three arg form for divub
;-------------------------------------
;-------------------------------------
; DJNZ
rtest1: ;backward reference
djnz breg1,rtest1
djnz breg1,rtest1
djnz breg1,rtest2
djnz breg1,rtest2
rtest2: ;forward reference
;-------------------------------------
;-------------------------------------
; DJNZW
djnzw wreg1,rtest1
djnzw wreg1,rtest1
djnzw wreg1,rtest3
djnzw wreg1,rtest3
rtest3: ;forward reference
;-------------------------------------
;-------------------------------------
; DPTS
dpts
;-------------------------------------
;-------------------------------------
; EI
ei
;-------------------------------------
;-------------------------------------
; EPTS
epts
;-------------------------------------
;-------------------------------------
; EXT & EXTB
ext lreg1
ext lreg2
extb wreg1
extb wreg2
;-------------------------------------
;-------------------------------------
; IDLPD
idlpd #1
idlpd #2
;-------------------------------------
;-------------------------------------
; INC & INCB
inc wreg1
inc wreg2
incb breg1
incb breg2
;-------------------------------------
FLAG: EQU 3
;-------------------------------------
; JBC
jbc breg1,0,rtest1
jbc breg1,1,rtest1
jbc breg1,2,rtest1
jbc breg1,3,rtest1
jbc breg1,4,rtest1
jbc breg1,5,rtest1
jbc breg1,6,rtest1
jbc breg1,7,rtest1
;-------------------------------------
;-------------------------------------
; JBS
jbs breg1,0,rtest1
jbs breg1,1,rtest1
jbs breg1,2,rtest1
jbs breg1,3,rtest1
jbs breg1,4,rtest1
jbs breg1,5,rtest1
jbs breg1,6,rtest1
jbs breg1,7,rtest1
;-------------------------------------
;-------------------------------------
; MISC Jump backward
jc rtest1
je rtest1
jge rtest1
jgt rtest1
jh rtest1
jle rtest1
jlt rtest1
jnc rtest1
jne rtest1
jnh rtest1
jnst rtest1
jnv rtest1
jnvt rtest1
jst rtest1
jv rtest1
jvt rtest1
;-------------------------------------
;-------------------------------------
; MISC Jump forward
jc rtest4
je rtest4
jge rtest4
jgt rtest4
jh rtest4
jle rtest4
jlt rtest4
jnc rtest4
jne rtest4
jnh rtest4
jnst rtest4
jnv rtest4
jnvt rtest4
jst rtest4
jv rtest4
rtest4: jvt rtest4
;-------------------------------------
;-------------------------------------
; LCALL
lcall rtest1
lcall rtest2
lcall rtest4
lcall addr8
lcall addr16
;-------------------------------------
;-------------------------------------
; LD
ld wreg1,#imm8
ld wreg1,#imm16
ld wreg1,wreg2
ld wreg1,addr16
ld wreg1,[wreg2]
ld wreg1,[wreg2]+
ld wreg1,addr8[wreg2]
ld wreg1,addr16[wreg2]
; No three arg form for ld
;-------------------------------------
;-------------------------------------
; LDB
ldb breg1,#imm8
ldb breg1,breg2
ldb breg1,addr16
ldb breg1,[wreg2]
ldb breg1,[wreg2]+
ldb breg1,addr8[wreg2]
ldb breg1,addr16[wreg2]
; No three arg form for ldb
;-------------------------------------
;-------------------------------------
; LDBSE
ldbse wreg1,#imm8
ldbse wreg1,breg2
ldbse wreg1,addr16
ldbse wreg1,[wreg2]
ldbse wreg1,[wreg2]+
ldbse wreg1,addr8[wreg2]
ldbse wreg1,addr16[wreg2]
; No three arg form for ldbse
;-------------------------------------
;-------------------------------------
; LDBZE
ldbze wreg1,#imm8
ldbze wreg1,breg2
ldbze wreg1,addr16
ldbze wreg1,[wreg2]
ldbze wreg1,[wreg2]+
ldbze wreg1,addr8[wreg2]
ldbze wreg1,addr16[wreg2]
; No three arg form for ldbze
;-------------------------------------
;-------------------------------------
; LJMP
ljmp addr8
ljmp addr16
;-------------------------------------
;-------------------------------------
; MUL
mul lreg1,#imm8
mul lreg1,#imm16
mul lreg1,wreg2
mul lreg1,addr16
mul lreg1,[wreg2]
mul lreg1,[wreg2]+
mul lreg1,addr8[wreg2]
mul lreg1,addr16[wreg2]
mul lreg1,wreg2,#imm8
mul lreg1,wreg2,#imm16
mul lreg1,wreg2,wreg3
mul lreg1,wreg2,addr16
mul lreg1,wreg2,[wreg3]
mul lreg1,wreg2,[wreg3]+
mul lreg1,wreg2,addr8[wreg3]
mul lreg1,wreg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; MULB
mulb wreg1,#imm8
mulb wreg1,breg2
mulb wreg1,addr16
mulb wreg1,[wreg2]
mulb wreg1,[wreg2]+
mulb wreg1,addr8[wreg2]
mulb wreg1,addr16[wreg2]
mulb wreg1,breg2,#imm8
mulb wreg1,breg2,breg3
mulb wreg1,breg2,addr16
mulb wreg1,breg2,[wreg3]
mulb wreg1,breg2,[wreg3]+
mulb wreg1,breg2,addr8[wreg3]
mulb wreg1,breg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; MULU
mulu lreg1,#imm8
mulu lreg1,#imm16
mulu lreg1,wreg2
mulu lreg1,addr16
mulu lreg1,[wreg2]
mulu lreg1,[wreg2]+
mulu lreg1,addr8[wreg2]
mulu lreg1,addr16[wreg2]
mulu lreg1,wreg2,#imm8
mulu lreg1,wreg2,#imm16
mulu lreg1,wreg2,wreg3
mulu lreg1,wreg2,addr16
mulu lreg1,wreg2,[wreg3]
mulu lreg1,wreg2,[wreg3]+
mulu lreg1,wreg2,addr8[wreg3]
mulu lreg1,wreg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; MULUB
mulub wreg1,#imm8
mulub wreg1,breg2
mulub wreg1,addr16
mulub wreg1,[wreg2]
mulub wreg1,[wreg2]+
mulub wreg1,addr8[wreg2]
mulub wreg1,addr16[wreg2]
mulub wreg1,breg2,#imm8
mulub wreg1,breg2,breg3
mulub wreg1,breg2,addr16
mulub wreg1,breg2,[wreg3]
mulub wreg1,breg2,[wreg3]+
mulub wreg1,breg2,addr8[wreg3]
mulub wreg1,breg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; NEG & NEGB
neg wreg1
negb breg1
;-------------------------------------
;-------------------------------------
; NOP
nop
;-------------------------------------
;-------------------------------------
; NORML
norml lreg1,breg1
;-------------------------------------
;-------------------------------------
; NOT & NOTB
not wreg1
notb breg1
;-------------------------------------
;-------------------------------------
; OR
or wreg1,#imm8
or wreg1,#imm16
or wreg1,wreg2
or wreg1,addr16
or wreg1,[wreg2]
or wreg1,[wreg2]+
or wreg1,addr8[wreg2]
or wreg1,addr16[wreg2]
; No three arg form for or
;-------------------------------------
;-------------------------------------
; ORB
orb breg1,#imm8
orb breg1,breg2
orb breg1,addr16
orb breg1,[wreg2]
orb breg1,[wreg2]+
orb breg1,addr8[wreg2]
orb breg1,addr16[wreg2]
; No three arg form for orb
;-------------------------------------
;-------------------------------------
; POP
pop wreg1
pop [wreg1]
pop [wreg1]+
pop addr8[wreg1]
pop addr16[wreg1]
popa
popf
;-------------------------------------
;-------------------------------------
; PUSH
push wreg1
push [wreg1]
push [wreg1]+
push addr8[wreg1]
push addr16[wreg1]
pusha
pushf
;-------------------------------------
;-------------------------------------
; RET - return
ret
;-------------------------------------
;-------------------------------------
; RST - reset
rst
;-------------------------------------
;-------------------------------------
; SCALL - short call
scall1:
scall2: EQU scall1-1015
scall scall1
scall scall1
scall scall2
scall scall2
scall scall3
scall scall4
scall3:
scall4: EQU scall3+1020
;-------------------------------------
;-------------------------------------
; SETC - set carry
setc
;-------------------------------------
;-------------------------------------
; shl - shift word left
shl wreg1,#count
shl wreg2,breg1
;-------------------------------------
;-------------------------------------
; shlb - shift byte left
shlb breg1,#count
shlb breg2,breg1
;-------------------------------------
;-------------------------------------
; shll - shift long word left
shll lreg1,#count
shll lreg1,breg1
;-------------------------------------
;-------------------------------------
; shr - logical shift word right
shr wreg1,#count
shr wreg2,breg1
;-------------------------------------
;-------------------------------------
; shra - arithmetic shift word right
shra wreg1,#count
shra wreg2,breg1
;-------------------------------------
;-------------------------------------
; shrab - arithmetic shift byte right
shrab breg1,#count
shrab breg2,breg1
;-------------------------------------
;-------------------------------------
; shral - arithmetic shift long word right
shral lreg1,#count
shral lreg1,breg1
;-------------------------------------
;-------------------------------------
; shrb - logical shift byte right
shrb breg1,#count
shrb breg2,breg1
;-------------------------------------
;-------------------------------------
; shrl - logical shift long word right
shrl lreg1,#count
shrl lreg1,breg1
;-------------------------------------
;-------------------------------------
; SJMP - short jump
sjump1:
sjump2: EQU sjump1-1015
sjmp sjump1
sjmp sjump1
sjmp sjump2
sjmp sjump2
sjmp sjump3
sjmp sjump4
sjump3:
sjump4: EQU sjump3+1020
;-------------------------------------
;-------------------------------------
; skip - two byte nop
skip breg1
;-------------------------------------
;-------------------------------------
; ST - store word
st wreg1,wreg2
st wreg1,addr16
st wreg1,[wreg2]
st wreg1,[wreg2]+
st wreg1,addr8[wreg2]
st wreg1,addr16[wreg2]
; No three arg form for st; No immediate
;-------------------------------------
;-------------------------------------
; STB - store byte
stb breg1,breg2
stb breg1,addr16
stb breg1,[wreg2]
stb breg1,[wreg2]+
stb breg1,addr8[wreg2]
stb breg1,addr16[wreg2]
; No three arg form for stb; No immediate
;-------------------------------------
;-------------------------------------
; SUB - subtract word
sub wreg1,#imm8
sub wreg1,#imm16
sub wreg1,wreg2
sub wreg1,addr16
sub wreg1,[wreg2]
sub wreg1,[wreg2]+
sub wreg1,addr8[wreg2]
sub wreg1,addr16[wreg2]
sub wreg1,wreg2,#imm8
sub wreg1,wreg2,#imm16
sub wreg1,wreg2,wreg3
sub wreg1,wreg2,addr16
sub wreg1,wreg2,[wreg3]
sub wreg1,wreg2,[wreg3]+
sub wreg1,wreg2,addr8[wreg3]
sub wreg1,wreg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; SUBB - subtract byte
subb breg1,#imm8
subb breg1,breg2
subb breg1,addr16
subb breg1,[wreg2]
subb breg1,[wreg2]+
subb breg1,addr8[wreg2]
subb breg1,addr16[wreg2]
subb breg1,breg2,#imm8
subb breg1,breg2,breg3
subb breg1,breg2,addr16
subb breg1,breg2,[wreg3]
subb breg1,breg2,[wreg3]+
subb breg1,breg2,addr8[wreg3]
subb breg1,breg2,addr16[wreg3]
;-------------------------------------
;-------------------------------------
; SUBC - subtract word with carry
subc wreg1,#imm8
subc wreg1,#imm16
subc wreg1,wreg2
subc wreg1,addr16
subc wreg1,[wreg2]
subc wreg1,[wreg2]+
subc wreg1,addr8[wreg2]
subc wreg1,addr16[wreg2]
; No three arg form for subc
;-------------------------------------
;-------------------------------------
; SUBCB - subtract byte with carry
subcb breg1,#imm8
subcb breg1,breg2
subcb breg1,addr16
subcb breg1,[wreg2]
subcb breg1,[wreg2]+
subcb breg1,addr8[wreg2]
subcb breg1,addr16[wreg2]
; No three arg form for subcb
;-------------------------------------
;-------------------------------------
; tijmp - table indirect jump
tijmp wreg1,[wreg2],#imm8
tijmp wreg2,[wreg1],#imm8
tijmp wreg3,[wreg2],#13
;-------------------------------------
;-------------------------------------
; TRAP - software trap
trap
;-------------------------------------
;-------------------------------------
; XCH - exchange word
xch wreg1,wreg2
xch wreg1,addr16
xch wreg1,addr8[wreg2]
xch wreg1,addr16[wreg2]
;-------------------------------------
;-------------------------------------
; XCHB - exchange byte
xchb breg1,breg2
xchb breg1,addr16
xchb breg1,addr8[wreg2]
xchb breg1,addr16[wreg2]
;-------------------------------------
;-------------------------------------
; XOR
xor wreg1,#imm8
xor wreg1,#imm16
xor wreg1,wreg2
xor wreg1,addr16
xor wreg1,[wreg2]
xor wreg1,[wreg2]+
xor wreg1,addr8[wreg2]
xor wreg1,addr16[wreg2]
; No three arg form for xor
;-------------------------------------
;-------------------------------------
; XORB
xorb breg1,#imm8
xorb breg1,breg2
xorb breg1,addr16
xorb breg1,[wreg2]
xorb breg1,[wreg2]+
xorb breg1,addr8[wreg2]
xorb breg1,addr16[wreg2]
; No three arg form for xorb
;-------------------------------------
END

18
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rem mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
rem $Id: testtabs.bat 1.3 1998/02/25 12:27:04 toma Exp $
rem mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
rem Run TASM on all the table test files. Those that have
rem extended instuctions use the -x option.
tasm -48 -x test48.asm
tasm -65 -x test65.asm
tasm -51 test51.asm
tasm -85 test85.asm
tasm -80 -x testz80.asm
tasm -05 -x test05.asm
tasm -3210 test3210.asm
tasm -3225 test3225.asm
tasm -68 -x test68.asm
tasm -70 test70.asm
tasm -96 -x test96.asm

19
trunk/XSource/bin/TESTTABS.SH Normal file
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#!/bin/sh
#rem mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
#rem $Id: testtabs.bat 1.3 1998/02/25 12:27:04 toma Exp $
#rem mmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmmm
#rem Run TASM on all the table test files. Those that have
#rem extended instuctions use the -x option.
./TASM -48 -x TEST48.ASM
./TASM -65 -x TEST65.ASM
./TASM -51 TEST51.ASM
./TASM -85 TEST85.ASM
./TASM -80 -x TESTz80.ASM
./TASM -05 -x TEST05.ASM
./TASM -3210 TEST3210.ASM
./TASM -3225 TEST3225.ASM
./TASM -68 -x TEST68.ASM
./TASM -70 TEST70.ASM
./TASM -96 -x TEST96.ASM

831
trunk/XSource/bin/TESTZ80.ASM Normal file
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; $Id: testz80.asm 1.4 1998/02/25 12:18:20 toma Exp $
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; TASM test file
; Test all instructions and addressing modes.
; Processor: Z80
;
; SEPT. 16,1987
; CARL A. WALL
; VE3APY
;
;
#define equ .equ
#define end .end
n: equ 20h
nn: equ 0584h
dddd: equ 07h
addr16: equ $1234
port: equ 3
imm8: equ 56h ;immediate data (8 bits)
offset: equ 7
offset_neg: equ -7
; try a few cases that have two expressions in the args and
; one is inside ().
LD (IX+offset),n+1+4+8-9
LD (IX+offset+5),n-1
LD (IX+dddd),n
LD (IX+offset),n
LD (IX+offset),n
; Try all possible instructions
ADC A,(HL)
ADC A,(IX+offset)
ADC A,(IX+offset_neg)
ADC A,(IY+offset)
ADC A,(IY+offset_neg)
ADC A,A
ADC A,B
ADC A,C
ADC A,D
ADC A,E
ADC A,H
ADC A,L
ADC A,n
ADC HL,BC
ADC HL,DE
ADC HL,HL
ADC HL,SP
ADD A,(HL)
ADD A,(IX+offset)
ADD A,(IY+offset)
ADD A,A
ADD A,B
ADD A,C
ADD A,D
ADD A,E
ADD A,H
ADD A,L
ADD A,n
ADD HL,BC
ADD HL,DE
ADD HL,HL
ADD HL,SP
ADD IX,BC
ADD IX,DE
ADD IX,IX
ADD IX,SP
ADD IY,BC
ADD IY,DE
ADD IY,IY
ADD IY,SP
AND (HL)
AND (IX+offset)
AND (IY+offset)
AND A
AND B
AND C
AND D
AND E
AND H
AND L
AND n
BIT 0,(HL)
BIT 0,(IX+offset)
BIT 0,(IY+offset)
BIT 0,A
BIT 0,B
BIT 0,C
BIT 0,D
BIT 0,E
BIT 0,H
BIT 0,L
BIT 1,(HL)
BIT 1,(IX+offset)
BIT 1,(IY+offset)
BIT 1,A
BIT 1,B
BIT 1,C
BIT 1,D
BIT 1,E
BIT 1,H
BIT 1,L
BIT 2,(HL)
BIT 2,(IX+offset)
BIT 2,(IY+offset)
BIT 2,A
BIT 2,B
BIT 2,C
BIT 2,D
BIT 2,E
BIT 2,H
BIT 2,L
BIT 3,(HL)
BIT 3,(IX+offset)
BIT 3,(IY+offset)
BIT 3,A
BIT 3,B
BIT 3,C
BIT 3,D
BIT 3,E
BIT 3,H
BIT 3,L
BIT 4,(HL)
BIT 4,(IX+offset)
BIT 4,(IY+offset)
BIT 4,A
BIT 4,B
BIT 4,C
BIT 4,D
BIT 4,E
BIT 4,H
BIT 4,L
BIT 5,(HL)
BIT 5,(IX+offset)
BIT 5,(IY+offset)
BIT 5,A
BIT 5,B
BIT 5,C
BIT 5,D
BIT 5,E
BIT 5,H
BIT 5,L
BIT 6,(HL)
BIT 6,(IX+offset)
BIT 6,(IY+offset)
BIT 6,A
BIT 6,B
BIT 6,C
BIT 6,D
BIT 6,E
BIT 6,H
BIT 6,L
BIT 7,(HL)
BIT 7,(IX+offset)
BIT 7,(IY+offset)
BIT 7,A
BIT 7,B
BIT 7,C
BIT 7,D
BIT 7,E
BIT 7,H
BIT 7,L
CALL C,addr16
CALL M,addr16
CALL NC,addr16
CALL NZ,addr16
CALL P,addr16
CALL PE,addr16
CALL PO,addr16
CALL Z,addr16
CALL addr16
CCF
CP (HL)
CP (IX+offset)
CP (IY+offset)
CP A
CP B
CP C
CP D
CP E
CP H
CP L
CP imm8
CPD
CPDR
CPIR
CPI
CPL
DAA
DEC (HL)
DEC (IX+offset)
DEC (IY+offset)
DEC A
DEC B
DEC BC
DEC C
DEC D
DEC DE
DEC E
DEC H
DEC HL
DEC IX
DEC IY
DEC L
DEC SP
DI
loop1:
DJNZ loop1
EI
EX (SP),HL
EX (SP),IX
EX (SP),IY
EX AF,AF'
EX DE,HL
EXX
HALT
IM 0
IM 1
IM 2
IN A,(C)
IN B,(C)
IN C,(C)
IN D,(C)
IN E,(C)
IN H,(C)
IN L,(C)
IN A,(port)
IN0 B,(n)
IN0 C,(n)
IN0 D,(n)
IN0 E,(n)
IN0 H,(n)
IN0 L,(n)
INC (HL)
INC (IX+offset)
INC (IY+offset)
INC A
INC B
INC BC
INC C
INC D
INC DE
INC E
INC H
INC HL
INC IX
INC IY
INC L
INC SP
IND
INDR
INI
INIR
JP addr16
JP (HL)
JP (IX)
JP (IY)
JP C,addr16
JP M,addr16
JP NC,addr16
JP NZ,addr16
JP P,addr16
JP PE,addr16
JP PO,addr16
JP Z,addr16
loop2:
JR C,loop2
JR NC,loop2
JR NZ,loop2
JR Z,loop2
JR loop2
LD (BC),A
LD (DE),A
LD (HL),A
LD (HL),B
LD (HL),C
LD (HL),D
LD (HL),E
LD (HL),H
LD (HL),L
LD (HL),n
LD (IX+offset),A
LD (IX+offset),B
LD (IX+offset),C
LD (IX+offset),D
LD (IX+offset),E
LD (IX+offset),H
LD (IX+offset),L
LD (IX+offset),n
LD (IY+offset),A
LD (IY+offset),B
LD (IY+offset),C
LD (IY+offset),D
LD (IY+offset),E
LD (IY+offset),H
LD (IY+offset),L
LD (IY+offset),n
LD (nn),A
LD (nn),BC
LD (nn),DE
LD (nn),HL
LD (nn),IX
LD (nn),IY
LD (nn),SP
LD A,(BC)
LD A,(DE)
LD A,(HL)
LD A,(IX+offset)
LD A,(IY+offset)
LD A,(nn)
LD A,A
LD A,B
LD A,C
LD A,D
LD A,E
LD A,H
LD A,I
LD A,L
LD A,n
LD A,R
LD B,(HL)
LD B,(IX+offset)
LD B,(IY+offset)
LD B,A
LD B,B
LD B,C
LD B,D
LD B,E
LD B,H
LD B,L
LD B,n
LD BC,(nn)
LD BC,nn
LD C,(HL)
LD C,(IX+offset)
LD C,(IY+offset)
LD C,A
LD C,B
LD C,C
LD C,D
LD C,E
LD C,H
LD C,L
LD C,n
LD D,(HL)
LD D,(IX+offset)
LD D,(IY+offset)
LD D,A
LD D,B
LD D,C
LD D,D
LD D,E
LD D,H
LD D,L
LD D,n
LD DE,(nn)
LD DE,nn
LD E,(HL)
LD E,(IX+offset)
LD E,(IY+offset)
LD E,A
LD E,B
LD E,C
LD E,D
LD E,E
LD E,H
LD E,L
LD E,n
LD H,(HL)
LD H,(IX+offset)
LD H,(IY+offset)
LD H,A
LD H,B
LD H,C
LD H,D
LD H,E
LD H,H
LD H,L
LD H,n
LD HL,(nn)
LD HL,nn
LD I,A
LD IX,(nn)
LD IX,nn
LD IY,(nn)
LD IY,nn
LD L,(HL)
LD L,(IX+offset)
LD L,(IY+offset)
LD L,A
LD L,B
LD L,C
LD L,D
LD L,E
LD L,H
LD L,L
LD L,n
LD R,A
LD SP,(nn)
LD SP,HL
LD SP,IX
LD SP,IY
LD SP,nn
LDD
LDDR
LDI
LDIR
MLT BC
MLT DE
MLT HL
MLT SP
NEG
NOP
OR (HL)
OR (IX+offset)
OR (IY+offset)
OR A
OR B
OR C
OR D
OR E
OR H
OR L
OR imm8
OTDR
OTIR
OUT (C),A
OUT (C),B
OUT (C),C
OUT (C),D
OUT (C),E
OUT (C),H
OUT (C),L
OUT (port),A
OUT0 (imm8),A
OUT0 (imm8),B
OUT0 (imm8),C
OUT0 (imm8),D
OUT0 (imm8),E
OUT0 (imm8),H
OUT0 (imm8),L
OUTD
OUTI
OTIM
OTDM
OTIMR
OTDMR
POP AF
POP BC
POP DE
POP HL
POP IX
POP IY
PUSH AF
PUSH BC
PUSH DE
PUSH HL
PUSH IX
PUSH IY
RES 0,(HL)
RES 0,(IX+offset)
RES 0,(IY+offset)
RES 0,A
RES 0,B
RES 0,C
RES 0,D
RES 0,E
RES 0,H
RES 0,L
RES 1,(HL)
RES 1,(IX+offset)
RES 1,(IY+offset)
RES 1,A
RES 1,B
RES 1,C
RES 1,D
RES 1,E
RES 1,H
RES 1,L
RES 2,(HL)
RES 2,(IX+offset)
RES 2,(IY+offset)
RES 2,A
RES 2,B
RES 2,C
RES 2,D
RES 2,E
RES 2,H
RES 2,L
RES 3,(HL)
RES 3,(IX+offset)
RES 3,(IY+offset)
RES 3,A
RES 3,B
RES 3,C
RES 3,D
RES 3,E
RES 3,H
RES 3,L
RES 4,(HL)
RES 4,(IX+offset)
RES 4,(IY+offset)
RES 4,A
RES 4,B
RES 4,C
RES 4,D
RES 4,E
RES 4,H
RES 4,L
RES 5,(HL)
RES 5,(IX+offset)
RES 5,(IY+offset)
RES 5,A
RES 5,B
RES 5,C
RES 5,D
RES 5,E
RES 5,H
RES 5,L
RES 6,(HL)
RES 6,(IX+offset)
RES 6,(IY+offset)
RES 6,A
RES 6,B
RES 6,C
RES 6,D
RES 6,E
RES 6,H
RES 6,L
RES 7,(HL)
RES 7,(IX+offset)
RES 7,(IY+offset)
RES 7,A
RES 7,B
RES 7,C
RES 7,D
RES 7,E
RES 7,H
RES 7,L
RET
RET C
RET M
RET NC
RET NZ
RET P
RET PE
RET PO
RET Z
RETI
RETN
RL (HL)
RL (IX+offset)
RL (IY+offset)
RL A
RL B
RL C
RL D
RL E
RL H
RL L
RLA
RLC (HL)
RLC (IX+offset)
RLC (IY+offset)
RLC A
RLC B
RLC C
RLC D
RLC E
RLC H
RLC L
RLCA
RLD
RR (HL)
RR (IX+offset)
RR (IY+offset)
RR A
RR B
RR C
RR D
RR E
RR H
RR L
RRA
RRC (HL)
RRC (IX+offset)
RRC (IY+offset)
RRC A
RRC B
RRC C
RRC D
RRC E
RRC H
RRC L
RRCA
RRD
RST 00H
RST 08H
RST 10H
RST 18H
RST 20H
RST 28H
RST 30H
RST 38H
SBC A,n
SBC A,(HL)
SBC A,(IX+offset)
SBC A,(IY+offset)
SBC A,A
SBC A,B
SBC A,C
SBC A,D
SBC A,E
SBC A,H
SBC A,L
SBC HL,BC
SBC HL,DE
SBC HL,HL
SBC HL,SP
SCF
SET 0,(HL)
SET 0,(IX+offset)
SET 0,(IY+offset)
SET 0,A
SET 0,B
SET 0,C
SET 0,D
SET 0,E
SET 0,H
SET 0,L
SET 1,(HL)
SET 1,(IX+offset)
SET 1,(IY+offset)
SET 1,A
SET 1,B
SET 1,C
SET 1,D
SET 1,E
SET 1,H
SET 1,L
SET 2,(HL)
SET 2,(IX+offset)
SET 2,(IY+offset)
SET 2,A
SET 2,B
SET 2,C
SET 2,D
SET 2,E
SET 2,H
SET 2,L
SET 3,(HL)
SET 3,(IX+offset)
SET 3,(IY+offset)
SET 3,A
SET 3,B
SET 3,C
SET 3,D
SET 3,E
SET 3,H
SET 3,L
SET 4,(HL)
SET 4,(IX+offset)
SET 4,(IY+offset)
SET 4,A
SET 4,B
SET 4,C
SET 4,D
SET 4,E
SET 4,H
SET 4,L
SET 5,(HL)
SET 5,(IX+offset)
SET 5,(IY+offset)
SET 5,A
SET 5,B
SET 5,C
SET 5,D
SET 5,E
SET 5,H
SET 5,L
SET 6,(HL)
SET 6,(IX+offset)
SET 6,(IY+offset)
SET 6,A
SET 6,B
SET 6,C
SET 6,D
SET 6,E
SET 6,H
SET 6,L
SET 7,(HL)
SET 7,(IX+offset)
SET 7,(IY+offset)
SET 7,A
SET 7,B
SET 7,C
SET 7,D
SET 7,E
SET 7,H
SET 7,L
SLA (HL)
SLA (IX+offset)
SLA (IY+offset)
SLA A
SLA B
SLA C
SLA D
SLA E
SLA H
SLA L
SLP
SRA (HL)
SRA (IX+offset)
SRA (IY+offset)
SRA A
SRA B
SRA C
SRA D
SRA E
SRA H
SRA L
SRL (HL)
SRL (IX+offset)
SRL (IY+offset)
SRL A
SRL B
SRL C
SRL D
SRL E
SRL H
SRL L
SUB (HL)
SUB (IX+offset)
SUB (IY+offset)
SUB A
SUB B
SUB C
SUB D
SUB E
SUB H
SUB L
SUB n
TST A
TST B
TST C
TST D
TST E
TST (HL)
TST n
XOR (HL)
XOR (IX+offset)
XOR (IY+offset)
XOR A
XOR B
XOR C
XOR D
XOR E
XOR H
XOR L
XOR n
end