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Support MBC CTCDART Board

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This commit is contained in:
Wayne Warthen
2022-01-22 14:40:17 -08:00
parent 52cd458e76
commit 79dc868e6e
6 changed files with 31 additions and 5 deletions
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2
Source/HBIOS/Config/MBC_std.asm
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@@ -37,3 +37,5 @@ PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
DSKYENABLE .SET FALSE ; ENABLES DSKY
DSKYMODE .SET DSKYMODE_NG ; DSKY VERSION: DSKYMODE_[V1|NG]
;
CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT

4
Source/HBIOS/cfg_mbc.asm
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@@ -49,7 +49,7 @@ CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY
CTCOSC .EQU (4915200/8) ; CTC CLOCK FREQUENCY
;
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
;
@@ -120,7 +120,7 @@ Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP

2
Source/HBIOS/ctc.asm
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@@ -101,7 +101,7 @@ CTC_PREINIT1:
; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE
; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
; IVT CORRESPOND TO CTC CHANNELS A-D.
LD A,0
LD A,INT_CTC0A * 2
OUT (CTCBASE),A ; SETUP CTC BASE INT VECTOR
;
; IN ORDER TO DIVIDE THE CTC INPUT CLOCK DOWN TO THE

24
Source/HBIOS/std.asm
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@@ -670,6 +670,28 @@ INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
; Z80-BASED SYSTEMS
#IF (PLATFORM == PLT_MBC)
;INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
;INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
;INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
;INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; MBC UART 0
INT_UART1 .EQU 5 ; MBC UART 1
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 13 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 14 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
;INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
;INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
;INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
;INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ELSE
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
@@ -683,6 +705,8 @@ INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#ENDIF
#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1

2
Source/ver.inc
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@@ -2,4 +2,4 @@
#DEFINE RMN 1
#DEFINE RUP 1
#DEFINE RTP 0
#DEFINE BIOSVER "3.1.1-pre.146"
#DEFINE BIOSVER "3.1.1-pre.147"

2
Source/ver.lib
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@@ -3,5 +3,5 @@ rmn equ 1
rup equ 1
rtp equ 0
biosver macro
db "3.1.1-pre.146"
db "3.1.1-pre.147"
endm