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Wayne Warthen
2022-01-22 14:40:17 -08:00
parent 52cd458e76
commit 79dc868e6e
6 changed files with 31 additions and 5 deletions
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24
Source/HBIOS/std.asm
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@@ -670,6 +670,28 @@ INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
; Z80-BASED SYSTEMS
#IF (PLATFORM == PLT_MBC)
;INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
;INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
;INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
;INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; MBC UART 0
INT_UART1 .EQU 5 ; MBC UART 1
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 13 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 14 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
;INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
;INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
;INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
;INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ELSE
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
@@ -683,6 +705,8 @@ INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#ENDIF
#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1