From b18dd28caf6d15159047b2d8b3f4bd4af40193bd Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Mon, 27 Jul 2020 18:24:42 -0700
Subject: [PATCH 1/8] Add configuration for Tiny Z80

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/HBIOS/Config/EZZ80_tz80.asm | 41 ++++++++++++++++++++++++++++++
 Source/HBIOS/Makefile              |  1 +
 Source/HBIOS/cfg_dyno.asm          |  2 ++
 Source/HBIOS/cfg_ezz80.asm         |  2 ++
 Source/HBIOS/cfg_master.asm        |  2 ++
 Source/HBIOS/cfg_mk4.asm           |  2 ++
 Source/HBIOS/cfg_n8.asm            |  2 ++
 Source/HBIOS/cfg_rcz180.asm        |  2 ++
 Source/HBIOS/cfg_rcz80.asm         |  2 ++
 Source/HBIOS/cfg_sbc.asm           |  2 ++
 Source/HBIOS/cfg_scz180.asm        |  2 ++
 Source/HBIOS/cfg_zeta.asm          |  2 ++
 Source/HBIOS/cfg_zeta2.asm         |  2 ++
 Source/HBIOS/hbios.asm             | 16 ++++++++++++
 14 files changed, 80 insertions(+)
 create mode 100644 Source/HBIOS/Config/EZZ80_tz80.asm

diff --git a/Source/HBIOS/Config/EZZ80_tz80.asm b/Source/HBIOS/Config/EZZ80_tz80.asm
new file mode 100644
index 00000000..93a45e94
--- /dev/null
+++ b/Source/HBIOS/Config/EZZ80_tz80.asm
@@ -0,0 +1,41 @@
+;
+;==================================================================================================
+;   EASY Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "TINYZ80"
+;
+#include "cfg_ezz80.asm"
+;
+CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+EIPCENABLE	.SET	TRUE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+CTCBASE		.SET	$10		; CTC BASE I/O ADDRESS
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDPORT		.SET	$6E		; STATUS LED PORT ADDRESS
+SIO0BASE	.SET	$18		; SIO 0: REGISTERS BASE ADR
+IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS
diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile
index 6ee90216..294ddf1a 100644
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -3,6 +3,7 @@ OBJECTS =
 ifeq (1,1)
 OBJECTS += DYNO_std.rom DYNO_std.com
 OBJECTS += EZZ80_std.rom EZZ80_std.com
+OBJECTS += EZZ80_tz80.rom EZZ80_tz80.com
 OBJECTS += MK4_std.rom MK4_std.com
 OBJECTS += N8_std.rom N8_std.com
 OBJECTS += RCZ180_ext.rom RCZ180_ext.com
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 3a073290..41c41471 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -154,3 +154,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 9036a113..20e9c5ef 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -169,3 +169,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 53f062fd..17a84abc 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -230,3 +230,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 630b47f1..e8f9da73 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -184,3 +184,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index 65db812a..6e60cd26 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -184,3 +184,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index a221334a..5f6c0354 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -179,3 +179,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 9a078f5c..de1476f4 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -184,3 +184,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 482fe08c..0e83b015 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -185,3 +185,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 0450a6a6..77f06047 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -175,3 +175,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 75ddc039..f13aeb61 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -133,3 +133,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 1582373c..a91ad204 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -138,3 +138,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 6e696cb6..40b0d392 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -860,6 +860,22 @@ HB_START:
 ;
 #ENDIF
 ;
+#IF (EIPCENABLE)
+	LD	A,$7B			; CLEAR WDTE BIT (DISABLE WATCHDOG)
+	OUT	($F0),A
+	LD	A,$B1			; DISABLE WDT - SECOND KEY
+	OUT 	($F1),A
+	LD	A,$00			; SET SYSTEM CONTROL REGISTER POINTER
+					; (SCRP) TO POINT TO WAIT STATE
+	OUT	($EE),A			; CONTROL REGISTER (WCR)
+	LD	A,$00			; NO WAIT STATES
+	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
+	LD	A,$03			; SET SCRP TO POINT TO MISCELLANEOUS
+	OUT	($EE),A			; CONTROL REGISTER (MCR)
+	LD	A,$10			; DIVIDE CLOCK BY 1, /CS0 DISABLE
+	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
+#ENDIF
+;
 #IF (MEMMGR == MM_Z2)
 	; SET PAGING REGISTERS
 #IFDEF ROMBOOT

From b4713fa3ff081770f87eb8f7b6ffb12615d08bb2 Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Mon, 27 Jul 2020 18:26:53 -0700
Subject: [PATCH 2/8] Add Tiny Z80 image file name

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/Doc/GettingStarted.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Source/Doc/GettingStarted.md b/Source/Doc/GettingStarted.md
index ba84859b..c3d486d7 100644
--- a/Source/Doc/GettingStarted.md
+++ b/Source/Doc/GettingStarted.md
@@ -153,6 +153,7 @@ the appropriate ROM image for your hardware.
 | RC Z180\*      | RCZ180_ext.rom           | 115200      | RC2014 w/ Z180 CPU & 512K banked RAM/ROM module  |
 | RC Z180\*      | RCZ180_nat.rom           | 115200      | RC2014 w/ Z180 CPU & 512K native RAM/ROM module  |
 | Easy Z80       | EZZ80_std.rom            | 115200      | Sergey Kiselev's Easy Z80                        |
+| Tiny Z80       | EZZ80_tz80.rom           | 115200      | Sergey Kiselev's Tiny Z80                        |
 | SC126          | SCZ180_126.rom           | 115200      | Stephen Cousin's SC126 Z180                      |
 | SC130          | SCZ180_130.rom           | 115200      | Stephen Cousin's SC130 Z180                      |
 | SC131          | SCZ180_131.rom           | 115200      | Stephen Cousin's SC131 Z180                      |
@@ -1218,4 +1219,4 @@ RetroBrew Computers projects is via the community forums:
 
 Submission of issues and bugs are welcome at the [RomWBW GitHub Repository](https://github.com/wwarthen/RomWBW).
 
-Also feel free to email !author at [!authmail](mailto:!authmail).
\ No newline at end of file
+Also feel free to email !author at [!authmail](mailto:!authmail).

From f482801b94aac5d3e8ce2a625446befc906ef769 Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Sat, 1 Aug 2020 13:24:13 -0700
Subject: [PATCH 3/8] Add definitions for Z80 EIPC / Z84C15

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/HBIOS/eipc.inc | 75 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 Source/HBIOS/eipc.inc

diff --git a/Source/HBIOS/eipc.inc b/Source/HBIOS/eipc.inc
new file mode 100644
index 00000000..24519d62
--- /dev/null
+++ b/Source/HBIOS/eipc.inc
@@ -0,0 +1,75 @@
+;
+; Z80 EIPC (Z84C15) REGISTERS
+;
+EIPC_SCRP	.EQU	$EE		; SYSTEM CONTROL REGISTER POINTER
+EIPC_SCDP	.EQU	$EF		; SYSTEM CONTROL DATA PORT
+EIPC_WDTMR	.EQU	$F0		; WATCHDOG TIMER MASTER REGISTER
+EIPC_WDTCR	.EQU	$F1		; WATCHDOG TIMER COMMAND REGISTER
+EIPC_INTPR	.EQU	$F4		; INTERRUPT PRIORITY REGISTER
+;
+; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP)
+;
+EIPC_WCR	.EQU	$00		; WAIT STATE CONTROL REGISTER
+EIPC_MWBR	.EQU	$01		; MEMORY WAIT BOUNDARY REGISTER
+EIPC_CSBR	.EQU	$02		; CHIP SELECT BOUNDARY REGISTER
+EIPC_MCR	.EQU	$03		; MISCELLANEOUS CONTROL REGISTER
+;
+; WAIT STATE VALUES (FOR EIPC_WCR)
+;
+EIPC_IO_0WS	.EQU	$00		; NO (ZERO) I/O WAIT STATES
+EIPC_IO_2WS	.EQU	$01		; 2 I/O WAIT STATES
+EIPC_IO_4WS	.EQU	$02		; 4 I/O WAIT STATES
+EIPC_IO_6WS	.EQU	$03		; 6 I/O WAIT STATES
+EIPC_MEM_OWS	.EQU	$00		; NO (ZERO) MEMORY WAIT STATES
+EIPC_MEM_1WS	.EQU	$04		; 1 MEMORY WAIT STATE
+EIPC_MEM_1WS	.EQU	$08		; 2 MEMORY WAIT STATES
+EIPC_MEM_1WS	.EQU	$0C		; 3 MEMORY WAIT STATES
+EIPC_OCF_0WS	.EQU	$00		; NO ADDITIONAL WAIT ON OP-CODE FETCH
+EIPC_OCF_1WS	.EQU	$10		; +1 WAIT STATE ON OP-CODE FETCH
+EIPC_INT_0WS	.EQU	$00		; NO WAIT ON INTERRUPT VECTOR READ
+EIPC_INT_1WS	.EQU	$20		; 1 WAIT STATE ON INT. VECTOR READ
+EIPC_CHAIN_0WS	.EQU	$00		; 0 WAIT ON INT ACK. / 0 WAIT ON RETI
+EIPC_CHAIN_2WS	.EQU	$40		; 2 WAIT ON INT ACK. / 0 WAIT ON RETI
+EIPC_CHAIN_4WS	.EQU	$80		; 4 WAIT ON INT ACK. / 2 WAIT ON RETI
+EIPC_CHAIN_6WS	.EQU	$C0		; 6 WAIT ON INT ACK. / 4 WAIT ON RETI
+;
+; MISCELLANEOUS CONTROL REGISTER VALUES
+;
+EIPC_CS0_DIS	.EQU	$00		; DISABLE /CS0
+EIPC_CS0_ENA	.EQU	$01		; ENABLE /CS0
+EIPC_CS1_DIS	.EQU	$00		; DISABLE /CS1
+EIPC_CS1_ENA	.EQU	$02		; ENABLE /CS1
+EIPC_32CRC_DIS	.EQU	$00		; DISABLE 32-BIT CRC FOR SIO CHANNEL A
+EIPC_32CRC_ENA	.EQU	$04		; ENABLE 32-BIT CRC FOR SIO CHANNEL A
+EIPC_RSTOUT_DIS	.EQU	$08		; DISABLE RESET OUTPUT
+EIPC_RSTOUT_ENA	.EQU	$00		; ENABLE RESET OUTPUT
+EIPC_CLKDIV1	.EQU	$10		; DIVIDE XTAL/CGC CLOCK BY ONE
+EIPC_CLKDIV2	.EQU	$00		; DIVIDE XTAL/CGC CLOCK BY TWO
+;
+; WATCHDOG TIMER MASTER REGISTER VALUES
+;
+EIPC_WDT_CONST	.EQU	$03		; MUST SET LOWER THREE BITS TO 011
+EIPC_HALT_IDLE1 .EQU	$00		; HALT / POWER DOWN MODE - IDLE 1 MODE
+EIPC_HALT_IDLE2 .EQU	$08		; HALT / POWER DOWN MODE - IDLE 2 MODE
+EIPC_HALT_STOP	.EQU	$10		; HALT / POWER DOWN MODE - STOP MODE
+EIPC_HALT_RUN	.EQU	$18		; HALT / POWER DOWN MODE - RUN MODE
+EIPC_WDT_P2_16	.EQU	$00		; SET WATCHDOG PERIOD TO TOC * 2^16
+EIPC_WDT_P2_18	.EQU	$20		; SET WATCHDOG PERIOD TO TOC * 2^18
+EIPC_WDT_P2_20	.EQU	$40		; SET WATCHDOG PERIOD TO TOC * 2^20
+EIPC_WDT_P2_22	.EQU	$60		; SET WATCHDOG PERIOD TO TOC * 2^22
+EIPC_WDTE	.EQU	$80		; ENABLE WATCHDOG TIMER
+;
+; WATCHDOG TIMER COMMAND REGISTER VALUES
+; 
+EIPC_DIS_WDT	.EQU	$B1		; DISABLE WATCHDOG TIMER
+EIPC_CLR_WDT	.EQU	$4E		; CLEAR WATCHDOG TIMER
+EIPC_HLT_MODE	.EQU	$DB		; CHANGE HALT MODE
+;
+; INTERRUPT PRIORITY REGISTER VALUES
+;
+EIPC_CTC_SIO_PIO	.EQU	$00	; PRIORITY HIGH TO LOW: CTC, SIO, PIO
+EIPC_SIO_CTC_PIO	.EQU	$01	; PRIORITY HIGH TO LOW: SIO, CTC, PIO
+EIPC_CTC_PIO_SIO	.EQU	$02	; PRIORITY HIGH TO LOW: CTC, PIO, SIO
+EIPC_PIO_SIO_CTC	.EQU	$03	; PRIORITY HIGH TO LOW: PIO, SIO, CTC
+EIPC_PIC_CTC_SIO	.EQU	$04	; PRIORITY HIGH TO LOW: PIO, CTC, SIO
+EIPC_SIO_PIO_CTC	.EQU	$05	; PRIORITY HIGH TO LOW: SIO, PIO, CTC

From 78cd69e34d210fd1d91bed4e8f8d7e1aa44ec9cd Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Sat, 1 Aug 2020 13:24:43 -0700
Subject: [PATCH 4/8] Use definitions for Z80 EIPC / Z84C15

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/HBIOS/hbios.asm | 24 ++++++++++++------------
 Source/HBIOS/std.asm   |  3 +++
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 40b0d392..4e9a5f8a 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -861,19 +861,19 @@ HB_START:
 #ENDIF
 ;
 #IF (EIPCENABLE)
-	LD	A,$7B			; CLEAR WDTE BIT (DISABLE WATCHDOG)
-	OUT	($F0),A
-	LD	A,$B1			; DISABLE WDT - SECOND KEY
-	OUT 	($F1),A
-	LD	A,$00			; SET SYSTEM CONTROL REGISTER POINTER
+	LD	A,(EIPC_WDT_CONST | EIPC_HALT_RUN | EIPC_WDT_P2_22)
+	OUT	(EIPC_WDTMR),A		; CLEAR WDTE BIT (DISABLE WATCHDOG)
+	LD	A,EIPC_DIS_WDT		; DISABLE WDT - SECOND KEY
+	OUT 	(EIPC_WDTCR),A
+	LD	A,EIPC_WCR		; SET SYSTEM CONTROL REGISTER POINTER
 					; (SCRP) TO POINT TO WAIT STATE
-	OUT	($EE),A			; CONTROL REGISTER (WCR)
-	LD	A,$00			; NO WAIT STATES
-	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
-	LD	A,$03			; SET SCRP TO POINT TO MISCELLANEOUS
-	OUT	($EE),A			; CONTROL REGISTER (MCR)
-	LD	A,$10			; DIVIDE CLOCK BY 1, /CS0 DISABLE
-	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
+	OUT	(EIPC_SCRP),A		; CONTROL REGISTER (WCR)
+	LD	A,(EIPC_IO_0WS | EIPC_MEM_OWS | EIPC_OCF_0WS | EIPC_INT_0WS | EIPC_CHAIN_0WS)
+	OUT	(EIPC_SCDP),A		; NO WAIT STATES
+	LD	A,EIPC_MCR		; SET SCRP TO POINT TO MISCELLANEOUS
+	OUT	(EIPC_SCRP),A		; CONTROL REGISTER (MCR)
+	LD	A,EIPC_CLKDIV1		; DIVIDE CLOCK BY 1, /CS0 DISABLE
+	OUT	(EIPC_SCDP),A		; SET SYSTEM CONTROL DATA PORT (SCDP)
 #ENDIF
 ;
 #IF (MEMMGR == MM_Z2)
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index f0aa880d..9a51672a 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -327,6 +327,9 @@ FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
   #IF (CPUFAM == CPU_Z180)
     #INCLUDE "z180.inc"
   #ENDIF
+  #IF (EIPCENABLE)
+    #INCLUDE "eipc.inc"
+  #ENDIF
 #ENDIF
 ;
 ; SETUP DEFAULT CPU SPEED VALUES

From f078b98c5d7a77998683492a683deefec8b3fd2b Mon Sep 17 00:00:00 2001
From: mlukasek <martin@lukasek.cz>
Date: Sat, 10 Oct 2020 02:54:29 +0200
Subject: [PATCH 5/8] EIPC_MEM_xWS values corrected

---
 Source/HBIOS/eipc.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Source/HBIOS/eipc.inc b/Source/HBIOS/eipc.inc
index 24519d62..6497e63d 100644
--- a/Source/HBIOS/eipc.inc
+++ b/Source/HBIOS/eipc.inc
@@ -22,8 +22,8 @@ EIPC_IO_4WS	.EQU	$02		; 4 I/O WAIT STATES
 EIPC_IO_6WS	.EQU	$03		; 6 I/O WAIT STATES
 EIPC_MEM_OWS	.EQU	$00		; NO (ZERO) MEMORY WAIT STATES
 EIPC_MEM_1WS	.EQU	$04		; 1 MEMORY WAIT STATE
-EIPC_MEM_1WS	.EQU	$08		; 2 MEMORY WAIT STATES
-EIPC_MEM_1WS	.EQU	$0C		; 3 MEMORY WAIT STATES
+EIPC_MEM_2WS	.EQU	$08		; 2 MEMORY WAIT STATES
+EIPC_MEM_3WS	.EQU	$0C		; 3 MEMORY WAIT STATES
 EIPC_OCF_0WS	.EQU	$00		; NO ADDITIONAL WAIT ON OP-CODE FETCH
 EIPC_OCF_1WS	.EQU	$10		; +1 WAIT STATE ON OP-CODE FETCH
 EIPC_INT_0WS	.EQU	$00		; NO WAIT ON INTERRUPT VECTOR READ

From 705e1944c9eb996e4b78916ab7ca4892368c9942 Mon Sep 17 00:00:00 2001
From: Cocoacrumbs <kvnieuwe@telenet.be>
Date: Sat, 23 Jan 2021 15:38:41 +0100
Subject: [PATCH 6/8] Fix for multiple definition of 'verbose' in
 RomWBW/Tools/unix/uz80as/uz80as.h

---
 Tools/unix/uz80as/uz80as.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Tools/unix/uz80as/uz80as.h b/Tools/unix/uz80as/uz80as.h
index 511da085..19e71764 100644
--- a/Tools/unix/uz80as/uz80as.h
+++ b/Tools/unix/uz80as/uz80as.h
@@ -8,7 +8,7 @@
 #ifndef UZ80AS_H
 #define UZ80AS_H
 
-int verbose;
+static int verbose;
 
 /* matchtab.flags */
 enum {

From d3d59d6922a748b399f992c2bf7872406bb5fe4b Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sat, 23 Jan 2021 09:02:12 -0800
Subject: [PATCH 7/8] Update commit.yml

---
 .github/workflows/commit.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index 7cdbe1a0..088fca37 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -13,7 +13,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-      - uses: rlespinasse/github-slug-action@1.1.0
+      - uses: rlespinasse/github-slug-action@v3.x
         
       - uses: actions/checkout@v2
           
@@ -28,4 +28,4 @@ jobs:
         uses: actions/upload-artifact@v1
         with:
           name: RomWBW-${{env.GITHUB_REF_SLUG}}-${{env.GITHUB_SHA_SHORT}}
-          path: .
\ No newline at end of file
+          path: .

From 8a7bc97fea27bf10a23c61ee508522a60e2909c6 Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sat, 30 Jan 2021 18:46:03 -0800
Subject: [PATCH 8/8] Update commit.yml

Trying to get GitHub build scripts to use Pacific Time Zone.
---
 .github/workflows/commit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index 088fca37..689e14c1 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -19,6 +19,7 @@ jobs:
           
       - name: Build
         run: |
+          export TZ='America/Los_Angeles'
           sudo apt-get install libncurses-dev
           make
           make clean