From 7e2b2b8f40be5dd319461f0b480982b8aa4025eb Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sun, 4 Aug 2024 13:39:44 -0700
Subject: [PATCH] Implement SIOINTS Setting in SIO Driver

- SIOINTS allows disabling use of interrupts in the SIO driver when interrupts are enabled globally.  It will not allow you to enable SIO interrupts if interrupts are globally disabled (INTMODE 0).
---
 Source/HBIOS/cfg_duo.asm      |   1 +
 Source/HBIOS/cfg_dyno.asm     |   1 +
 Source/HBIOS/cfg_epitx.asm    |   1 +
 Source/HBIOS/cfg_fz80.asm     |   1 +
 Source/HBIOS/cfg_heath.asm    |   1 +
 Source/HBIOS/cfg_master.asm   |   1 +
 Source/HBIOS/cfg_mbc.asm      |   1 +
 Source/HBIOS/cfg_mk4.asm      |   1 +
 Source/HBIOS/cfg_mon.asm      |   1 +
 Source/HBIOS/cfg_n8.asm       |   1 +
 Source/HBIOS/cfg_nabu.asm     |   1 +
 Source/HBIOS/cfg_rcz180.asm   |   1 +
 Source/HBIOS/cfg_rcz280.asm   |   1 +
 Source/HBIOS/cfg_rcz80.asm    |   1 +
 Source/HBIOS/cfg_s100.asm     |   1 +
 Source/HBIOS/cfg_sbc.asm      |   1 +
 Source/HBIOS/cfg_scz180.asm   |   1 +
 Source/HBIOS/cfg_z80retro.asm |   1 +
 Source/HBIOS/sio.asm          | 137 +++++++++++++++++-----------------
 19 files changed, 87 insertions(+), 68 deletions(-)

diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm
index e7fd9b81..ac440660 100644
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -169,6 +169,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 74e7be03..0ddc8c08 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -183,6 +183,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_epitx.asm b/Source/HBIOS/cfg_epitx.asm
index 27c372ad..acc5efdc 100644
--- a/Source/HBIOS/cfg_epitx.asm
+++ b/Source/HBIOS/cfg_epitx.asm
@@ -185,6 +185,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_fz80.asm b/Source/HBIOS/cfg_fz80.asm
index 8b365710..e2da9217 100644
--- a/Source/HBIOS/cfg_fz80.asm
+++ b/Source/HBIOS/cfg_fz80.asm
@@ -188,6 +188,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm
index 328151dd..06e2e75a 100644
--- a/Source/HBIOS/cfg_heath.asm
+++ b/Source/HBIOS/cfg_heath.asm
@@ -188,6 +188,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index f9800fb8..27cfffa2 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -227,6 +227,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm
index cde1fd91..10551bd8 100644
--- a/Source/HBIOS/cfg_mbc.asm
+++ b/Source/HBIOS/cfg_mbc.asm
@@ -166,6 +166,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 95b67f02..2b65a9c8 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -176,6 +176,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_mon.asm b/Source/HBIOS/cfg_mon.asm
index b6c4e8eb..65564ab9 100644
--- a/Source/HBIOS/cfg_mon.asm
+++ b/Source/HBIOS/cfg_mon.asm
@@ -183,6 +183,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index eebd6674..ef92f4af 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -178,6 +178,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm
index eafbf833..e19bf2ae 100644
--- a/Source/HBIOS/cfg_nabu.asm
+++ b/Source/HBIOS/cfg_nabu.asm
@@ -188,6 +188,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 8a53da51..97aea416 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -189,6 +189,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 06c81258..4841795e 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -193,6 +193,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 0df87842..bc22d90c 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -188,6 +188,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm
index 11307e32..b96ca7ea 100644
--- a/Source/HBIOS/cfg_s100.asm
+++ b/Source/HBIOS/cfg_s100.asm
@@ -183,6 +183,7 @@ SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 5d0328c8..4ea037e3 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -166,6 +166,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 62072993..b68d0545 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -183,6 +183,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm
index 973d0d75..09a7f6ce 100644
--- a/Source/HBIOS/cfg_z80retro.asm
+++ b/Source/HBIOS/cfg_z80retro.asm
@@ -169,6 +169,7 @@ SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
 SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
 SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
 SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
 SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
 SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 0274a66e..c7e23e01 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -24,13 +24,13 @@ SIO_SIO		.EQU	1
 SIO_RTSON	.EQU	$EA
 SIO_RTSOFF	.EQU	$E8
 ;
-#IF (INTMODE == 0)
-SIO_WR1VAL	.EQU	$00		; WR1 VALUE FOR NO INTS
-#ELSE
+#IF ((SIOINTS) & (INTMODE > 0))
 SIO_WR1VAL	.EQU	$18		; WR1 VALUE FOR INT ON RECEIVED CHARS
+#ELSE
+SIO_WR1VAL	.EQU	$00		; WR1 VALUE FOR NO INTS
 #ENDIF
 ;
-#IF ((INTMODE == 2) | (INTMODE == 3))
+#IF ((SIOINTS) & (INTMODE >= 2))
 ;
 SIO0_IVT	.EQU	IVT(INT_SIO0)
 SIO1_IVT	.EQU	IVT(INT_SIO1)
@@ -146,7 +146,7 @@ SIO_PREINIT2:
 	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
 	DJNZ	SIO_PREINIT0		; LOOP UNTIL DONE
 ;
-#IF (INTMODE >= 1)
+#IF ((SIOINTS) & (INTMODE > 0))
 	; SETUP INT VECTORS AS APPROPRIATE
 	LD	A,(SIO_DEV)		; GET DEVICE COUNT
 	OR	A			; SET FLAGS
@@ -223,7 +223,7 @@ SIO_INIT1:
 ;
 ; RECEIVE INTERRUPT HANDLER
 ;
-#IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 ; IM1 ENTRY POINT
 ;
@@ -354,17 +354,7 @@ SIO_FNTBL:
 ;
 ;
 ;
-#IF (INTMODE == 0)
-;
-SIO_IN:
-	CALL	SIO_IST			; CHAR WAITING?
-	JR	Z,SIO_IN		; LOOP IF NOT
-	LD	C,(IY+4)		; DATA PORT
-	IN	E,(C)			; GET CHAR
-	XOR	A			; SIGNAL SUCCESS
-	RET
-;
-#ELSE
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 SIO_IN:
 	CALL	SIO_IST			; SEE IF CHAR AVAILABLE
@@ -411,6 +401,17 @@ SIO_IN2:
 	HB_EI				; INTERRUPTS OK AGAIN
 	XOR	A			; SIGNAL SUCCESS
 	RET				; AND DONE
+;
+#ELSE
+;
+SIO_IN:
+	CALL	SIO_IST			; CHAR WAITING?
+	JR	Z,SIO_IN		; LOOP IF NOT
+	LD	C,(IY+4)		; DATA PORT
+	IN	E,(C)			; GET CHAR
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
 #ENDIF
 ;
 ;
@@ -425,7 +426,17 @@ SIO_OUT:
 ;
 ;
 ;
-#IF (INTMODE == 0)
+#IF ((SIOINTS) & (INTMODE > 0))
+;
+SIO_IST:
+	LD	L,(IY+7)		; GET ADDRESS
+	LD	H,(IY+8)		; ... OF RECEIVE BUFFER
+	LD	A,(HL)			; BUFFER UTILIZATION COUNT
+	OR	A			; SET FLAGS
+	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
+	RET
+;
+#ELSE
 ;
 SIO_IST:
 	LD	C,(IY+3)		; CMD PORT
@@ -438,16 +449,6 @@ SIO_IST:
 	INC	A			; ASCCUM := 1 TO SIGNAL 1 CHAR WAITING
 	RET				; DONE
 ;
-#ELSE
-;
-SIO_IST:
-	LD	L,(IY+7)		; GET ADDRESS
-	LD	H,(IY+8)		; ... OF RECEIVE BUFFER
-	LD	A,(HL)			; BUFFER UTILIZATION COUNT
-	OR	A			; SET FLAGS
-	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	RET
-;
 #ENDIF
 ;
 ;
@@ -853,7 +854,7 @@ SIO_INITGO:
 ;
 ; SET INTERRUPT VECTOR OFFSET WR2
 ;
-#IF ((INTMODE == 2) | (INTMODE == 3))
+#IF ((SIOINTS) & (INTMODE >= 2))
 	LD	A,(IY+2)		; CHIP / CHANNEL
 	SRL	A			; SHIFT AWAY CHANNEL BIT
 	LD	L,SIO0_VEC		; ASSUME CHIP 0
@@ -893,7 +894,7 @@ SIO_INITPRT:
 	LD	B,SIO_INITLEN		; COUNT OF BYTES TO WRITE
 	OTIR				; WRITE ALL VALUES
 ;
-#IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 	; RESET THE RECEIVE BUFFER
 	LD	E,(IY+7)
@@ -1108,17 +1109,7 @@ SIO_STR_SIO	.DB	"SIO$"
 SIO_DEV		.DB	0		; DEVICE NUM USED DURING INIT
 SIO_MAP		.DB	0		; CHIP PRESENCE BITMAP
 ;
-#IF (INTMODE == 0)
-;
-SIO0A_RCVBUF	.EQU	0
-SIO0B_RCVBUF	.EQU	0
-;
-  #IF (SIOCNT >= 2)
-SIO1A_RCVBUF	.EQU	0
-SIO1B_RCVBUF	.EQU	0
-  #ENDIF
-;
-#ELSE
+#IF ((SIOINTS) & (INTMODE > 0))
 ;
 ; SIO0 CHANNEL A RECEIVE BUFFER
 SIO0A_RCVBUF:
@@ -1152,6 +1143,16 @@ SIO1B_BUF	.FILL	SIO_BUFSZ,0	; RECEIVE RING BUFFER
 ;
   #ENDIF
 ;
+#ELSE
+;
+SIO0A_RCVBUF	.EQU	0
+SIO0B_RCVBUF	.EQU	0
+;
+  #IF (SIOCNT >= 2)
+SIO1A_RCVBUF	.EQU	0
+SIO1B_RCVBUF	.EQU	0
+  #ENDIF
+;
 #ENDIF
 ;
 ; SIO PORT TABLE
@@ -1191,9 +1192,9 @@ SIO0A_CFG:
 	DEVECHO	", IO="
 	DEVECHO	SIO0BASE
 	DEVECHO	", CHANNEL A"
-  #IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
-  #ENDIF
+#ENDIF
 		DEVECHO	"\n"
 ;
 SIO_CFGSIZ	.EQU	$ - SIO_CFG	; SIZE OF ONE CFG TABLE ENTRY
@@ -1231,9 +1232,9 @@ SIO0B_CFG:
 	DEVECHO	", IO="
 	DEVECHO	SIO0BASE
 	DEVECHO	", CHANNEL B"
-  #IF (INTMODE > 0)
+#IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
-  #ENDIF
+#ENDIF
 		DEVECHO	"\n"
 ;
 #IF (SIOCNT >= 2)
@@ -1253,26 +1254,26 @@ SIO1A_CFG:
 	.DB	SIO1MODE		; MODE
 ;
 	DEVECHO	"SIO MODE="
-#IF (SIO1MODE == SIOMODE_STD)
+  #IF (SIO1MODE == SIOMODE_STD)
 	DEVECHO	"STD"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_RC)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_RC)
 	DEVECHO	"RC"
-#ENDIF	
-
-#IF (SIO1MODE == SIOMODE_SMB)
+  #ENDIF	
+;
+  #IF (SIO1MODE == SIOMODE_SMB)
 	DEVECHO	"SMB"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_ZP)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_ZP)
 	DEVECHO	"ZP"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_Z80R)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_Z80R)
 	DEVECHO	"Z80R"
-#ENDIF
+  #ENDIF
 	DEVECHO	", IO="
 	DEVECHO	SIO1BASE
 	DEVECHO	", CHANNEL A"
-  #IF (INTMODE > 0)
+  #IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
   #ENDIF
 		DEVECHO	"\n"
@@ -1292,25 +1293,25 @@ SIO1B_CFG:
 	.DB	SIO1MODE		; MODE
 ;
 	DEVECHO	"SIO MODE="
-#IF (SIO1MODE == SIOMODE_STD)
+  #IF (SIO1MODE == SIOMODE_STD)
 	DEVECHO	"STD"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_RC)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_RC)
 	DEVECHO	"RC"
-#ENDIF	
-#IF (SIO1MODE == SIOMODE_SMB)
+  #ENDIF	
+  #IF (SIO1MODE == SIOMODE_SMB)
 	DEVECHO	"SMB"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_ZP)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_ZP)
 	DEVECHO	"ZP"
-#ENDIF
-#IF (SIO1MODE == SIOMODE_Z80R)
+  #ENDIF
+  #IF (SIO1MODE == SIOMODE_Z80R)
 	DEVECHO	"Z80R"
-#ENDIF
+  #ENDIF
 	DEVECHO	", IO="
 	DEVECHO	SIO1BASE
 	DEVECHO	", CHANNEL B"
-  #IF (INTMODE > 0)
+  #IF ((SIOINTS) & (INTMODE > 0))
 		DEVECHO	", INTERRUPTS ENABLED"
   #ENDIF
 		DEVECHO	"\n"