From dc6ecfd9e3fbad91593439867a4fa8376e675777 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 17 Nov 2019 17:35:11 -0800 Subject: [PATCH 1/9] CP/M 3 Support in ASSIGN --- Source/Apps/Assign.asm | 178 ++++++++++++++++++++++++++++++++++++++++- Source/CBIOS/cbios.asm | 6 +- Source/HBIOS/hbios.asm | 11 ++- 3 files changed, 190 insertions(+), 5 deletions(-) diff --git a/Source/Apps/Assign.asm b/Source/Apps/Assign.asm index 129de63d..e76adab7 100644 --- a/Source/Apps/Assign.asm +++ b/Source/Apps/Assign.asm @@ -21,11 +21,13 @@ ; 2016-03-21 [WBW] Updated for HBIOS 2.8 ; 2016-04-08 [WBW] Determine key memory addresses dynamically ; 2019-08-07 [WBW] Fixed DPB selection error +; 2019-11-17 [WBW] Added preliminary CP/M 3 support ;_______________________________________________________________________________ ; ; ToDo: ; 1) Do something to prevent assigning slices when device does not support them ; 2) ASSIGN C: causes drive map to be reinstalled unnecessarily +; 3) Need to find a way to verify RomWBW under CP/M 3 ;_______________________________________________________________________________ ; ;=============================================================================== @@ -47,6 +49,19 @@ rmn .equ 9 ; CBIOS version - minor ;=============================================================================== ; .org $100 +; + ; relocate to high memory + ld hl,image + ld de,$8000 + ld bc,modsize + ldir + jp start +; +image .equ $ +; + .org $8000 +; +start: ; ; setup stack (save old value) ld (stksav),sp ; save stack @@ -84,6 +99,14 @@ init: ld de,-3 ; adjustment for start of table add hl,de ; HL now has start of table ld (bioloc),hl ; save it +; + ; get CP/M version and save it + ld c,$0C ; function number + call bdos ; do it, HL := version + ld (cpmver),hl ; save it + ld a,l ; low byte + cp $30 ; CP/M 3.0? + jp nc,initcpm3 ; handle CP/M 3.0 or greater ; ; get location of config data and verify integrity ld hl,stamp ; HL := adr or RomWBW zero page stamp @@ -193,6 +216,66 @@ initx: xor a ; signal success ret ; return ; +; CP/M 3 initialization +; +initcpm3: + ld hl,(bioloc) + ld de,22*3 ; offset of DRVTBL func + add hl,de ; HL := DRVTBL func + call jphl ; do it, HL := DRVTBL adr + ld (drvtbl),hl ; save it +; + ; switch to sysbnk + ld hl,(bioloc) + ld de,27*3 ; offset of SELMEM func + add hl,de ; HL := SELMEM func + ld a,0 ; bank 0 is system bank + call jphl +; + ; copy CP/M 3 drvtbl to drvmap working copy + ld hl,(drvtbl) ; get drive table in HL + ld de,mapwrk ; DE := working drive map + ld b,16 +initc2: + push hl ; save drvtbl entry adr + ld a,(hl) ; deref HL to get DPH adr + inc hl ; ... + ld h,(hl) ; ... + ld l,a ; ... + ld a,l ; check for + or h ; ... zero + jr nz,initc3 ; if not zero, copy entry + inc de ; ... else bump past unit field + jr initc4 ; ... and continue without copying +initc3: + dec hl ; back up to + dec hl ; ... unit + ld a,(hl) ; get unit from drvtbl + ld (de),a ; save unit to drvmap + inc hl ; bump to slice + inc de ; bump to slice + ld a,(hl) ; get slice from drvtbl + ld (de),a ; save slice to drvmap +initc4: + inc de ; bump past slice + inc de ; skip + inc de ; ... dph + pop hl ; back to drvtbl entry + inc hl ; bump to + inc hl ; ... next drvtbl entry + djnz initc2 +; + ; switch back to tpabnk + ld hl,(bioloc) + ld de,27*3 ; offset of SELMEM func + add hl,de ; HL := SELMEM func + ld a,1 ; bank 1 is tpa bank + call jphl +; + ; return success + xor a ; signal success + ret ; return +; ; Process command line ; process: @@ -374,6 +457,10 @@ devlstu1: ; Install the new drive map into CBIOS ; install: + ld a,(cpmver) ; low byte of CP/M version + cp $30 ; CP/M 3.0? + jp nc,instcpm3 ; handle CP/M 3.0 or greater +; ; capture CBIOS snapshot and stack frame for error recovery ld hl,(bioloc) ; start of CBIOS ld de,$8000 ; save it here @@ -625,6 +712,90 @@ makdph3: xor a ; signal success ret ; +; +; +instcpm3: +; + ; switch to sysbnk + ld hl,(bioloc) + ld de,27*3 ; offset of SELMEM func + add hl,de ; HL := SELMEM func + ld a,0 ; bank 0 is system bank + call jphl +; + ; copy drvmap working copy to CP/M 3 drvtbl + ld hl,(drvtbl) ; get drvtbl address + ld a,(hl) ; deref HL to get DPH0 adr + inc hl ; ... + ld h,(hl) ; ... + ld l,a ; ... + ld (dphadr),hl ; save starting dphadr + + + ld hl,(drvtbl) ; get drive table in HL + ld de,mapwrk ; DE := working drive map + ld b,16 +instc1: + ld a,(de) ; get unit field of mapwrk + inc a ; test for $FF + jr nz,instc2 ; if used, do copy + xor a ; zero accum + ld (hl),a ; zero lsb of drvtbl entry adr + inc hl ; move to msb + ld (hl),a ; zero msb of drvtbl entry adr + inc hl ; bump to start of next drvtbl entry + inc de ; bump to next mapwrk entry + inc de ; ... + inc de ; ... + inc de ; ... + jr instc3 ; resume loop without copy +; +instc2: + push hl ; save drvtbl entry adr + push de ; save mapwrk entry adr + ld de,(dphadr) ; get cur dph adr + ld (hl),e ; save dph adr to drvtbl + inc hl ; ... + ld (hl),d ; ... + ex de,hl ; dph adr to HL + pop de ; restore mapwrk entry adr + dec hl ; backup to unit + dec hl ; ... + ld a,(de) ; get unit from mapwrk + ld (hl),a ; put unit into DPH field + inc de ; bump to slice field of mapwrk + inc hl ; bump to slice field of DPH field + ld a,(de) ; get slice from mapwrk + ld (hl),a ; put slice into DPH field + inc de ; bump to next mapwrk entry + inc de ; ... + inc de ; ... + pop hl ; back to drvtbl entry + inc hl ; bump to + inc hl ; ... next drvtbl entry +instc3: + push hl ; save drvtbl entry adr + push de ; save mapwrk entry adr + ld hl,(dphadr) ; get cur dph address + ld de,$23 ; size of xdph + add hl,de ; bump to next dph + ld (dphadr),hl ; save it + pop de ; recover mapwrk entry adr + pop hl ; recover drvtbl entry adr + djnz instc1 +; + ; switch back to tpabnk + ld hl,(bioloc) + ld de,27*3 ; offset of SELMEM func + add hl,de ; HL := SELMEM func + ld a,1 ; bank 1 is tpa bank + call jphl +; + call drvrst ; perform BDOS drive reset +; + xor a ; signal success + ret +; ; Handle overflow error in installation ; instovf: @@ -1623,6 +1794,9 @@ bioend .dw 0 ; CBIOS ending address biosiz .dw 0 ; CBIOS size (in bytes) maploc .dw 0 ; location of CBIOS drive map table dpbloc .dw 0 ; location of CBIOS DPB map table +cpmver .dw 0 ; CP/M version +drvtbl .dw 0 ; CP/M 3 drive table address +dphadr .dw 0 ; CP/M 3 working value for DPH ; drives: dstdrv .db 0 ; destination drive @@ -1688,7 +1862,7 @@ stack .equ $ ; stack top ; Messages ; indent .db " ",0 -msgban1 .db "ASSIGN v1.0d for RomWBW CP/M 2.2, 08-Aug-2019",0 +msgban1 .db "ASSIGN v1.1 for RomWBW CP/M, 17-Nov-2019",0 msghb .db " (HBIOS Mode)",0 msgub .db " (UBIOS Mode)",0 msgban2 .db "Copyright 2019, Wayne Warthen, GNU GPL v3",0 @@ -1715,5 +1889,7 @@ msgint .db "Multiple drive letters reference one filesystem, aborting!",0 msgnoa .db "Drive A: is unassigned, aborting!",0 msgdos .db "DOS error, return code=0x",0 msgmem .db " Disk Buffer Bytes Free",0 +; +modsize .equ $ - start ; .end diff --git a/Source/CBIOS/cbios.asm b/Source/CBIOS/cbios.asm index afcd5bab..a1b5320e 100644 --- a/Source/CBIOS/cbios.asm +++ b/Source/CBIOS/cbios.asm @@ -237,7 +237,7 @@ DEVMAP: ; Disk mapping is done using a drive map table (DRVMAP) which is built ; dynamically at cold boot. See the DRV_INIT routine. This table is ; made up of entries as documented below. The table is prefixed with one -; byte indicating the number of entries. The postion of the entry indicates +; byte indicating the number of entries. The position of the entry indicates ; the drive letter, so the first entry is A:, the second entry is B:, etc. ; ; UNIT: BIOS DISK UNIT # (BYTE) @@ -272,8 +272,8 @@ DEVMAP: ; DPB MAPPING TABLE ;================================================================================================== ; -; MAP MEDIA ID'S TO APPROPRIATE DPB ADDRESSEES -; THE ENTRIES IN THIS TABLE MUST CONCIDE WITH THE VALUES +; MAP MEDIA ID'S TO APPROPRIATE DPB ADDRESSES +; THE ENTRIES IN THIS TABLE MUST COINCIDE WITH THE VALUES ; OF THE MEDIA ID'S (SAME SEQUENCE, NO GAPS) ; .DB DPBCNT diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index b990716a..b17a35ca 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -775,6 +775,12 @@ HB_START: OUT0 (Z180_TCR),A ; SET DEFAULT CPU CLOCK MULTIPLIERS (XTAL / 2) + ; + ; IT HAS BEEN REPORTED THAT CMR NEEDS TO BE SET PRIOR TO CCR + ; SEEMS COUNTER-INTUITIVE AND I NEVER EXPERIENCED A PROBLEM + ; RELATED TO ORDER, BUT JUST FOR GOOD MEASURE, CMR + ; IS SET PRIOR TO CCR BELOW. + ; https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=316&#msg_5045 XOR A OUT0 (Z180_CMR),A OUT0 (Z180_CCR),A @@ -1008,8 +1014,11 @@ HB_CPU1: CP 3 ; Z8S180 REV N OR BETTER? JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE! ; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED + ; ALSO SET CCR AGAIN BECAUSE OF REPORTS THAT CCR + ; *MUST* BE SET AFTER CMR. LD A,$80 - OUT0 (Z180_CMR),A + OUT0 (Z180_CMR),A ; CPU MULTIPLIER + OUT0 (Z180_CCR),A ; CLOCK DIVIDE ; REFLECT SPEED CHANGE LD C,(CPUOSC * 2) / 1000000 LD DE,(CPUOSC * 2) / 1000 From bd8d059f32997e79044b7bcfe846e661b66ee766 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 17 Nov 2019 21:31:07 -0800 Subject: [PATCH 2/9] Cleanup --- Source/Apps/Assign.asm | 7 +++++-- Source/CBIOS/cbios.asm | 2 +- Source/CPM3/boot.z80 | 43 ++++++++++++++++++++++++++++++++---------- Source/CPM3/ver.inc | 7 +++++++ 4 files changed, 46 insertions(+), 13 deletions(-) create mode 100644 Source/CPM3/ver.inc diff --git a/Source/Apps/Assign.asm b/Source/Apps/Assign.asm index e76adab7..28a950ba 100644 --- a/Source/Apps/Assign.asm +++ b/Source/Apps/Assign.asm @@ -27,7 +27,6 @@ ; ToDo: ; 1) Do something to prevent assigning slices when device does not support them ; 2) ASSIGN C: causes drive map to be reinstalled unnecessarily -; 3) Need to find a way to verify RomWBW under CP/M 3 ;_______________________________________________________________________________ ; ;=============================================================================== @@ -106,7 +105,6 @@ init: ld (cpmver),hl ; save it ld a,l ; low byte cp $30 ; CP/M 3.0? - jp nc,initcpm3 ; handle CP/M 3.0 or greater ; ; get location of config data and verify integrity ld hl,stamp ; HL := adr or RomWBW zero page stamp @@ -146,6 +144,11 @@ init: inc hl ; ... into DE to get ld d,(hl) ; ... DPB map pointer ld (dpbloc),de ; and save it +; + ; test for CP/M 3 and branch if so + ld a,(cpmver) ; low byte of cpm version + cp $30 ; CP/M 3.0? + jp nc,initcpm3 ; handle CP/M 3.0 or greater ; ; make a local working copy of the drive map ld hl,(maploc) ; copy from CBIOS drive map diff --git a/Source/CBIOS/cbios.asm b/Source/CBIOS/cbios.asm index a1b5320e..971d3690 100644 --- a/Source/CBIOS/cbios.asm +++ b/Source/CBIOS/cbios.asm @@ -131,7 +131,7 @@ STPSIZ .EQU $ - STPIMG ; ; The following section contains key information and addresses for the ; RomWBW CBIOS. A pointer to the start of this section is stored with -; with the ZPX data in page zero at $44 (see above). +; with the CBX data in page zero at $44 (see above). ; CBX: DEVMAPADR .DW DEVMAP ; DEVICE MAP ADDRESS diff --git a/Source/CPM3/boot.z80 b/Source/CPM3/boot.z80 index 0e8b1013..a870edea 100644 --- a/Source/CPM3/boot.z80 +++ b/Source/CPM3/boot.z80 @@ -12,6 +12,8 @@ extrn dph0 extrn @dtbl,@ctbl + include ver.inc + bdos equ 5 if banked @@ -25,14 +27,11 @@ tpa$bank equ 0 ?init: call ?mvinit - ; Clear reserved area in page zero - xor a - ld hl,40h - ld b,10h -init$1: - ld (hl),a - inc hl - djnz init$1 + ; Install RomWBW CBIOS stamp in page zero + ld hl,stpimg + ld de,stploc + ld bc,stpsiz + ldir if banked @@ -382,12 +381,13 @@ read: ld c,20 jp bdos - signon$msg db 13,10,'CP/M v3.0' if banked db ' [BANKED]' endif - db ' for RomWBW HBIOS v2.9.2',13,10,13,10,0 + db ' on HBIOS v' + biosver + db 13,10,13,10,0 ccp$msg db 13,10,'BIOS Err on ' ccp$msg$drv db '?' @@ -401,4 +401,27 @@ fcb$nr db 0,0,0 @bootdu db 0 hdspv db 2 ; slices per volume for hard disks (must be >= 1) +; RomWBW CBIOS page zero stamp starts at $40 +; $40-$41: Marker ('W', ~'W') +; $42-$43: Version bytes: major/minor, update/patch +; $44-$45: CBIOS Extension Info address +; +stploc equ 40h +stpimg db 'W',~'W' ; marker + db rmj << 4 | rmn ; first byte of version info + db rup << 4 | rtp ; second byte of version info + dw cbx ; address of cbios ext data +stpsiz equ $ - stpimg + +; +; The following section contains key information and addresses for the +; RomWBW CBIOS. A pointer to the start of this section is stored with +; with the CBX data in page zero at $44 (see above). +; +cbx: +devmapadr dw 0 ; device map address +drvtbladr dw @dtbl ; drive map address (filled in later) +dphtbladr dw dph0 ; dpb map address +cbxsiz equ $ - cbx +; end diff --git a/Source/CPM3/ver.inc b/Source/CPM3/ver.inc new file mode 100644 index 00000000..379d1cd7 --- /dev/null +++ b/Source/CPM3/ver.inc @@ -0,0 +1,7 @@ +rmj equ 2 +rmn equ 9 +rup equ 2 +rtp equ 0 +biosver macro + db "2.9.2-pre.21" + endm From 1d542d88bc2106c034186c2414575ae39ce20e2b Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Thu, 21 Nov 2019 16:27:00 -0800 Subject: [PATCH 3/9] TUNE App Refinements --- Doc/ChangeLog.txt | 1 + Source/Apps/Tune/Tune.asm | 284 ++++++++++++++++++++++--------- Source/Images/hd0/s0/u3/Tune.com | Bin 3986 -> 4365 bytes 3 files changed, 207 insertions(+), 78 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index c1dd800e..683aab23 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -29,6 +29,7 @@ Version 2.9.2 - WBW: Add CP/M 3 (experimental) - M?T: Support Shift register SPI WIZNET for RC2014 - PLS: Added seconds register in HBIOS +- WBW: More flexible table-driven config in TUNE.COM Version 2.9.1 ------------- diff --git a/Source/Apps/Tune/Tune.asm b/Source/Apps/Tune/Tune.asm index a4cec9ea..9d5fe6a9 100644 --- a/Source/Apps/Tune/Tune.asm +++ b/Source/Apps/Tune/Tune.asm @@ -33,6 +33,7 @@ ; Change Log: ; 2018-01-26 [WBW] Initial release ; 2018-01-28 [WBW] Added support for MYM sound files +; 2019-11-21 [WBW] Added table-driven configuration ;_______________________________________________________________________________ ; ; ToDo: @@ -54,8 +55,6 @@ RMN .EQU 9 ; intended CBIOS version - minor BF_SYSVER .EQU $F1 ; BIOS: VER function BF_SYSGET .EQU $F8 ; HBIOS: SYSGET function ; -DCNTL .EQU $72 ; Z180 DCNTL PORT -; FCB .EQU $5C ; Location of default FCB ; HEAPEND .EQU $C000 ; End of heap storage @@ -79,48 +78,60 @@ TYPMYM .EQU 3 ; FILTYP value for MYM sound file LD A,RMJ << 4 | RMN ; Expected HBIOS ver CP D ; Compare with result above JP NZ,ERRBIO ; Handle BIOS error -; - ; Use platform id to derive port addresses +; + ; Use platform id to setup active configuration LD A,L ; Platform ID is still in L from above - LD C,L ; Save platform id in C for now - LD HL,$D0D8 ; For RC2014 Z80, RSEL=D8, RDAT=D0 - LD DE,MSGRCZ80 ; Message for RC2014 Z80 platform - CP 7 ; RC2014 Z80? - JR Z,_SETP ; If so, set ports - LD DE,MSGEZ ; Message for Easy Z80 platform - CP 9 ; Easy Z80? - LD HL,$6068 ; For RC2014 Z180, RSEL=D8, RDAT=D0 - LD DE,MSGRCZ180 ; Message for RC2014 Z180 platform - CP 8 ; RC2014 Z80? - JR Z,_SETP ; If so, set ports - LD DE,MSGSCZ180 ; Message for SC Z180 platform - CP 10 ; SCZ180? - JR Z,_SETP ; If so, same ports as RC2014 - LD HL,$9D9C ; For N8, RSEL=9C, RDAT=9D - LD DE,MSGN8 ; Message for N8 platform - CP 4 ; N8? - JR Z,_SETP ; If so, set ports - LD HL,$9B9A ; Otherwise SCG, RSEL=9A, RDAT=9B - LD DE,MSGSCG ; Message for SCG platform - LD A,$FF ; Write $FF to the - OUT ($9C),A ; ... SCG ACR register to activate card -_SETP LD (PORTS),HL ; Save port values + RLCA ; Adjust for table entry size (4 bytes) + PUSH AF ; Save ID * 2 for later + RLCA + LD HL,CFGTBL ; Point to start of config table + CALL ADDHLA ; HL := desired config table entry + LD DE,CFG ; Dest is active config + LD BC,4 ; Copy 4 bytes + LDIR ; Copy to active config +; + LD HL,PLTSTR ; Point to platform string table + POP AF ; Recover platform id * 2 for table offset + CALL ADDHLA ; HL := Platform string index adr + LD E,(HL) ; DE := Platform string adr + INC HL + LD D,(HL) CALL CRLF ; Formatting CALL PRTSTR ; Display platform string -; - ; Choose quark wait mode based on platform - LD A,C ; Recover platform id - LD B,1 ; Assume timer mode - LD DE,MSGTIM ; Corresponding display string - CP 4 ; N8? - JR Z,_SETM ; If so, commit timer mode - CP 5 ; MK4? - JR Z,_SETM ; If so, commit timer mode - LD B,0 ; Otherwise, delay mode - LD DE,MSGDLY ; Corresponding display string -_SETM LD A,B ; Mode flag value to A +; + LD A,(CFG) ; RSEL port address to A + INC A ; Test for $FF + JP Z,ERRPLT ; Bail out if unsupported platform +; + ; Test for timer running to determine if it can be used for delay + LD B,BF_SYSGET ; HBIOS: GET function + LD C,$D0 ; TIMER subfunction + RST 08 ; DE:HL := current tick count + LD A,L ; DE:HL == 0? + OR H + OR E + OR D + LD A,0 ; Assume no timer + LD DE,MSGDLY ; Delay mode msg + JR Z,SETDLY ; If tick count is zero, no timer active + LD A,$FF ; Value for timer active + LD DE,MSGTIM ; Timer mode msg +SETDLY: LD (WMOD),A ; Save wait mode CALL PRTSTR ; Print it +; +; ; *DEBUG* +; LD A,',' +; CALL PRTCHR +; LD HL,CFG +; LD B,4 +;DBGLP: +; LD A,' ' +; CALL PRTCHR +; LD A,(HL) +; INC HL +; CALL PRTHEX +; DJNZ DBGLP ; ; Get CPU speed & type from RomWBW HBIOS and compute quark delay factor LD B,$F8 ; HBIOS SYSGET function 0xF8 @@ -130,9 +141,19 @@ _SETM LD A,B ; Mode flag value to A RR E ; ... for delay factor EX DE,HL ; Move result to HL LD (QDLY),HL ; Save result as quark delay factor +; + ; Activate SCG card if applicable + LD A,(CFG+3) + CP $FF + JR Z,NOSCG + LD C,A + LD A,$FF + OUT (C),A +NOSCG: ; ; Test for hardware (sound chip detection) - LD DE,(PORTS) ; D := RDAT, E := RSEL + CALL SLOWIO + LD DE,(CFG) ; D := RDAT, E := RSEL LD C,E ; Port = RSEL LD A,2 ; Register 2 OUT (C),A ; Select register 2 @@ -141,6 +162,9 @@ _SETM LD A,B ; Mode flag value to A OUT (C),A ; Write $AA to register 2 LD C,E ; Port = RSEL IN A,(C) ; Read back value in register 2 + PUSH AF + CALL NORMIO + POP AF ;CALL PRTHEX ; *debug* CP $AA ; Value as written? JP NZ,ERRHW ; If not, handle hardware error @@ -228,7 +252,7 @@ _LDX LD C,16 ; CPM Close File function LD DE,MSGPLY ; Playing message CALL PRTSTR ; Print message ;CALL CRLF2 ; Formatting - + ;CALL SLOWCPU LD A,(FILTYP) ; Get file type CP TYPPT2 ; PT2? JR Z,GOPT2 ; If so, do it @@ -292,6 +316,7 @@ waitvb call WAITQ jr mymlp ; EXIT CALL START+8 ; Mute audio + ;CALL NORMCPU ;CALL CRLF2 ; Formatting LD DE,MSGEND ; Completion message CALL PRTSTR ; Print message @@ -389,6 +414,70 @@ IDBIO2: XOR A ; Setup return value of 0 RET ; and done ; +; +; +SLOWCPU: + LD A,(CFG+2) ; Z180 base I/O port + CP $FF ; Check for no value + RET Z ; Bail out if no value + ADD A,$1E ; Apply offset of CMR register + LD C,A ; And put it in C + LD B,0 ; MSB for 16-bit I/O + IN A,(C) ; Get current value + LD (CMRSAV),A ; Save it to restore later + XOR A ; Go slow + OUT (C),A ; And update CMR + INC C ; Now point to CCR register + IN A,(C) ; Get current value + LD (CCRSAV),A ; Save it to restore later + XOR A ; Go slow + OUT (C),A ; And update CCR + RET +; +; +; +NORMCPU: + LD A,(CFG+2) ; Z180 base I/O port + CP $FF ; Check for no value + RET Z ; Bail out if no value + ADD A,$1E ; Apply offset of CMR register + LD C,A ; And put it in C + LD B,0 ; MSB for 16-bit I/O + LD A,(CMRSAV) ; Get original CMR value + OUT (C),A ; And update CMR + INC C ; Now point to CCR register + LD A,(CCRSAV) ; Get original CCR value + OUT (C),A ; And update CCR + RET +; +; +; +SLOWIO: + LD A,(CFG+2) ; Z180 base I/O port + CP $FF ; Check for no value + RET Z ; Bail out if no value + ADD A,$32 ; Apply offset of DCNTL register + LD C,A ; And put it in C + LD B,0 ; MSB for 16-bit I/O + IN A,(C) ; Get current value + LD (DCSAV),A ; Save it to restore later + OR %00110000 ; Force slow operation (I/O W/S=3) + OUT (C),A ; And update DCNTL + RET +; +; +; +NORMIO: + LD A,(CFG+2) ; Z180 base I/O port + CP $FF ; Check for no value + RET Z ; Bail out if no value + ADD A,$32 ; Apply offset of DCNTL register + LD C,A ; And put it in C + LD B,0 ; MSB for 16-bit I/O + LD A,(DCSAV) ; Get saved DCNTL value + OUT (C),A ; And restore it + RET +; ; Print character in A without destroying any registers ; PRTCHR: @@ -562,10 +651,25 @@ CRLF: POP AF ; restore AF RET ; +; ADD HL,A +; +; A REGISTER IS DESTROYED! +; +ADDHLA: + ADD A,L + LD L,A + RET NC + INC H + RET +; ERRBIO: ; Invalid BIOS or version LD DE,MSGBIO JR ERR ; +ERRPLT: ; Invalid BIOS or version + LD DE,MSGPLT + JR ERR +; ERRHW: ; Hardware error, sound chip not detected LD DE,MSGHW JR ERR @@ -595,41 +699,81 @@ ERR1: ; without the leading crlf ERR2: ; without the string CALL CRLF ; print newline JP 0 ; fast exit - +; +; CONFIG TABLE, ENTRY ORDER MATCHES HBIOS PLATFORM ID +; +CFGTBL: ; RSEL RDAT Z180 ACR + .DB $FF, $FF, $FF, $FF ; PLATFORM ID 0 IS INVALID + .DB $9A, $9B, $FF, $9C ; SBC W/ SCG + .DB $FF, $FF, $FF, $FF ; ZETA (NOT POSSIBLE) + .DB $FF, $FF, $FF, $FF ; ZETA 2 (NOT POSSIBLE) + .DB $9C, $9D, $40, $FF ; N8 W/ ONBOARD PSG + .DB $9A, $9B, $40, $9C ; MK4 W/ SCG + .DB $9A, $9B, $FF, $FF ; UNA (NOT SUPPORTED) + .DB $D8, $D0, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (EB) + .DB $68, $60, $C0, $FF ; RCZ180 W/ RC SOUND MODULE (EB) + .DB $D8, $D0, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (EB) + .DB $68, $60, $C0, $FF ; SCZ180 W/ RC SOUND MODULE (EB) +; +CFG: ; ACTIVE CONFIG VALUES (FROM SELECTED CFGTBL) +RSEL .DB 0 ; Register selection port +RDAT .DB 0 ; Register data port +Z180 .DB 0 ; Z180 base I/O port +ACR .DB 0 ; Aux Ctrl Reg I/O port on SCG +; QDLY .DW 0 ; quark delay factor WMOD .DB 0 ; delay mode, non-zero to use timer -DCSAV .DB 0 ; for saving Z180 DCNTL value +DCSAV .DB 0 ; for saving original Z180 DCNTL value +CCRSAV .DB 0 ; for saving original Z180 CCR value +CMRSAV .DB 0 ; for saving original Z180 CMR value +; DMA .DW 0 ; Working DMA FILTYP .DB 0 ; Sound file type (TYPPT2, TYPPT3, TYPMYM) - +; TMP .DB 0 ; work around use of undocumented Z80 - -PORTS: -RSEL .DB 0 ; Register selection port -RDAT .DB 0 ; Register data port +; -MSGBAN .DB "Tune Player for RomWBW v2.1, 11-Aug-2019",0 +MSGBAN .DB "Tune Player for RomWBW v2.2, 21-Nov-2019",0 MSGUSE .DB "Copyright (C) 2019, Wayne Warthen, GNU GPL v3",13,10 .DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10 .DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10 .DB "Usage: TUNE .[PT2|PT3|MYM]",0 MSGBIO .DB "Incompatible BIOS or version, " .DB "HBIOS v", '0' + RMJ, ".", '0' + RMN, " required",0 +MSGPLT .DB "Hardware error, system not supported!",0 MSGHW .DB "Hardware error, sound chip not detected!",0 MSGNAM .DB "Sound filename invalid (must be .PT2, .PT3, or .MYM)",0 MSGFIL .DB "Sound file not found!",0 MSGSIZ .DB "Sound file too large to load!",0 -MSGRCZ80 .DB "RC2014 Z80 w/ Ed Brindley Sound Module",0 -MSGRCZ180 .DB "RC2014 Z180 w/ Ed Brindley Sound Module",0 -MSGSCZ180 .DB "SC Z180 w/ Ed Brindley Sound Module",0 -MSGEZ .DB "Easy Z80 w/ Ed Brindley Sound Module",0 -MSGN8 .DB "RetroBrew N8 Onboard Sound System",0 -MSGSCG .DB "RetroBrew SCG ECB Adapter Sound System",0 MSGTIM .DB ", timer mode",0 MSGDLY .DB ", delay mode",0 MSGPLY .DB "Playing...",0 MSGEND .DB " Done",0 ; +PLTSTR: + .DW 0 + .DW PLTSTR_SBC + .DW PLTSTR_ZETA + .DW PLTSTR_ZETA2 + .DW PLTSTR_N8 + .DW PLTSTR_MK4 + .DW PLTSTR_UNA + .DW PLTSTR_RCZ80 + .DW PLTSTR_RCZ180 + .DW PLTSTR_EZZ80 + .DW PLTSTR_SCZ180 +; +PLTSTR_SBC .DB "SBC w/ SCG ECB Sound Card",0 +PLTSTR_ZETA .DB "Zeta -- Not Supported!!!",0 +PLTSTR_ZETA2 .DB "Zeta 2 -- Not Supported!!!",0 +PLTSTR_N8 .DB "N8 Onboard Sound System",0 +PLTSTR_MK4 .DB "Mark IV w/ SCG ECB Sound Card",0 +PLTSTR_UNA .DB "UNA -- Not Supported!!!",0 +PLTSTR_RCZ80 .DB "RC2014 Z80 w/ Sound Module (EB)",0 +PLTSTR_RCZ180 .DB "RC2014 Z180 w/ Sound Module (EB)",0 +PLTSTR_EZZ80 .DB "Easy Z80 w/ Sound Module (EB)",0 +PLTSTR_SCZ180 .DB "SC Z180 w/ Sound Module (EB)",0 +; ;=============================================================================== ; PTx Player Routines ;=============================================================================== @@ -2012,15 +2156,9 @@ LOUT OUT (C),A #ENDIF #IF WBW - LD A,(WMOD) ; If WMOD = 1, CPU is Z180 - OR A ; Set flags - JR Z,LOUT0 ; Skip Z180 stuff DI - IN0 A,(DCNTL) ; Get wait states - LD (DCSAV),A ; Save value - OR %00110000 ; Force slow operation (I/O W/S=3) - OUT0 (DCNTL),A ; And update DCNTL -LOUT0 LD DE,(PORTS) ; D := RDAT, E := RSEL + CALL SLOWIO + LD DE,(CFG) ; D := RDAT, E := RSEL XOR A ; start with reg 0 LD C,E ; point to address port LD HL,AYREGS ; start of value list @@ -2037,11 +2175,8 @@ LOUT OUT (C),A ; select register JP M,LOUT2 ; if bit 7 set, return w/o writing value LD C,D ; select data port OUT (C),A ; write value to register 13 -LOUT2 LD A,(WMOD) ; If WMOD = 1, CPU is Z180 - OR A ; Set flags - RET Z ; Skip Z180 stuff - LD A,(DCSAV) ; Get saved DCNTL value - OUT0 (DCNTL),A ; And restore it +LOUT2 + CALL NORMIO EI RET ; And done #ENDIF @@ -2405,13 +2540,10 @@ upsg: ld a,(WMOD) ; if WMOD = 1, CPU is z180 or a ; set flags jr z,upsg1 ; skip z180 stuff di - in0 a,(DCNTL) ; get wait states - ld (DCSAV),a ; save value - or %00110000 ; force slow operation (i/o w/s=3) - out0 (DCNTL),a ; and update DCNTL + call SLOWIO upsg1: ld hl,(psource) - ld de,(PORTS) ; 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CHARACTER INPPUT +CIOIN EQU 00h ; CHARACTER INPUT CIOOUT EQU 01h ; CHARACTER OUTPUT CIOIST EQU 02h ; CHARACTER INPUT STATUS BID_BOOT EQU 00h @@ -35,7 +35,7 @@ FTH_LOC EQU 0200h ; ; =============================================== ; CAMEL80.AZM: Code Primitives -; Source code is for the Z80MR macro assembler. +; Source code is for the ZSM assembler. ; Forth words are documented as follows: ;x NAME stack -- stack description ; where x=C for ANS Forth Core words, X for ANS @@ -126,12 +126,12 @@ nexthl MACRO ENDM ; RESET AND INTERRUPT VECTORS =================== -; ...are not used in the CP/M implementation +; ...are not used in the ROMWBW implementation ; Instead, we have the... ; RELOCATED ENTRY POINT - .PHASE 0200H + .PHASE FTH_LOC reset: ld hl,0FDFFh ; HBIOS address, rounded down ld l,0 ; = end of avail.mem (EM) diff --git a/Source/Forth/camel80h.azm b/Source/Forth/camel80h.azm index d7a7c481..85990346 100644 --- a/Source/Forth/camel80h.azm +++ b/Source/Forth/camel80h.azm @@ -23,7 +23,7 @@ ; ; =============================================== ; CAMEL80H.AZM: High Level Words -; Source code is for the Z80MR macro assembler. +; Source code is for the ZSM assembler. ; Forth words are documented as follows: ;* NAME stack -- stack description ; Word names in upper case are from the ANS @@ -1023,5 +1023,5 @@ DOTS2: DW EXIT DB 55,'Z80 CamelForth v1.02 25 Jan 1995, ROMWBW 19 Oct 2019' DB 0dh,0ah DW TYPE,ABORT ; ABORT never returns -; DON'T FORGET TO UPDATE THE BYTE COUNT IF YOU CHANCGE THE SIZE OF THE BOOT MSG +; DON'T FORGET TO UPDATE THE BYTE COUNT IF YOU CHANGE THE SIZE OF THE BOOT MSG diff --git a/Source/Images/ReadMe.txt b/Source/Images/ReadMe.txt index b984e4a4..2bce9386 100644 --- a/Source/Images/ReadMe.txt +++ b/Source/Images/ReadMe.txt @@ -200,7 +200,7 @@ then use the COPYSYS command to make the desired drive bootable. You would use a command like the following to make drive C bootable. - | B>COPYSYS C:=CPM.SYS + | B>SYSCOPY C:=CPM.SYS Notes ----- From c6e6ed89dc5eea627d1869665c13143d38652339 Mon Sep 17 00:00:00 2001 From: b1ackmai1er Date: Sat, 23 Nov 2019 22:55:30 +0800 Subject: [PATCH 5/9] minor --- Source/Images/ReadMe.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/Images/ReadMe.txt b/Source/Images/ReadMe.txt index 2bce9386..23d9f66c 100644 --- a/Source/Images/ReadMe.txt +++ b/Source/Images/ReadMe.txt @@ -196,7 +196,7 @@ choice best left to the user. The simplest way to make a resultant image bootable is to do it from your running CP/M system. Boot your system using the ROM selection, -then use the COPYSYS command to make the desired drive bootable. +then use the SYSCOPY command to make the desired drive bootable. You would use a command like the following to make drive C bootable. From 7917a0143abbed780f8c604aaae59fc8474d2cb0 Mon Sep 17 00:00:00 2001 From: b1ackmai1er Date: Sun, 24 Nov 2019 20:49:51 +0800 Subject: [PATCH 6/9] ecb-sbc-v2 ecb-zp ctc timer support --- Source/HBIOS/cfg_sbc.asm | 1 + Source/HBIOS/hbios.asm | 67 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 63 insertions(+), 5 deletions(-) diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index 7576fbe1..27de79c6 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -38,6 +38,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCBASE .EQU $80 ; CTC BASE FOR ECB-ZILOG-PERIPHERALS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index b17a35ca..e3e0e75b 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1071,16 +1071,62 @@ HB_CPU2: ; #IF (HTIMENABLE) ; SIMH TIMER ; - #IF (INTMODE == 1) + #IF (INTMODE == 1) LD HL,HB_TIMINT CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST #ENDIF + + #ENDIF + #IF (CTCENABLE) + #IF (INTMODE == 2) ; - #IF (INTMODE == 2) - ;LD HL,HB_TIMINT - ;LD (HBX_IVT),HL - #ENDIF + ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT + LD HL,HB_TIMINT ; TIMER INT HANDLER ADR + LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D ; + ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR + ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE + ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE + ; IVT CORRESPOND TO CTC CHANNELS A-D + LD A,0 + OUT (CTCA),A ; SETUP CTC BASE INT VECTOR +; + ; ASSUMING ECB-ZP WITH 4.9125MHz XTAL AND / 8 DIVIDER + ; JUMPER X5 15-16, 9-11, X5 PIN 3 (PHI_X) TO X4 PIN 7 (CTC_TG2) + ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS + ; CTC CLK = 614,400Hz + ; CTCD TIME CONSTANT = 48 + ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC + ; WHICH IS 614,400HZ / 256 / 48 = 50HZ + LD A,%01010111 ; CTCC CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 1=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCC),A ; SETUP CTCC + LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 + OUT (CTCC),A ; SETUP CTCC TIMER CONSTANT + LD A,%11010111 ; CTCD CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 1=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 1=ENABLE INTERRUPTS + OUT (CTCD),A ; SETUP CTCD + LD A,48 ; CTCD TIMER CONSTANT = 48 + OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT + + #ELSE + .ECHO "*** ERROR: CTC REQUIRES INTMODE 2!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR + #ENDIF #ENDIF ; #ENDIF @@ -1740,6 +1786,9 @@ HB_INITTBL: #IF (UFENABLE) .DW UF_INIT #ENDIF +#IF (CTCENABLE) + .DW CTC_INIT +#ENDIF ; HB_INITTBLLEN .EQU (($ - HB_INITTBL) / 2) ; @@ -3197,6 +3246,14 @@ SIZ_UF .EQU $ - ORG_UF .ECHO SIZ_UF .ECHO " bytes.\n" #ENDIF +#IF (CTCENABLE) +ORG_CTC .EQU $ + #INCLUDE "ctcstub.asm" +SIZ_CTC .EQU $ - ORG_CTC + .ECHO "CTC occupies " + .ECHO SIZ_CTC + .ECHO " bytes.\n" +#ENDIF ; #DEFINE USEDELAY #INCLUDE "util.asm" From e2f066492f90fd8a0a6e57bda0c9854cfbd4ba03 Mon Sep 17 00:00:00 2001 From: b1ackmai1er Date: Sun, 24 Nov 2019 20:51:39 +0800 Subject: [PATCH 7/9] Create ctcstub.asm --- Source/HBIOS/ctcstub.asm | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 Source/HBIOS/ctcstub.asm diff --git a/Source/HBIOS/ctcstub.asm b/Source/HBIOS/ctcstub.asm new file mode 100644 index 00000000..4551502e --- /dev/null +++ b/Source/HBIOS/ctcstub.asm @@ -0,0 +1,20 @@ +;___CTC________________________________________________________________________________________________________________ +; +; Z80 CTC STUB +; +; DISPLAY CONFIGURATION DETAILS +;______________________________________________________________________________________________________________________ +; +CTC_INIT: ; MINIMAL INIT +CTC_PRTCFG: + ; ANNOUNCE PORT + CALL NEWLINE ; FORMATTING + PRTS("CTC$") ; FORMATTING +; LD A,(IY) ; DEVICE NUM +; CALL PRTDECB ; PRINT DEVICE NUM + PRTS(": IO=0x$") ; FORMATTING + LD A,CTCBASE ; GET BASE PORT + CALL PRTHEXBYTE ; PRINT BASE PORT +; + XOR A + RET From 6d22708b66beb645d72dc7e21304bb3484eef01c Mon Sep 17 00:00:00 2001 From: b1ackmai1er Date: Sun, 24 Nov 2019 21:18:08 +0800 Subject: [PATCH 8/9] ecb-sbc-v2 / ecb-zp ctc timer configuration Correct instructions on jumpering. --- Source/HBIOS/hbios.asm | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index e3e0e75b..0bc178c4 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1086,13 +1086,15 @@ HB_CPU2: ; ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE + ; START OF THE IVT, SO THE FIRST FOUR ENTRIES OF THE ; IVT CORRESPOND TO CTC CHANNELS A-D LD A,0 OUT (CTCA),A ; SETUP CTC BASE INT VECTOR ; ; ASSUMING ECB-ZP WITH 4.9125MHz XTAL AND / 8 DIVIDER - ; JUMPER X5 15-16, 9-11, X5 PIN 3 (PHI_X) TO X4 PIN 7 (CTC_TG2) + ; JUMPER X5 15-16, 9-11 + ; JUMPER X5 PIN 3 (PHI_X) TO X4 PIN 7 (CTC_TG2) + ; JUMPER X4 PIN 8 (CTC_ZC2) TO X4 PIN 9 (CTC_TG3) ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS ; CTC CLK = 614,400Hz ; CTCD TIME CONSTANT = 48 From 2ebd80048268c8322ca5e6dcb88c7b1f61902e32 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 24 Nov 2019 20:16:54 -0800 Subject: [PATCH 9/9] CTC Refactoring --- Source/Apps/Tune/Tune.asm | 7 +- Source/HBIOS/Config/RCZ80_kio.asm | 1 + Source/HBIOS/cfg_ezz80.asm | 3 + Source/HBIOS/cfg_master.asm | 3 + Source/HBIOS/cfg_rcz180.asm | 2 + Source/HBIOS/cfg_rcz80.asm | 3 + Source/HBIOS/cfg_sbc.asm | 4 +- Source/HBIOS/cfg_scz180.asm | 2 + Source/HBIOS/cfg_zeta2.asm | 1 + Source/HBIOS/ctc.asm | 126 ++++++++++++++ Source/HBIOS/ctcstub.asm | 20 --- Source/HBIOS/hbios.asm | 272 ++---------------------------- Source/HBIOS/sio.asm | 38 +++++ Source/HBIOS/std.asm | 8 + 14 files changed, 205 insertions(+), 285 deletions(-) create mode 100644 Source/HBIOS/ctc.asm delete mode 100644 Source/HBIOS/ctcstub.asm diff --git a/Source/Apps/Tune/Tune.asm b/Source/Apps/Tune/Tune.asm index 9d5fe6a9..2aec55fc 100644 --- a/Source/Apps/Tune/Tune.asm +++ b/Source/Apps/Tune/Tune.asm @@ -23,11 +23,14 @@ ; - Max Z80 CPU clock is about 8MHz or sound chip will not handle speed. ; - Higher CPU clock speeds are possible on Z180 because extra I/O ; wait states are added during I/O to sound chip. -; - Uses hardware timer support on Z180 processors. Otherwise, a delay -; loop calibrated to CPU speed is used. +; - Uses hardware timer support on systems that support a timer. Otherwise, +; a delay loop calibrated to CPU speed is used. ; - Delay loop is calibrated to CPU speed, but it does not compensate for ; time variations in each quark loop resulting from data decompression. ; An average quark processing time is assumed in each loop. +; - Most sound files originally targeted MSX or ZX Spectrum which used +; 1.7897725 MHz and 1.773400 MHz respectively for the PSG clock. For best +; sound playback, PSG should be run at approx. this clock rate. ;_______________________________________________________________________________ ; ; Change Log: diff --git a/Source/HBIOS/Config/RCZ80_kio.asm b/Source/HBIOS/Config/RCZ80_kio.asm index 45d7637b..d8229e6b 100644 --- a/Source/HBIOS/Config/RCZ80_kio.asm +++ b/Source/HBIOS/Config/RCZ80_kio.asm @@ -39,6 +39,7 @@ SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .SET SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR +SIO0CTCC .SET 0 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 ;SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 08a2a9ac..4d92013b 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -41,6 +41,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_EZ ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT @@ -74,6 +75,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -82,6 +84,7 @@ SIO0BCLK .EQU 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index e8677023..a34ac222 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -59,6 +59,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT @@ -113,6 +114,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -121,6 +123,7 @@ SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index ca3bfb1f..62c5bf8b 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -80,6 +80,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -88,6 +89,7 @@ SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 818e0274..9c3ab068 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -40,6 +40,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_RC ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT @@ -83,6 +84,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -91,6 +93,7 @@ SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index 27de79c6..43da5d26 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -38,7 +38,8 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCBASE .EQU $80 ; CTC BASE FOR ECB-ZILOG-PERIPHERALS +CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] +CTCBASE .EQU $80 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS @@ -80,6 +81,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 4915200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 8 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 9f8e35ef..3ddae6ae 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -75,6 +75,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -83,6 +84,7 @@ SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index f83f0788..03571213 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -41,6 +41,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_Z2 ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT diff --git a/Source/HBIOS/ctc.asm b/Source/HBIOS/ctc.asm new file mode 100644 index 00000000..7551bed9 --- /dev/null +++ b/Source/HBIOS/ctc.asm @@ -0,0 +1,126 @@ +;___CTC________________________________________________________________________________________________________________ +; +; Z80 CTC +; +; DISPLAY CONFIGURATION DETAILS +;______________________________________________________________________________________________________________________ +; +; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO +; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO +; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO +; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. +; +#IF (INTMODE != 2) + .ECHO "*** ERROR: CTC REQUIRES INTMODE 2!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR +#ENDIF +; +; CONFIGURATION +; +#IF (CTCMODE == CTCMODE_ZP) +CTCPC .EQU CTCC ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCD ; TIMER CHANNEL +CTCTCC .EQU 48 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +#IF (CTCMODE == CTCMODE_Z2) +CTCPC .EQU CTCA ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCB ; TIMER CHANNEL +CTCTCC .EQU 72 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0B ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +#IF (CTCMODE == CTCMODE_EZ) +CTCPC .EQU CTCC ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCD ; TIMER CHANNEL +CTCTCC .EQU 72 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +#IF (CTCMODE == CTCMODE_RC) +CTCPC .EQU CTCC ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCD ; TIMER CHANNEL +CTCTCC .EQU 144 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +; +; +CTC_PREINIT: + ; SETUP TIMER INTERRUPT IVT SLOT + LD HL,HB_TIMINT ; TIMER INT HANDLER ADR + LD (IVT(CTCTIVT)),HL ; IVT ENTRY FOR TIMER CHANNEL +; + ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR + ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE + ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE + ; IVT CORRESPOND TO CTC CHANNELS A-D + LD A,0 + OUT (CTCBASE),A ; SETUP CTC BASE INT VECTOR +; + ; IN ORDER TO DIVIDE THE CTC INPUT CLOCK DOWN TO THE + ; DESIRED 50 HZ PERIODIC INTERRUPT, WE NEED TO CONFIGURE ONE + ; CTC CHANNEL AS A PRESCALER AND ANOTHER AS THE ACTUAL + ; TIMER INTERRUPT. THE PRESCALE CHANNEL OUTPUT MUST BE WIRED + ; TO THE TIMER CHANNEL TRIGGER INPUT VIA HARDWARE. + LD A,%01010111 ; PRESCALE CHANNEL CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 1=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCPC),A ; SETUP PRESCALE CHANNEL + LD A,CTCPCC ; PRESCALE CHANNEL CONSTANT + OUT (CTCPC),A ; SET PRESCALE CONSTANT + ; + LD A,%11010111 ; TIMER CHANNEL CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 1=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 1=ENABLE INTERRUPTS + OUT (CTCTC),A ; SETUP TIMER CHANNEL + LD A,CTCTCC ; TIMER CHANNEL CONSTANT + OUT (CTCTC),A ; SET TIMER CONSTANT +; + XOR A + RET +; +; +; +CTC_INIT: ; MINIMAL INIT +CTC_PRTCFG: + ; ANNOUNCE PORT + CALL NEWLINE ; FORMATTING + PRTS("CTC: MODE=$") ; FORMATTING +#IF (CTCMODE == CTCMODE_ZP) + PRTS("ZP$") +#ENDIF +#IF (CTCMODE == CTCMODE_Z2) + PRTS("Z2$") +#ENDIF +#IF (CTCMODE == CTCMODE_EZ) + PRTS("EZ$") +#ENDIF +#IF (CTCMODE == CTCMODE_RC) + PRTS("RC$") +#ENDIF +; LD A,(IY) ; DEVICE NUM +; CALL PRTDECB ; PRINT DEVICE NUM + PRTS(" IO=0x$") ; FORMATTING + LD A,CTCBASE ; GET BASE PORT + CALL PRTHEXBYTE ; PRINT BASE PORT +; + XOR A + RET diff --git a/Source/HBIOS/ctcstub.asm b/Source/HBIOS/ctcstub.asm deleted file mode 100644 index 4551502e..00000000 --- a/Source/HBIOS/ctcstub.asm +++ /dev/null @@ -1,20 +0,0 @@ -;___CTC________________________________________________________________________________________________________________ -; -; Z80 CTC STUB -; -; DISPLAY CONFIGURATION DETAILS -;______________________________________________________________________________________________________________________ -; -CTC_INIT: ; MINIMAL INIT -CTC_PRTCFG: - ; ANNOUNCE PORT - CALL NEWLINE ; FORMATTING - PRTS("CTC$") ; FORMATTING -; LD A,(IY) ; DEVICE NUM -; CALL PRTDECB ; PRINT DEVICE NUM - PRTS(": IO=0x$") ; FORMATTING - LD A,CTCBASE ; GET BASE PORT - CALL PRTHEXBYTE ; PRINT BASE PORT -; - XOR A - RET diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 0bc178c4..78097c77 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1048,11 +1048,6 @@ HB_CPU2: ; #ENDIF ; -#IF (KIOENABLE) - LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN - OUT (KIOBASE+$0E),A ; DO IT -#ENDIF -; #IF (INTMODE == 2) ; SETUP Z80 IVT AND INT MODE 2 LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS @@ -1077,262 +1072,16 @@ HB_CPU2: #ENDIF #ENDIF - #IF (CTCENABLE) - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTRIES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; ASSUMING ECB-ZP WITH 4.9125MHz XTAL AND / 8 DIVIDER - ; JUMPER X5 15-16, 9-11 - ; JUMPER X5 PIN 3 (PHI_X) TO X4 PIN 7 (CTC_TG2) - ; JUMPER X4 PIN 8 (CTC_ZC2) TO X4 PIN 9 (CTC_TG3) - ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 614,400Hz - ; CTCD TIME CONSTANT = 48 - ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC - ; WHICH IS 614,400HZ / 256 / 48 = 50HZ - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCC),A ; SETUP CTCC - LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCC),A ; SETUP CTCC TIMER CONSTANT - LD A,%11010111 ; CTCD CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCD),A ; SETUP CTCD - LD A,48 ; CTCD TIMER CONSTANT = 48 - OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT - - #ELSE - .ECHO "*** ERROR: CTC REQUIRES INTMODE 2!!!\n" - !!! ; FORCE AN ASSEMBLY ERROR - #ENDIF - #ENDIF -; -#ENDIF -; -#IF (PLATFORM == PLT_ZETA2) -; -; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO -; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO -; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO -; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. -; - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0B)),HL ; IVT ENTRY FOR CTC0B -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; CTCA IS SLAVED (WIRED) TO TO CTCB TO ACT AS A PRESCALER - ; CONFIGURE CHANNEL B FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 921,200HZ - ; CTCA TIME CONSTANT = 256 - ; CTCB TIME CONSTANT = 72 - ; INT FREQ IS CTC CLK / CTCA TC / CTCB TC - ; WHICH IS 921,600HZ / 256 / 72 = 50HZ - LD A,%01010111 ; CTCA CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCA),A ; SETUP CTCA - LD A,0 ; CTCA TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCA),A ; SETUP CTCA TIMER CONSTANT - LD A,%11010111 ; CTCB CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCB),A ; SETUP CTCB - LD A,72 ; CTCB TIMER CONSTANT = 72 - OUT (CTCB),A ; SETUP CTCB TIMER CONSTANT - #ENDIF -; -#ENDIF -; -#IF (PLATFORM == PLT_EZZ80) -; -; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO -; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO -; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO -; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. -; - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER - ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 921,200HZ - ; CTCC TIME CONSTANT = 256 - ; CTCD TIME CONSTANT = 72 - ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC - ; WHICH IS 921,600HZ / 256 / 72 = 50HZ - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCC),A ; SETUP CTCC - LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCC),A ; SETUP CTCC TIMER CONSTANT - LD A,%11010111 ; CTCD CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCD),A ; SETUP CTCD - LD A,72 ; CTCD TIMER CONSTANT = 72 - OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT - #ELSE - .ECHO "*** ERROR: EZZ80 REQUIRES INTMODE 2!!!\n" - !!! ; FORCE AN ASSEMBLY ERROR - #ENDIF ; #ENDIF ; -#IF (PLATFORM == PLT_RCZ80) -; -; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO -; AT 1:1 USING CTC CHANNELS A & B. IN OTHER WORDS, IT JUST -; PASSES THE INCOMING TRIGGER OUT AT 1:1. -; - #IF (CTCENABLE == TRUE) -; - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 0=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCA),A ; SETUP CTCC - LD A,1 ; CTCC TIMER CONSTANT = 1 - OUT (CTCA),A ; SETUP CTCC TIMER CONSTANT -; - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 0=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCB),A ; SETUP CTCC - LD A,1 ; CTCC TIMER CONSTANT = 1 - OUT (CTCB),A ; SETUP CTCC TIMER CONSTANT -; -; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO -; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO -; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO -; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. -; - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER - ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 1,843,200HZ - ; CTCC TIME CONSTANT = 256 - ; CTCD TIME CONSTANT = 144 - ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC - ; WHICH IS 1,843,200HZ / 256 / 144 = 50HZ - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCC),A ; SETUP CTCC - LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCC),A ; SETUP CTCA TIMER CONSTANT - LD A,%11010111 ; CTCD CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCD),A ; SETUP CTCD - LD A,144 ; CTCD TIMER CONSTANT = 144 - OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT - #ENDIF -; - #ENDIF +#IF (KIOENABLE) + LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN + OUT (KIOBASE+$0E),A ; DO IT +#ENDIF ; +#IF (CTCENABLE) + CALL CTC_PREINIT #ENDIF ; #IF (CPUFAM == CPU_Z180) @@ -1712,7 +1461,9 @@ PC_INITTBLLEN .EQU (($ - PC_INITTBL) / 2) ;================================================================================================== ; HB_INITTBL: -;#IF (SPKENABLE & DSRTCENABLE) +#IF (CTCENABLE) + .DW CTC_INIT +#ENDIF #IF (SPKENABLE) .DW SPK_INIT ; AUDIBLE INDICATOR OF BOOT START #ENDIF @@ -1788,9 +1539,6 @@ HB_INITTBL: #IF (UFENABLE) .DW UF_INIT #ENDIF -#IF (CTCENABLE) - .DW CTC_INIT -#ENDIF ; HB_INITTBLLEN .EQU (($ - HB_INITTBL) / 2) ; @@ -3250,7 +2998,7 @@ SIZ_UF .EQU $ - ORG_UF #ENDIF #IF (CTCENABLE) ORG_CTC .EQU $ - #INCLUDE "ctcstub.asm" + #INCLUDE "ctc.asm" SIZ_CTC .EQU $ - ORG_CTC .ECHO "CTC occupies " .ECHO SIZ_CTC diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm index 1d3d8791..31000849 100644 --- a/Source/HBIOS/sio.asm +++ b/Source/HBIOS/sio.asm @@ -158,6 +158,44 @@ SIO_PREINIT2: ; #ENDIF ; +; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO +; AT 1:1 USING CTC CHANNELS A & B. IN OTHER WORDS, IT JUST +; PASSES THE INCOMING TRIGGER OUT AT 1:1. +; +#IF (SIOCNT >= 1) + #IF (SIO0CTCC >= 0) + LD A,%01010111 ; CTCC CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 0=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCA + SIO0CTCC),A ; SETUP CTCC + LD A,1 ; CTC TIMER CONSTANT = 1 + OUT (CTCA + SIO0CTCC),A ; SETUP CTC TIMER CONSTANT + #ENDIF +#ENDIF +; +#IF (SIOCNT >= 2) + #IF (SIO1CTCC >= 0) + LD A,%01010111 ; CTCC CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 0=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCA + SIO1CTCC),A ; SETUP CTCC + LD A,1 ; CTC TIMER CONSTANT = 1 + OUT (CTCA + SIO1CTCC),A ; SETUP CTC TIMER CONSTANT + #ENDIF +#ENDIF +; SIO_PREINIT3: XOR A ; SIGNAL SUCCESS RET ; AND RETURN diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 625c0f98..2f8776e4 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -93,6 +93,14 @@ MID_FD360 .EQU 7 MID_FD120 .EQU 8 MID_FD111 .EQU 9 ; +; ZILOG CTC MODE SELECTIONS +; +CTCMODE_NONE .EQU 0 ; NO CTC +CTCMODE_ZP .EQU 1 ; ZILOG PERIPHERALS ECB CTC +CTCMODE_Z2 .EQU 2 ; ZETA2 ONBOARD CTC +CTCMODE_EZ .EQU 3 ; EASY Z80 ONBOARD CTC +CTCMODE_RC .EQU 4 ; RC2014 CTC MODULE (ALSO KIO) +; ; DS RTC MODE SELECTIONS ; DSRTCMODE_NONE .EQU 0 ; NO DSRTC