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Reintegrate wbw -> trunk

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This commit is contained in:
wayne
2013-06-08 04:58:34 +00:00
parent f5c27ce732
commit 82351f2c5f
52 changed files with 657 additions and 496 deletions
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2
Source/bootapp.asm
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@@ -79,7 +79,7 @@
;
JP PHASE2 ; JUMP TO PHASE 2 BOOT IN UPPER MEMORY
;
STR_BOOT .DB "Boot$"
STR_BOOT .DB "RomWBW$"
;
; IMBED DIRECT SERIAL I/O ROUTINES
;

2
Source/bootrom.asm
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@@ -62,7 +62,7 @@
;
JP PHASE2 ; JUMP TO PHASE 2 BOOT IN UPPER MEMORY
;
STR_BOOT .DB "Boot$"
STR_BOOT .DB "RomWBW$"
;
; IMBED DIRECT SERIAL I/O ROUTINES
;

18
Source/cbios.asm
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@@ -512,9 +512,21 @@ READWRITE:
#ENDIF
LD A,(SEKDU) ; GET DEVICE/UNIT
AND 0F0H ; ISOLATE DEVICE NIBBLE
JR Z,DIRRW ; DEVICE = 0 = MD, SO DIRECT R/W
JP BLKRW ; OTHERWISE, (DE)BLOCKING R/W
; JR Z,DIRRW ; DEVICE = 0 = MD, SO DIRECT R/W
; JP BLKRW ; OTHERWISE, (DE)BLOCKING R/W
JR NZ,BLKRW ; DEVICE != 0, (DE)BLOCKING R/W
;
LD (STKSAV),SP ; SAVE STACK
LD SP,TMPSTK ; TEMP STACK
CALL DIRRW ; DEVICE = 0 = MD, SO DIRECT R/W
LD SP,(STKSAV) ; RESTORE STACK
RET ; DONE
;
; NEED TO FORCE STACK INTO UPPER MEMORY DUE TO PAGING OF LOWER MEMORY
;
STKSAV .DW 0
.FILL 16
TMPSTK .EQU $
;
;==================================================================================================
; DIRECT READ/WRITE (NO (DE)BLOCKING, NO BUFFERING, 128 BYTE SECTOR)

2
Source/config_n8_2312.asm
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@@ -52,7 +52,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8_2511.asm
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@@ -52,7 +52,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

4
Source/config_n8vem_ci.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR N8VEM SBC
; ROMWBW 2.X CONFIGURATION FOR N8VEM SBC W/ CASSETTE INTERFACE
;==================================================================================================
;
; BUILD CONFIGURATION OPTIONS
@@ -60,7 +60,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_cvdu.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_dide.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_diskio.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_diskio3.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $20 ; PPIDE IOBASE IS $20 FOR DISKIO V3
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_dsd.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

102
Source/config_n8vem_mfp.asm Normal file
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@@ -0,0 +1,102 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR N8VEM SBC W/ MULTIFUNCTION PIC
;==================================================================================================
;
; BUILD CONFIGURATION OPTIONS
;
CPUFREQ .EQU 8 ; IN MHZ, USED TO COMPUTE DELAY FACTORS
;
DEFCON .EQU CIODEV_UART ; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, DIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
ALTCON .EQU DEFCON ; ALT CONSOLE DEVICE (USED WHEN CONFIG JUMPER SHORTED)
CONBAUD .EQU 38400 ; BAUDRATE FOR CONSOLE DURING HARDWARE INIT
DEFVDA .EQU VDADEV_NONE ; DEFAULT VDA DEVICE (VDADEV_NONE, VDADEV_VDU, VDADEV_CVDU, VDADEV_N8V, VDADEV_UPD7220)
DEFEMU .EQU EMUTYP_TTY ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
TERMTYPE .EQU TERM_ANSI ; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
CLRRAMDISK .EQU CLR_AUTO ; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
;
DSKMAP .EQU DM_RAM ; DM_ROM, DM_RAM, DM_FD, DM_IDE, DM_PPIDE, DM_SD, DM_PRPSD, DM_PPPSD
;
DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
;
UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
UARTCNT .EQU 2 ; NUMBER OF UARTS
UART0IOB .EQU $68 ; UART0 IOBASE
UART0BAUD .EQU CONBAUD ; UART0 BAUDRATE
UART0FIFO .EQU TRUE ; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
UART0AFC .EQU FALSE ; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
UART1IOB .EQU $88 ; UART1 IOBASE AT $88 FOR MFPIC
UART1BAUD .EQU 38400 ; UART1 BAUDRATE IS 38400 FOR MFPIC
UART1FIFO .EQU TRUE ; UART1 FIFO ENABLED FOR MFPIC
UART1AFC .EQU FALSE ; UART1 AUTO FLOW CONTROL DISABLED FOR MFPIC (ENABLE IF DESIRED)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT
ASCI0BAUD .EQU 38400 ; ASCI0 BAUDRATE (IMPLEMENTED BY Z180_CNTLB0)
ASCI1BAUD .EQU 38400 ; ASCI1 BAUDRATE (IMPLEMENTED BY Z180_CNTLB1)
;
VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
UPD7220ENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
N8VENABLE .EQU FALSE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
;
DEFIOBYTE .EQU $00 ; DEFAULT INITIAL VALUE FOR CP/M IOBYTE, $00=TTY, $01=CRT (MUST HAVE CRT HARDWARE)
ALTIOBYTE .EQU DEFIOBYTE ; ALT INITIAL VALUE (USED WHEN CONFIG JUMPER SHORTED)
WRTCACHE .EQU TRUE ; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
DSKTRACE .EQU FALSE ; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
;
FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .EQU FDMODE_DIO ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
;
IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
IDEMODE .EQU IDEMODE_DIO ; IDEMODE_DIO, IDEMODE_DIDE
IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEIOB .EQU $84 ; PPIDE IOBASE IS $84 FOR MFPIC (PRELIMINARY ADDRESS)
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
PPIDESLOW .EQU FALSE ; ADD DELAYS TO HELP PROBLEMATIC HARDWARE (TRY THIS IF PPIDE IS UNRELIABLE)
;
SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
SDMODE .EQU SDMODE_JUHA ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
SDCSIOFAST .EQU FALSE ; TABLE-DRIVEN BIT INVERTER
;
PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
PRPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
PRPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
PRPSDCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
PRPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
PPPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
PPPSDCAPACITY .EQU 64 ; CAPACITY OF PPP SD DEVICE (IN MB)
PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
;
HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
HDSKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
HDSKCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPKENABLE .EQU FALSE ; TRUE FOR PARALLEL PORT KEYBOARD
PPKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
KBDENABLE .EQU FALSE ; TRUE FOR PS/2 KEYBOARD ON I8242
KBDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
;
TTYENABLE .EQU FALSE ; INCLUDE TTY EMULATION SUPPORT
ANSIENABLE .EQU FALSE ; INCLUDE ANSI EMULATION SUPPORT
ANSITRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
;
BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'R' ; SELECTION TO INVOKE AT TIMEOUT

2
Source/config_n8vem_ppide.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_ppisd.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_propio.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_simh.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_std.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_n8vem_vdu.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_zeta_ppp.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

2
Source/config_zeta_std.asm
View File

@@ -56,7 +56,7 @@ IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!
IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
;
PPIDEENABLE .EQU TRUE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
PPIDEIOB .EQU $60 ; PPIDE IOBASE
PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)

15
Source/ppide.asm
View File

@@ -18,17 +18,10 @@
;
; MAP PPI PORTS TO PPIDE PORTS
;
#IF (PPIDEMODE == PPIDEMODE_DIO3)
IDELSB .EQU 20H ; LSB
IDEMSB .EQU 21H ; MSB
IDECTL .EQU 22H ; CONTROL SIGNALS
PPI1CONT .EQU 23H ; CONTROL BYTE PPI 82C55
#ELSE
IDELSB .EQU PPIA ; LSB
IDEMSB .EQU PPIB ; MSB
IDECTL .EQU PPIC ; CONTROL SIGNALS
PPI1CONT .EQU PPIX ; CONTROL BYTE PPI 82C55
#ENDIF
IDELSB .EQU PPIDEIOB + 0 ; LSB
IDEMSB .EQU PPIDEIOB + 1 ; MSB
IDECTL .EQU PPIDEIOB + 2 ; CONTROL SIGNALS
PPI1CONT .EQU PPIDEIOB + 3 ; CONTROL BYTE PPI 82C55
;
; PPI control bytes for read and write to IDE drive
;

1
Source/std.asm
View File

@@ -98,6 +98,7 @@ IDEMODE_DIDE .EQU 2 ; DUAL IDE
PPIDEMODE_NONE .EQU 0
PPIDEMODE_STD .EQU 1 ; STANDARD N8VEM PARALLEL PORT
PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
;
; SD MODE SELECTIONS
;

2
Source/syscfg.asm
View File

@@ -134,7 +134,7 @@ BOOTTIME .DB 0,0,0,0,0,0 ; SYSTEM STARTUP TIME (YY,MM,DD,HH,MM,SS)
.DW IDECAPACITY
.DB PPIDEENABLE
.DB PPIDEMODE
.DB PPIDEIOB
.DB PPIDETRACE
.DB PPIDE8BIT
.DW PPIDECAPACITY

486
Source/uart.asm
View File

@@ -3,6 +3,35 @@
; UART DRIVER (SERIAL PORT)
;==================================================================================================
;
UART_DEBUG .EQU FALSE
;
UART_NONE .EQU 0 ; UNKNOWN OR NOT PRESENT
UART_8250 .EQU 1
UART_16450 .EQU 2
UART_16550 .EQU 3
UART_16550A .EQU 4
UART_16550C .EQU 5
UART_16650 .EQU 6
UART_16750 .EQU 7
UART_16850 .EQU 8
;
UART_RBR .EQU 0 ; DLAB=0: RCVR BUFFER REG (READ)
UART_THR .EQU 0 ; DLAB=0: XMIT HOLDING REG (WRITE)
UART_IER .EQU 1 ; DLAB=0: INT ENABLE REG (READ)
UART_IIR .EQU 2 ; INT IDENT REGISTER (READ)
UART_FCR .EQU 2 ; FIFO CONTROL REG (WRITE)
UART_LCR .EQU 3 ; LINE CONTROL REG (READ/WRITE)
UART_MCR .EQU 4 ; MODEM CONTROL REG (READ/WRITE)
UART_LSR .EQU 5 ; LINE STATUS REG (READ)
UART_MSR .EQU 6 ; MODEM STATUS REG (READ)
UART_SCR .EQU 7 ; SCRATCH REGISTER (READ/WRITE)
UART_DLL .EQU 0 ; DLAB=1: DIVISOR LATCH (LS) (READ/WRITE)
UART_DLM .EQU 1 ; DLAB=1: DIVISOR LATCH (MS) (READ/WRITE)
UART_EFR .EQU 2 ; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE)
;
#DEFINE UART_IN(RID) CALL UART_INP \ .DB RID
#DEFINE UART_OUT(RID) CALL UART_OUTP \ .DB RID
;
#IF (UARTCNT >= 1)
UART0_RBR .EQU UART0IOB + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
UART0_THR .EQU UART0IOB + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
@@ -16,8 +45,10 @@ UART0_MSR .EQU UART0IOB + 6 ; MODEM STATUS REG
UART0_SCR .EQU UART0IOB + 7 ; SCRATCH REGISTER
UART0_DLL .EQU UART0IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART0_DLM .EQU UART0IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART0_EFR .EQU UART0IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART0_DIV .EQU (1843200 / (16 * UART0BAUD))
;
#ENDIF
;
#IF (UARTCNT >= 2)
@@ -33,6 +64,7 @@ UART1_MSR .EQU UART1IOB + 6 ; MODEM STATUS REG
UART1_SCR .EQU UART1IOB + 7 ; SCRATCH REGISTER
UART1_DLL .EQU UART1IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART1_DLM .EQU UART1IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART1_EFR .EQU UART1IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART1_DIV .EQU (1843200 / (16 * UART1BAUD))
#ENDIF
@@ -50,6 +82,7 @@ UART2_MSR .EQU UART2IOB + 6 ; MODEM STATUS REG
UART2_SCR .EQU UART2IOB + 7 ; SCRATCH REGISTER
UART2_DLL .EQU UART2IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART2_DLM .EQU UART2IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART2_EFR .EQU UART2IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART2_DIV .EQU (1843200 / (16 * UART2BAUD))
#ENDIF
@@ -67,6 +100,7 @@ UART3_MSR .EQU UART3IOB + 6 ; MODEM STATUS REG
UART3_SCR .EQU UART3IOB + 7 ; SCRATCH REGISTER
UART3_DLL .EQU UART3IOB + 0 ; DLAB=1: DIVISOR LATCH (LS)
UART3_DLM .EQU UART3IOB + 1 ; DLAB=1: DIVISOR LATCH (MS)
UART3_EFR .EQU UART3IOB + 2 ; ENHANCED FEATURE (WHEN LCR = $BF)
;
UART3_DIV .EQU (1843200 / (16 * UART3BAUD))
#ENDIF
@@ -124,50 +158,25 @@ UART0_INIT:
PRTS("UART0: IO=0x$")
LD A,UART0IOB
CALL PRTHEXBYTE
PRTS(" BAUD=$")
LD HL,UART0BAUD / 10
CALL PRTDEC
PRTC('0')
LD A,80H
OUT (UART0_LCR),A ; DLAB ON
LD A,UART0_DIV % $100
OUT (UART0_DLL),A ; SET DIVISOR (LS)
LD A,UART0_DIV / $100
OUT (UART0_DLM),A ; SET DIVISOR (MS)
LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
#IF (UART0AFC)
PRTS(" AFC$")
LD A,$55 ; TEST VALUE
OUT (UART0_SCR),A ; SET SCRATCH REG TO TEST VALUE
LD A,0BFH
OUT (UART0_LCR),A ; SET LCR=$BF TO ATTEMPT TO ACCESS EFR
IN A,(UART0_SCR) ; READ SCRATCH REGISTER
CP $55 ; IF $55, NO EFR
JR NZ,UART0_AFC1 ; NZ, HAVE EFR, DO IT
SET 5,B ; ENABLE AUTO FLOW CONTROL
JR UART0_AFC2
UART0_AFC1:
LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
OUT (UART0_EFR),A ; SAVE IT
UART0_AFC2:
#ENDIF
LD A,03H
OUT (UART0_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
LD A,B ; LOAD MCR VALUE TO SET
OUT (UART0_MCR),A ; SAVE IT
;
; SETUP FOR GENERIC INIT ROUTINE
LD (UART_BASE),A ; IO BASE ADDRESS
LD DE,UART0BAUD / 10 ; BAUD RATE / 10
LD (UART_BAUD),DE ; SAVE IT
LD DE,UART0_DIV ; DIVISOR
LD (UART_DIV),DE ; SAVE IT
;
; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
XOR A ; START WITH NO FEATURES
#IF (UART0FIFO)
; LD A,07H ; ENABLE AND RESET FIFOS
LD A,01H ; ENABLE AND RESET FIFOS
OUT (UART0_FCR),A ; ENABLE FIFOS
PRTS(" FIFO$")
SET UART_FIFO,A ; TURN ON FIFO BIT IF REQUESTED
#ENDIF
RET
#IF (UART0AFC)
SET UART_AFC,A ; TURN ON AFC BIT IF REQUESTED
#ENDIF
LD (UART_FUNC),A ; SAVE IT
;
JP UART_INITP ; HAND OFF TO GENERIC INIT CODE
;
;
;
@@ -232,50 +241,25 @@ UART1_INIT:
PRTS("UART1: IO=0x$")
LD A,UART1IOB
CALL PRTHEXBYTE
PRTS(" BAUD=$")
LD HL,UART1BAUD / 10
CALL PRTDEC
PRTC('0')
LD A,80H
OUT (UART1_LCR),A ; DLAB ON
LD A,UART1_DIV % $100
OUT (UART1_DLL),A ; SET DIVISOR (LS)
LD A,UART1_DIV / $100
OUT (UART1_DLM),A ; SET DIVISOR (MS)
LD B,03H ; B = DEFAULT SETTING FOR MCR (DTR + RTS)
#IF (UART1AFC)
PRTS(" AFC$")
LD A,$55 ; TEST VALUE
OUT (UART1_SCR),A ; SET SCRATCH REG TO TEST VALUE
LD A,0BFH
OUT (UART1_LCR),A ; SET LCR=$BF TO ATTEMPT TO ACCESS EFR
IN A,(UART1_SCR) ; READ SCRATCH REGISTER
CP $55 ; IF $55, NO EFR
JR NZ,UART1_AFC1 ; NZ, HAVE EFR, DO IT
SET 5,B ; ENABLE AUTO FLOW CONTROL
JR UART1_AFC2
UART1_AFC1:
LD A,0C0H ; ENABLE CTS/RTS FLOW CONTROL
OUT (UART1_EFR),A ; SAVE IT
UART1_AFC2:
#ENDIF
LD A,03H
OUT (UART1_LCR),A ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
LD A,B ; LOAD MCR VALUE TO SET
OUT (UART1_MCR),A ; SAVE IT
;
; SETUP FOR GENERIC INIT ROUTINE
LD (UART_BASE),A ; IO BASE ADDRESS
LD DE,UART1BAUD / 10 ; BAUD RATE / 10
LD (UART_BAUD),DE ; SAVE IT
LD DE,UART1_DIV ; DIVISOR
LD (UART_DIV),DE ; SAVE IT
;
; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
XOR A ; START WITH NO FEATURES
#IF (UART1FIFO)
; LD A,07H ; ENABLE AND RESET FIFOS
LD A,01H ; ENABLE AND RESET FIFOS
OUT (UART1_FCR),A ; ENABLE FIFOS
PRTS(" FIFO$")
SET UART_FIFO,A ; TURN ON FIFO BIT IF REQUESTED
#ENDIF
RET
#IF (UART1AFC)
SET UART_AFC,A ; TURN ON AFC BIT IF REQUESTED
#ENDIF
LD (UART_FUNC),A ; SAVE IT
;
JP UART_INITP ; HAND OFF TO GENERIC INIT CODE
;
;
;
@@ -330,3 +314,337 @@ UART1_OST:
RET
;
#ENDIF
;
; UART INITIALIZATION ROUTINE
;
UART_INITP:
LD DE,400 ; WAIT 1/10 SEC FOR UART TO SEND PENDING
CALL VDELAY
; DETECT THE UART TYPE
CALL UART_DETECT ; DETERMINE UART TYPE
LD (UART_TYPE),A ; SAVE TYPE
; HL IS USED BELOW TO REFER TO FEATURE BITS ENABLED
LD HL,UART_FEAT ; HL POINTS TO FEATURE FLAGS BYTE
XOR A ; RESET ALL FEATRUES
LD (HL),A ; SAVE IT
; START OF UART INITIALIZATION, SET BAUD RATE
LD A,80H
UART_OUT(UART_LCR) ; DLAB ON
LD DE,(UART_DIV)
LD A,E
UART_OUT(UART_DLL) ; SET DIVISOR (LS)
LD A,D
UART_OUT(UART_DLM) ; SET DIVISOR (MS)
; SET LCR TO DEFAULT
LD A,$03 ; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
UART_OUT(UART_LCR) ; SAVE IT
; SET MCR TO DEFAULT
LD A,$03 ; DTR + RTS
UART_OUT(UART_MCR) ; SAVE IT
LD A,(UART_TYPE) ; GET UART TYPE
CP UART_16550A ; 16550A OR BETTER?
JR C,UART_INITP1 ; NOPE, SKIP FIFO & AFC FEATURES
LD B,0 ; START BY ASSUMING NO FIFOS, FCR=0
LD A,(UART_FUNC) ; LOAD FIFO ENABLE REQUEST VALUE
BIT UART_FIFO,A ; TEST FOR FIFO REQUESTED
JR Z,UART_FIFO1 ; NOPE
LD B,$07 ; VALUE TO ENABLE AND RESET FIFOS
SET UART_FIFO,(HL) ; RECORD FEATURE ENABLED
UART_FIFO1:
LD A,B ; MOVE VALUE TO A
UART_OUT(UART_FCR) ; DO IT
LD A,(UART_TYPE) ; GET UART TYPE
CP UART_16550C ; 16550C OR BETTER?
JR C,UART_INITP1 ; NOPE, SKIP AFC FEATURES
; BRANCH BASED ON TYPE AFC CONFIGURATION (EFR OR MCR)
LD A,(UART_TYPE) ; GET UART TYPE
CP UART_16650 ; 16650?
JR Z,UART_AFC2 ; USE EFR REGISTER
CP UART_16850 ; 16750?
JR Z,UART_AFC2 ; USE EFR REGISTER
; SET AFC VIA MCR
LD B,$03 ; START WITH DEFAULT MCR
LD A,(UART_FUNC) ; LOAD AFC ENABLE REQUEST VALUE
BIT UART_AFC,A ; TEST FOR AFC REQUESTED
JR Z,UART_AFC1 ; NOPE
SET 5,B ; SET MCR BIT TO ENABLE AFC
SET UART_AFC,(HL) ; RECORD FEATURE ENABLED
UART_AFC1:
LD A,B ; MOVE VALUE TO Ar
UART_OUT(UART_MCR) ; SET AFC VALUE VIA MCR
JR UART_INITP1 ; AND CONTINUE
UART_AFC2: ; SET AFC VIA EFR
LD A,$BF ; VALUE TO ACCESS EFR
UART_OUT(UART_LCR) ; SET VALUE IN LCR
LD B,0 ; ASSUME AFC OFF, EFR=0
LD A,(UART_FUNC) ; LOAD AFC ENABLE REQUEST VALUE
BIT UART_AFC,A ; TEST FOR AFC REQUESTED
JR Z,UART_AFC3 ; NOPE
LD B,$C0 ; ENABLE CTS/RTS FLOW CONTROL
SET UART_AFC,(HL) ; RECORD FEATURE ENABLED
UART_AFC3:
LD A,B ; MOVE VALUE TO A
UART_OUT(UART_EFR) ; SAVE IT
LD A,$03 ; NORMAL LCR VALUE
UART_OUT(UART_LCR) ; SAVE IT
UART_INITP1:
#IF (UART_DEBUG)
PRTS(" [$")
; DEBUG: DUMP UART TYPE
LD A,(UART_TYPE)
CALL PRTHEXBYTE
; DEBUG: DUMP IIR
UART_IN(UART_IIR)
CALL PC_SPACE
CALL PRTHEXBYTE
; DEBUG: DUMP LCR
UART_IN(UART_LCR)
CALL PC_SPACE
CALL PRTHEXBYTE
; DEBUG: DUMP MCR
UART_IN(UART_MCR)
CALL PC_SPACE
CALL PRTHEXBYTE
; DEBUG: DUMP EFR
LD A,$BF
UART_OUT(UART_LCR)
UART_IN(UART_EFR)
PUSH AF
LD A,$03
UART_OUT(UART_LCR)
POP AF
CALL PC_SPACE
CALL PRTHEXBYTE
PRTC(']')
#ENDIF
; PRINT THE UART TYPE
LD A,(UART_TYPE)
RLCA
LD HL,UART_TYPE_MAP
LD D,0
LD E,A
ADD HL,DE ; HL NOW POINTS TO MAP ENTRY
LD A,(HL)
INC HL
LD D,(HL)
LD E,A ; HL NOW POINTS TO STRING
CALL PC_SPACE
CALL WRITESTR ; PRINT THE STRING
;
; ALL DONE IF NO UART WAS DETECTED
LD A,(UART_TYPE)
OR A
JR Z,UART_INITP3
;
; PRINT BAUD RATE
PRTS(" BAUD=$")
LD HL,(UART_BAUD)
CALL PRTDEC
PRTC('0')
;
; PRINT FEATURES ENABLED
LD A,(UART_FEAT)
BIT UART_FIFO,A
JR Z,UART_INITP2
PRTS(" FIFO$")
UART_INITP2:
BIT UART_AFC,A
JR Z,UART_INITP3
PRTS(" AFC$")
UART_INITP3:
;
RET
;
; UART DETECTION ROUTINE
;
UART_DETECT:
;
; SEE IF UART IS THERE BY CHECKING DLAB FUNCTIONALITY
XOR A ; ZERO ACCUM
UART_OUT(UART_IER) ; IER := 0
LD A,$80 ; DLAB BIT ON
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW ACTIVE)
LD A,$5A ; LOAD TEST VALUE
UART_OUT(UART_DLM) ; OUTPUT TO DLM
UART_IN(UART_DLM) ; READ IT BACK
CP $5A ; CHECK FOR TEST VALUE
JR NZ,UART_DETECT_NONE ; NOPE, UNKNOWN UART OR NOT PRESENT
XOR A ; DLAB BIT OFF
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW INACTIVE)
UART_IN(UART_IER) ; READ IER
CP $5A ; CHECK FOR TEST VALUE
JR Z,UART_DETECT_NONE ; IF STILL $5A, UNKNOWN OR NOT PRESENT
;
; TEST FOR FUNCTIONAL SCRATCH REG, IF NOT, WE HAVE AN 8250
LD A,$5A ; LOAD TEST VALUE
UART_OUT(UART_SCR) ; PUT IT IN SCRATCH REGISTER
UART_IN(UART_SCR) ; READ IT BACK
CP $5A ; CHECK IT
JR NZ,UART_DETECT_8250 ; STUPID 8250
;
; TEST FOR EFR REGISTER WHICH IMPLIES 16650/850
LD A,$BF ; VALUE TO ENABLE EFR
UART_OUT(UART_LCR) ; WRITE IT TO LCR
UART_IN(UART_SCR) ; READ SCRATCH REGISTER
CP $5A ; SPR STILL THERE?
JR NZ,UART_DETECT1 ; NOPE, HIDDEN, MUST BE 16650/850
;
; RESET LCR TO DEFAULT
XOR A ; ZERO ACCUM
UART_OUT(UART_LCR) ; RESET LCR
;
; TEST FCR TO ISOLATE 16450/550/550A
LD A,$E7 ; TEST VALUE
UART_OUT(UART_FCR) ; PUT IT IN FCR
UART_IN(UART_IIR) ; READ BACK FROM IIR
BIT 6,A ; BIT 6 IS FIFO ENABLE, LO BIT
JR Z,UART_DETECT_16450 ; IF NOT SET, MUST BE 16450
BIT 7,A ; BIT 7 IS FIFO ENABLE, HI BIT
JR Z,UART_DETECT_16550 ; IF NOT SET, MUST BE 16550
BIT 5,A ; BIT 5 IS 64 BYTE FIFO
JR Z,UART_DETECT2 ; IF NOT SET, MUST BE 16550A/C
JR UART_DETECT_16750 ; ONLY THING LEFT IS 16750
;
UART_DETECT1: ; PICK BETWEEN 16650/850
; NEED TO RESET LCR
XOR A ; DLAB BIT OFF
UART_OUT(UART_LCR) ; OUTPUT TO LCR (DLAB REGS NOW INACTIVE)
; NOT SURE HOW TO DIFFERENTIATE 16650 FROM 16850 YET
JR UART_DETECT_16650 ; ASSUME 16650
RET
;
UART_DETECT2: ; PICK BETWEEN 16650A/C
; SET AFC BIT IN FCR
LD A,$20 ; SET AFC BIT, FCR:5
UART_OUT(UART_FCR) ; WRITE NEW FCR VALUE
;
; READ IT BACK, IF SET, WE HAVE 16550C
UART_IN(UART_FCR) ; READ BACK FCR
BIT 5,A ; CHECK AFC BIT
JR Z,UART_DETECT_16550A ; NOT SET, SO 16550A
JR UART_DETECT_16550C ; IS SET, SO 16550C
;
UART_DETECT_NONE:
LD A,UART_NONE
RET
;
UART_DETECT_8250:
LD A,UART_8250
RET
;
UART_DETECT_16450:
LD A,UART_16450
RET
;
UART_DETECT_16550:
LD A,UART_16550
RET
;
UART_DETECT_16550A:
LD A,UART_16550A
RET
;
UART_DETECT_16550C:
LD A,UART_16550C
RET
;
UART_DETECT_16650:
LD A,UART_16650
RET
;
UART_DETECT_16750:
LD A,UART_16750
RET
;
UART_DETECT_16850:
LD A,UART_16850
RET
;
; ROUTINES TO READ/WRITE PORTS INDIRECTLY
;
; READ VALUE OF UART PORT ON TOS INTO REGISTER A
;
UART_INP:
EX (SP),HL ; SWAP HL AND TOS
PUSH BC ; PRESERVE BC
LD A,(UART_BASE) ; GET UART IO BASE PORT
OR (HL) ; OR IN REGISTER ID BITS
LD C,A ; C := PORT
INC HL ; BUMP HL PAST REG ID PARM
IN A,(C) ; READ PORT INTO A
POP BC ; RESTORE BC
EX (SP),HL ; SWAP BACK HL AND TOS
RET
;
; WRITE VALUE IN REGISTER A TO UART PORT ON TOS
;
UART_OUTP:
EX (SP),HL ; SWAP HL AND TOS
PUSH BC ; PRESERVE BC
PUSH AF ; SAVE AF (VALUE TO WRITE)
LD A,(UART_BASE) ; GET UART IO BASE PORT
OR (HL) ; OR IN REGISTER ID BITS
LD C,A ; C := PORT
INC HL ; BUMP HL PAST REG ID PARM
POP AF ; RESTORE VALUE TO WRITE
OUT (C),A ; WRITE VALUE TO PORT
POP BC ; RESTORE BC
EX (SP),HL ; SWAP BACK HL AND TOS
RET
;
;
;
UART_TYPE_MAP:
.DW UART_STR_NONE
.DW UART_STR_8250
.DW UART_STR_16450
.DW UART_STR_16550
.DW UART_STR_16550A
.DW UART_STR_16550C
.DW UART_STR_16650
.DW UART_STR_16750
.DW UART_STR_16850
UART_STR_NONE .DB "<NOT PRESENT>$"
UART_STR_8250 .DB "8250$"
UART_STR_16450 .DB "16450$"
UART_STR_16550 .DB "16550$"
UART_STR_16550A .DB "16550A$"
UART_STR_16550C .DB "16550C$"
UART_STR_16650 .DB "16650$"
UART_STR_16750 .DB "16750$"
UART_STR_16850 .DB "16850$"
;
; WORKING VARIABLES
;
UART_BASE .DB 0 ; BASE IO ADDRESS FOR ACTIVE UART
UART_TYPE .DB 0 ; UART TYPE DISCOVERED
UART_FEAT .DB 0 ; UART FEATURES DISCOVERED
UART_BAUD .DW 0 ; BAUD RATE
UART_DIV .DW 0 ; BAUD DIVISOR
UART_FUNC .DB 0 ; UART FUNCTIONS REQUESTED
;
;
;
UART_FIFO .EQU 0 ; FIFO ENABLE BIT
UART_AFC .EQU 1 ; AUTO FLOW CONTROL ENABLE BIT

4
Source/ver.inc
View File

@@ -1,6 +1,6 @@
#DEFINE RMJ 2
#DEFINE RMN 5
#DEFINE RUP 0
#DEFINE RTP 12
#DEFINE BIOSVER "2.5 - Beta 12"
#DEFINE RTP 13
#DEFINE BIOSVER "2.5 - Beta 13"
#DEFINE REVISION 412