preliminary version of std-zeta.inc, used in new schema

branches/s100/Source/std-zeta.inc

@@ -0,0 +1,98 @@
+; ~/RomWBW/branches/s100/Source/std-zeta.asm 1/19/2013 dwg - 
+;
+;==============================================================================
+;   STANDARD INCLUDE STUFF
+;==============================================================================
+;
+; DEPRECATED STUFF!!!
+;
+;;DIOPLT		.EQU	0		; DEPRECATED!!!
+;;VDUMODE		.EQU	0		; DEPRECATED!!!
+;;BIOSSIZE	.EQU	0100H		; DEPRECATED!!!
+;
+; PRIMARY HARDWARE PLATFORMS
+;
+;PLT_N8VEM	.EQU	1		; N8VEM ECB Z80 SBC
+;PLT_ZETA	.EQU	2		; ZETA Z80 SBC
+;PLT_N8		.EQU	3		; N8 (HOME COMPUTER) Z180 SBC
+;PLT_S2I		.EQU	4		; SCSI2IDE
+;PLT_S100	.EQU	5		; S100COMPUTERS Z80 based system
+
+; BOOT STYLE
+;
+;BT_MENU		.EQU	1		; WAIT FOR MENU SELECTION AT LOADER PROMPT
+;BT_AUTO		.EQU	2		; AUTO SELECT BOOT_DEFAULT AFTER BOOT_TIMEOUT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;
+; VDA DEVICES (VIDEO DISPLAY ADAPTER)
+;
+;VDADEV_NONE	.EQU	$00		; NO VDA DEVICE
+
+;
+; CHARACTER DEVICES
+;
+;CIODEV_UART	.EQU	$00
+CIODEV_PRPCON	.EQU	$60
+CIODEV_PPPCON	.EQU	$70
+CIODEV_CRT	.EQU	$D0
+CIODEV_BAT	.EQU	$E0
+;CIODEV_NUL	.EQU	$F0
+;
+; DISK DEVICES (ONLY FIRST NIBBLE RELEVANT, SECOND NIBBLE RESERVED FOR UNIT)
+;
+;DIODEV_MD	.EQU	$00
+DIODEV_FD	.EQU	$10
+DIODEV_IDE	.EQU	$20
+DIODEV_ATAPI	.EQU	$30
+DIODEV_PPIDE	.EQU	$40
+DIODEV_SD	.EQU	$50
+DIODEV_PRPSD	.EQU	$60
+DIODEV_PPPSD	.EQU	$70
+DIODEV_HDSK	.EQU	$80
+;
+;
+; PPIDE MODE SELECTIONS
+;
+;PPIDEMODE_STD	.EQU	1		; STANDARD N8VEM PARALLEL PORT
+;PPIDEMODE_DIO3	.EQU	2		; DISKIO V3 PARALLEL PORT
+;
+
+;
+; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
+;
+MPCL_RAM	.EQU 	78H		; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
+MPCL_ROM	.EQU 	7CH		; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
+RTC		.EQU	70H		; ADDRESS OF RTC LATCH AND INPUT PORT
+
+;__HARDWARE_INTERFACES________________________________________________________________________________________________________________ 
+;
+; PPI 82C55 I/O IS DECODED TO PORT 60-67
+;
+PPIBASE		.EQU	60H
+PPIA		.EQU 	PPIBASE + 0	; PORT A
+PPIB		.EQU 	PPIBASE + 1	; PORT B
+PPIC		.EQU 	PPIBASE + 2	; PORT C
+PPIX	 	.EQU 	PPIBASE + 3	; PPI CONTROL PORT
+;
+; 16C550 SERIAL LINE UART
+;
+SIO_BASE	.EQU	68H
+SIO_RBR		.EQU	SIO_BASE + 0	; DLAB=0: RCVR BUFFER REG (READ ONLY)
+SIO_THR		.EQU	SIO_BASE + 0	; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
+SIO_IER		.EQU	SIO_BASE + 1	; DLAB=0: INT ENABLE REG
+SIO_IIR		.EQU	SIO_BASE + 2	; INT IDENT REGISTER (READ ONLY)
+SIO_FCR		.EQU	SIO_BASE + 2	; FIFO CONTROL REG (WRITE ONLY)
+SIO_LCR		.EQU	SIO_BASE + 3	; LINE CONTROL REG
+SIO_MCR		.EQU	SIO_BASE + 4	; MODEM CONTROL REG
+SIO_LSR		.EQU	SIO_BASE + 5	; LINE STATUS REG
+SIO_MSR		.EQU	SIO_BASE + 6	; MODEM STATUS REG
+SIO_SCR		.EQU	SIO_BASE + 7	; SCRATCH REGISTER
+SIO_DLL		.EQU	SIO_BASE + 0	; DLAB=1: DIVISOR LATCH (LS)
+SIO_DLM		.EQU	SIO_BASE + 1	; DLAB=1: DIVISOR LATCH (MS)
+
+;;;;;;;;;;;;;;;;;;;;;;
+; eof - std-zeta.inc ;
+;;;;;;;;;;;;;;;;;;;;;;
+