diff --git a/Source/Apps/FAT/FAT.com b/Source/Apps/FAT/fat.com similarity index 100% rename from Source/Apps/FAT/FAT.com rename to Source/Apps/FAT/fat.com diff --git a/Source/Apps/FDU/FDU.asm b/Source/Apps/FDU/fdu.asm similarity index 100% rename from Source/Apps/FDU/FDU.asm rename to Source/Apps/FDU/fdu.asm diff --git a/Source/Apps/FDU/FDU.txt b/Source/Apps/FDU/fdu.txt similarity index 100% rename from Source/Apps/FDU/FDU.txt rename to Source/Apps/FDU/fdu.txt diff --git a/Source/Apps/MBC/button2.asm b/Source/Apps/MBC/button2.asm new file mode 100644 index 00000000..001f8d48 --- /dev/null +++ b/Source/Apps/MBC/button2.asm @@ -0,0 +1,19 @@ +; test program for user button on Z80 MBC clock board +; by Andrew Lynch, 6 Jul 2021 + + + ORG 00100H + +MAIN_LOOP: + + IN A,($70) ; READ USER BUTTON STATUS + AND %01000000 ; REMOVE ALL EXCEPT USER BUTTON (D6) + ; 0=PRESSED, 1=NOT PRESSED + JR NZ,MAIN_LOOP ; IF NOT PRESSED TRY AGAIN + + LD A,%00000011 ; TURN ON BOTH USER LEDS + OUT ($70),A ; + + RET + + end diff --git a/Source/Apps/MBC/leds2.asm b/Source/Apps/MBC/leds2.asm new file mode 100644 index 00000000..ddf36f81 --- /dev/null +++ b/Source/Apps/MBC/leds2.asm @@ -0,0 +1,8 @@ +; program to test user LEDs on Z80 MBC clock board +; by Andrew Lynch, 6 Jul 2021 + + org $0100 + LD A,%00000011 + OUT ($70),A ; turn on USERLED0 and USERLED1 + RET + end diff --git a/Source/Apps/MBC/tone3.asm b/Source/Apps/MBC/tone3.asm new file mode 100644 index 00000000..620841e0 --- /dev/null +++ b/Source/Apps/MBC/tone3.asm @@ -0,0 +1,35 @@ +; program to test user buzzer/speaker on Z80 MBC clock board +; by Andrew Lynch, 6 Jul 2021 + + org $0100 + + LD HL,$7FFF ; INITIALIZE OUTER LOOP + LD DE,$0001 ; DECREMENT VALUE + +START: + + LD A,%00000100 + OUT ($70),A ; TURN ON SPEAKER + + LD B,$80 ; HOLD SPEAKER ON FOR 128 COUNTS +LOOP1: DJNZ LOOP1 + + LD A,%00000000 + OUT ($70),A ; TURN OFF SPEAKER + + LD B,$80 ; HOLD SPEAKER OFF FOR 128 COUNTS +LOOP2: DJNZ LOOP2 + + SBC HL,DE ; REDUCE OUTER LOOP BY 1 + + JR NZ,START ; LOOP 32768 TIMES, ABOUT 15 SECONDS + + LD A,%00000011 + OUT ($70),A ; TURN ON BOTH USER LEDS + +; HALT ; HALT & TURN ON HALT LED + + RET + + end + diff --git a/Source/Apps/Makefile b/Source/Apps/Makefile index bf58bc14..c2785b51 100644 --- a/Source/Apps/Makefile +++ b/Source/Apps/Makefile @@ -1,6 +1,6 @@ -OBJECTS = SysGen.com Survey.com \ - SysCopy.com Assign.com Format.com Talk.com Mode.com RTC.com \ - Timer.com IntTest.com RTCds7.com RTChb.com +OBJECTS = sysgen.com survey.com \ + syscopy.com assign.com format.com talk.com mode.com rtc.com \ + timer.com inttest.com rtcds7.com rtchb.com ppidetst.com tstdskng.com OTHERS = *.hex *.com SUBDIRS = XM FDU FAT Tune I2C DEST = ../../Binary/Apps @@ -10,5 +10,5 @@ include $(TOOLS)/Makefile.inc USETASM = 1 -Survey.com: USETASM=0 +survey.com: USETASM=0 diff --git a/Source/Apps/Tune/Build.cmd b/Source/Apps/Tune/Build.cmd index 82fa4c33..98901a70 100644 --- a/Source/Apps/Tune/Build.cmd +++ b/Source/Apps/Tune/Build.cmd @@ -5,11 +5,11 @@ set TOOLS=../../../Tools set PATH=%TOOLS%\tasm32;%PATH% set TASMTABS=%TOOLS%\tasm32 -tasm -t180 -g3 -fFF -dWBW Tune.asm Tune.com Tune.lst -tasm -t180 -g3 -fFF -dZX Tune.asm Tunezx.com Tunezx.lst -tasm -t180 -g3 -fFF -dMSX Tune.asm Tunemsx.com Tunemsx.lst +tasm -t180 -g3 -fFF -dWBW tune.asm tune.com tune.lst +tasm -t180 -g3 -fFF -dZX tune.asm tunezx.com tunezx.lst +tasm -t180 -g3 -fFF -dMSX tune.asm tunemsx.com tunemsx.lst if errorlevel 1 goto :eof -copy /Y Tune*.com ..\..\..\Binary\Apps\ +copy /Y tune*.com ..\..\..\Binary\Apps\ copy /Y Tunes\*.* ..\..\..\Binary\Apps\Tunes\ \ No newline at end of file diff --git a/Source/Apps/Tune/Tune.asm b/Source/Apps/Tune/tune.asm similarity index 100% rename from Source/Apps/Tune/Tune.asm rename to Source/Apps/Tune/tune.asm diff --git a/Source/Apps/Assign.asm b/Source/Apps/assign.asm similarity index 100% rename from Source/Apps/Assign.asm rename to Source/Apps/assign.asm diff --git a/Source/Apps/ppidetst.asm b/Source/Apps/ppidetst.asm new file mode 100644 index 00000000..85fcd3f5 --- /dev/null +++ b/Source/Apps/ppidetst.asm @@ -0,0 +1,1371 @@ +; N8VEM PPI IDE test program for checkout of IDE drive connected to the 8255 PPI +; +; Written by Max Scane July 2009 +; Based on work by Paul Stoffregen (www.pjrc.com) +; +; Note: due to a known anomaly in the 8255, some signals ( all active low signals) on the IDE bus require an inverter (74LS04 or 74LS14) +; between the 8255 and the IDE drive. +; This is due to the 8255 returning all signals to 0 (low) when a mode change is performed (for read and write to IDE data bus). +; +; This test program will allow you to check out an attached IDE drive using the basic commands: +; +; u - Spin up the drive +; d - Spin down the drive +; s - Read and print out drive status +; i - Execute drive ID command and print result correctly +; r - Read the current LBA into the sector buffer and print status +; w - Write the sector buffer to the current LBA and print status +; l - Change the current LBA +; h - Dump the current sector buffer in hexdump format +; f - format drive for CP/M use (fill with 0xE5) +; e - Display drive error information +; x - Return to CP/M +; n - read and hexdump next LBA +; ? - Display command menu help +; p - set PPI port +; +; +; +; +; - Updated December 2014 MS - changed IO routines to support different PPI ports. +; - Updated July 2021 Andrew Lynch - Minor cosmetic updates + +;********************* HARDWARE IO ADR ************************************ + +DEFBASE: .EQU 60H ; PPI base I/O address default + +; +; Offsets to the various PPI registers + +IDELSB: .EQU 0 ; LSB +IDEMSB: .EQU 1 ; MSB +IDECTL: .EQU 2 ; Control Signals +PIOCONT: .EQU 3 ; CONTROL BYTE PIO 82C55 + +; PPI control bytes for read and write to IDE drive + +rd_ide_8255: .EQU 10010010b ; ide_8255_ctl out, ide_8255_lsb/msb input +wr_ide_8255: .EQU 10000000b ; all three ports output + +;IDE control lines for use with ide_8255_ctl. Change these 8 +;constants to reflect where each signal of the 8255 each of the +;IDE control signals is connected. All the control signals must +;be on the same port, but these 8 lines let you connect them to +;whichever pins on that port. + +ide_a0_line: .EQU 01H ; direct from 8255 to IDE interface +ide_a1_line: .EQU 02H ; direct from 8255 to IDE interface +ide_a2_line: .EQU 04H ; direct from 8255 to IDE interface +ide_cs0_line: .EQU 08H ; inverter between 8255 and IDE interface +ide_cs1_line: .EQU 10H ; inverter between 8255 and IDE interface +ide_wr_line: .EQU 20H ; inverter between 8255 and IDE interface +ide_rd_line: .EQU 40H ; inverter between 8255 and IDE interface +ide_rst_line: .EQU 80H ; inverter between 8255 and IDE interface + + +;------------------------------------------------------------------ +; More symbolic constants... these should not be changed, unless of +; course the IDE drive interface changes, perhaps when drives get +; to 128G and the PC industry will do yet another kludge. + +;some symbolic constants for the ide registers, which makes the +;code more readable than always specifying the address pins + +ide_data: .EQU ide_cs0_line +ide_err: .EQU ide_cs0_line + ide_a0_line +ide_sec_cnt: .EQU ide_cs0_line + ide_a1_line +ide_sector: .EQU ide_cs0_line + ide_a1_line + ide_a0_line +ide_cyl_lsb: .EQU ide_cs0_line + ide_a2_line +ide_cyl_msb: .EQU ide_cs0_line + ide_a2_line + ide_a0_line +ide_head: .EQU ide_cs0_line + ide_a2_line + ide_a1_line +ide_command: .EQU ide_cs0_line + ide_a2_line + ide_a1_line + ide_a0_line +ide_status: .EQU ide_cs0_line + ide_a2_line + ide_a1_line + ide_a0_line +ide_control: .EQU ide_cs1_line + ide_a2_line + ide_a1_line +ide_astatus: .EQU ide_cs1_line + ide_a2_line + ide_a1_line + ide_a0_line + +;IDE Command Constants. These should never change. +ide_cmd_recal: .EQU 10H +ide_cmd_read: .EQU 20H +ide_cmd_write: .EQU 30H +ide_cmd_init: .EQU 91H +ide_cmd_id: .EQU 0ECH +ide_cmd_spindown: .EQU 0E0H +ide_cmd_spinup: .EQU 0E1H + +CR: .EQU 0Dh +LF: .EQU 0Ah +BELL: .EQU 07H + + + .org 100H + +start: + +; save stack pointer so that we can return to calling program + + ld (savsp),sp + ld sp,stack + + call set_ppi_rd ; setup PPI chip to known state + + ld hl,lba1 ; zero LBA variables + call clrlba + + ld hl,lba2 + call clrlba + + ld hl,lba3 + call clrlba + + + call print + .db "PPI IDE test program v0.6b",CR,LF,0 + + call prport + call prstatus + call prlba + + call ide_init + call prstatus + + call crlf + +menu: + call print ; display prompt + .db "Enter command (u,d,s,i,r,w,l,h,f,e,n,p,?,x) > ",0 + + call cin ; get command from console in reg A + push af + call crlf + pop af + +mnu1: + cp 'd' ; spin down command + jr nz,mnu2 + call spindown + jr menu +mnu2: + cp 'u' ; spinup command + jr nz,mnu3 + call spinup + jr menu + +mnu3: + cp 's' ; print IDE status reg contents + jr nz,mnu4 + call prstatus + jr menu + +mnu4: + cp 'i' + jr nz,mnu5 ; drive ID command + call drive_id + jr menu + +mnu5: + cp 'r' + jr nz,mnu6 ; read command + call prlba ; print out the current LBA + call read_sector ; read current LBA + call prstatus + jr menu + +mnu6: + cp 'w' + jr nz,mnu7 ; write command + call prlba ; print out the current LBA + call write_sector ; write current LBA + call prstatus + jr menu + +mnu7: + cp 'l' + jr nz,mnu8 ; LBA command + call prlba ; print out the current LBA +mnu7a: + call print + .db "Enter new LBA: ",0 + + ld de,lba1 ; get LBA in lba1 + call getlba + jp nc,menu ; valid, finished + + call print + .db "Invalid LBA",CR,LF,0 + + jr mnu7a ; try again + + +mnu8: + cp 'h' + jr nz,mnu9 ; hexdump command + call hexdump ; hexdump the current sector buffer + jp menu + +mnu9: + cp 'f' + jr nz,mnua ; drive format + call format + jp menu + +mnua: + cp 'e' + jr nz,mnub ; get error register + call get_err + push af + call print + .db "Error register is: ",0 + + pop af + call prhex + call crlf + + + ld a,ide_head + call ide_read + ld a,c + call prhex + + ld a,ide_cyl_msb + call ide_read + ld a,c + call prhex + + ld a,ide_cyl_lsb + call ide_read + ld a,c + call prhex + + + ld a,ide_sector + call ide_read + ld a,c + call prhex + + call crlf + + ld a,ide_sec_cnt + call ide_read + ld a,c + call prhex + call crlf + + jp menu + + +mnub: + cp 'n' + jr nz,mnuc + ld hl,lba1 + call inclba + call prlba + call read_sector + call hexdump + jp menu + +mnuc: + cp 'p' + jr nz,mnux + call prport +mnuca: + call print + .db "Enter new PPI base port: ",0 + + ld a,(ppibase) + call gethexbyte + jr c,mnucb + ld (ppibase),a ; save it + call prport + jp menu + +mnucb: + call print + .db "Invalid PPI base port value",CR,LF,0 + jr mnuca + +mnux: + cp 'x' ; exit command + jp nz,mnuhlp + ld sp,(savsp) + ret + + +mnuhlp: + call print + .db "Commands available:",CR,LF,LF + .db "u - Spin Up drive",CR,LF + .db "d - Spin Down drive",CR,LF + .db "s - Print drive Status",CR,LF + .db "i - Query drive using ID command",CR,LF + .db "r - Read a sector addressed by the lba variable",CR,LF + .db "w - Write a sector adresses by the lba variable",CR,LF + .db "l - Change the current LBA variable",CR,LF + .db "h - Hexdump the current buffer",CR,LF + .db "f - Format the drive for CP/M use (fill with 0xE5)",CR,LF + .db "e - Display drive Error information",CR,LF + .db "p - Change base IO port",CR,LF + .db "? - Display command menu help",CR,LF + .db "x - eXit from this utility",CR,LF,LF,0 + jp menu + + +format: + call print + .db "Warning - this command will write data to the drive",CR,LF,LF + .db "All existing data will be over written",CR,LF,LF + .db "Is that what you want to do ? ",0 + + call cin ; get answer + cp 'y' + jr z,fmt1 ; if yes then continue + call print + .db " Command aborted",CR,LF,0 + ret + +fmt1: + ld a,0E5h + call fillbuf ; setup sector buffer +fmt2: + + call print + .db CR,LF,"Enter starting LBA: ",0 + + ld de,lba2 ; starting LBA + call getlba + jr nc,fmt3 + + call print + .db "Invalid LBA",CR,LF,0 + jr fmt2 ; try again + +fmt3: + + call crlf + +fmt4: + call print + .db "Enter ending LBA: ",0 + + ld de,lba3 ; ending LBA + call getlba + jr nc,fmt5 + + call print + .db "Invalid LBA",CR,LF,0 + + jr fmt4 ; try again + +fmt5: + call crlf + + call print ; say what is going to happen + .db "Format will start at LBA ",0 + + ld a,(lba2+3) + call prhex + ld a,(lba2+2) + call prhex + ld a,(lba2+1) + call prhex + ld a,(lba2) + call prhex + + call print + .db " and finish at LBA ",0 + ld a,(lba3+3) + call prhex + ld a,(lba3+2) + call prhex + ld a,(lba3+1) + call prhex + ld a,(lba3) + call prhex + + call crlf + call print + .db "Type y to continue or any other key to abort ",0 + + call cin + cp 'y' + jp nz,fmtx + call crlf + + ; add the actual format code here + ; get starting LBA + ; get ending LBA + ; fill buffer with E5 + + ld hl,lba2 + ld de,lba1 + call cpylba ; copy start LBA to LBA + call inclba + + +fmt6: + push hl + call print ; display progress + .db "Writing LBN: ",0 + ld a,(lba1+3) + call prhex + ld a,(lba1+2) + call prhex + ld a,(lba1+1) + call prhex + ld a,(lba1) + call prhex + ld a,CR + call cout + pop hl + +; do some stuff to format here + call write_sector + +; need to check status after each call and check for errors +; + ld hl,lba1 ; LBA for disk operation + call inclba + + ld hl,lba1 + ld de,lba3 + call cplba + + jp nz,fmt6 + + call crlf + +fmtx: + call print ; finished + .db "Format complete",CR,LF,0 + ret + + +getlba: ; get an LBA value from the console and validate it + push de ; save LBA variable + ld c,0ah ; bdos read console buffer + ld de,conbuf + call 5 ; get edited string + + call crlf + + ; ok we now have an ascii string representing the LBA. now we have to validate it + + pop de + ld hl,conbuf + inc hl + ld b,(hl) ; get character count +glba1: + inc hl ; HL = address of buffer + ld a,(hl) ; get next character + + call ishex + ret c ; return with carry set if any char is invalid + + ; ok we are here when we have a valid character (0-9,A-F,a-f) need to convert to binary + ; character is still in A + + cp 3AH ; test for 0-9 + jp m,glba4 + cp 47H ; test for A-F + jp m,glba3 + cp 67H ; test for a-f + jp m,glba2 + +glba2: + sub 20H ; character is a-f +glba3: + sub 07h ; character is A-F +glba4: + sub 030H ; character is 0-9 + + ld (hl),a ; save back in buffer as binary + djnz glba1 ; continue checking the buffer + +; need to pack bytes into the destination LBA which is in de and points to the LSB + +glba5: + +; - need to change the endian-ness + push de + ex de,hl ; clear LBA ready +; push de ; address of LBA +; pop hl ; address of input buffer + ld a,0 ; zero existing LBA variable + ld (hl),a + inc hl + ld (hl),a + inc hl + ld (hl),a + inc hl + ld (hl),a + + ex de,hl ; de now positioned at end of LBA + pop de ; restore LBA + ; de still contains dest address + ; now pack and store LBA + + ld hl,conbuf+1 ; get character count + ld b,(hl) + inc hl ; point to first character in buffer + +glba6: + push de ; save starting address for next subsequent rotations + ld a,(hl) ; get next char from buffer + inc hl ; next character + ex de,hl ; switch to LBA + rld ; shift nibble into LBA + inc hl + rld + inc hl + rld + inc hl + rld + ex de,hl ; back to console buffer + pop de ; restore address of LBA + djnz glba6 ; process next character + + scf + ccf ; exit with carry clear = success + ret + + +gethexbyte: + push af ; save incoming value + ld c,0ah ; bdos read console buffer + ld de,conbuf + call 5 ; get edited string + call crlf + pop de ; restore incoming to d + + ; ok we should now have a string with a hex number + ld hl,conbuf + inc hl + ld a,(hl) ; get character count + inc hl + cp 3 + jr c,ghb0 ; ok if <= 2 chars + scf ; signal error + ret ; and return + +ghb0: + or a ; set flags + jr nz,ghb1 ; got chars, go ahead + ld a,d ; restore incoming value + or a ; signal success + ret ; and done + +ghb1: + ld b,a ; count to b + ld c,0 ; initial value + +ghb2: + ld a,(hl) ; get next char + inc hl + call ishex + ret c ; abort on non-hex char + + ; ok we are here when we have a valid character (0-9,A-F,a-f) need to convert to binary + ; character is still in A + + cp 3AH ; test for 0-9 + jp m,ghb2c + cp 47H ; test for A-F + jp m,ghb2b + cp 67H ; test for a-f + jp m,ghb2a +ghb2a: sub 20H ; character is a-f +ghb2b: sub 07H ; character is A-F +ghb2c: sub 30H ; character is 0-9 + + rlc c ; multiply cur value by 16 + rlc c + rlc c + rlc c + add a,c ; add to accum + ld c,a ; put back in c + + djnz ghb2 ; loop thru all chars + + ld a,c ; into a for return + or a ; signal success + ret ; done + +ishex: + cp 30h ; check if less than character 0 + jp m,nothex + cp 3Ah ; check for > 9 + jp m,ishx1 ; ok, character is 1-9 + + cp 41h ; check for character less than A + jp m,nothex + cp 47H ; check for characters > F + jp m,ishx1 + + cp 61H ; check for characters < a + jp m,nothex + + cp 67H ; check for character > f + jp m,ishx1 +nothex: + scf ; set carry to indicate fail + ret + +ishx1: + scf + ccf + ret + + + +fillbuf: + ; fill sector buffer with character specified in A + ld hl,buffer + ld b,0 +fb1: + ld (hl),a ; store character in buffer + inc hl + ld (hl),a + inc hl + djnz fb1 + ret + + +hexdump: + + call print ; print heading + .db "Current sector buffer contents:",CR,LF,LF,0 + + ld b,32 ; line counter + ld hl,buffer ; address of buffer to dump +hxd1: + + push bc ; save loop counter + push hl ; save address pointer + + push hl + ld a,h + call prhex ; print hi byte of address + pop hl + + push hl + ld a,l + call prhex ; print lo byte of address + ld a,' ' + call cout + pop hl + + + ld b,16 ; how many characters do we display +hxd2: + push bc + + ld a,(hl) ; get byte from buffer + inc hl + push hl + + call prhex ; display it in hex + ld a,' ' + call cout + + pop hl + pop bc + djnz hxd2 + + pop hl + + ld b,16 ; how many characters do we display +hxd3: + push bc + + ld a,(hl) ; get byte from buffer + inc hl + push hl + + call prascii ; display it in ASCII + + pop hl + pop bc + djnz hxd3 + + push hl + call crlf + + pop hl + pop bc + + ld a,b ; check for screen pause + cp 16 + jp nz,hxd4 + + push hl + push bc + call cin ; wait for a character + pop bc + pop hl + +hxd4: + djnz hxd1 ; continue if not at end of buffer + + call crlf + call crlf + ret + +prascii: + + cp 20H + jp m,pra1 ; anything less than 20H is non-printable + cp 7fH ; anything greater than 7E is non-printable + jp m,pra2 +pra1: + ld a,'.' +pra2: + call cout + ret +; +; +; +; ------------------------------------------------------------------------- +; +; LBA manipulation routines; +; +cpylba: + ; copy LBA to LBA + ; source = HL, Destination = DE + ld bc,04H + ldir + ret + +; ------------------------------------------------------------------------- + +inclba: + ld a,(hl) ; first byte + add a,1 + ld (hl),a + ret nc + + inc hl ;second byte + ld a,(hl) + add a,1 + ld (hl),a + ret nc + + inc hl ; third byte + ld a,(hl) + add a,1 + ld (hl),a + ret nc + + inc hl ; fourth byte (MSB) + ld a,(hl) + add a,1 + ld (hl),a + + ret + +; ------------------------------------------------------------------------- + +cplba: ; compare LBA + ; addresses by HL and DE + + ld a,(hl) ; start at LSB + inc hl + ex de,hl + cp (hl) + ret nz + inc hl + ex de,hl + + ld a,(hl) + inc hl + ex de,hl + cp (hl) + ret nz + inc hl + ex de,hl + + ld a,(hl) + inc hl + ex de,hl + cp (hl) + ret nz + inc hl + ex de,hl + + ld a,(hl) + inc hl + ex de,hl + cp (hl) + ret + + ret nz + inc hl + ex de,hl + + ret + +; ------------------------------------------------------------------------- + +prlba: + + call print + .db "Current LBA = ",0 + ld a,(lba1+3) + call prhex + ld a,(lba1+2) + call prhex + ld a,(lba1+1) + call prhex + ld a,(lba1) + call prhex + call crlf + call crlf + ret + +; ------------------------------------------------------------------------- + +prport: + call print + .db "Current PPI base port: 0x",0 + ld a,(ppibase) + call prhex + call crlf + ret + + +clrlba: + ld a,0 + ld b,4 +clr32b1: + ld (hl),a + inc hl + djnz clr32b1 + ret + + +; ------------------------------------------------------------------------- + +prstatus: + call print + .db "status = ",0 + + ld a,ide_status ; read IDE status register + call ide_read + ld a,c ; returned value + call prhex + + call crlf + ret + + + + +print: + pop hl ; get address of text + ld a,(hl) ; get next character + inc hl + push hl + cp 0 + ret z ; end of text found + call cout ; output character + jp print + +; ------------------------------------------------------------------------- + +prhex: ; print hexadecimal digit in A + push af + srl a ; move high nibble to low + srl a + srl a + srl a + call hexnib ; convert to ASCII Hex + call cout ; send character to output device + pop af + call hexnib + call cout ; send character to output device + ret + + + +hexnib: + and 0fh ; strip high order nibble + add a,30H ; add ASCII ofset + cp 3ah ; correction necessary? + ret m + add a,7 ; correction for A to F + ret + +; ------------------------------------------------------------------------- + +cout: + ld e,a + ld c,02h ; Console output byte call + call 5 + ret + +; ------------------------------------------------------------------------- + +cin: + ld c,01h ; BDOS console function + call 5 + ret + +; ------------------------------------------------------------------------- + +crlf: + ld a,CR + call cout + ld a,LF + call cout + ret + +;------------------------------------------------------------------ +; Routines that talk with the IDE drive, these should be called by +; the main program. + + + ; read a sector, specified by the 4 bytes in "lba", + ; Return, acc is zero on success, non-zero for an error +read_sector: + call ide_wait_not_busy ;make sure drive is ready + call wr_lba ;tell it which sector we want + + ld a, ide_command + ld c, ide_cmd_read + call ide_write ; ask the drive to read it + + call ide_wait_drq ;wait until it's got the data + + bit 0,a + jp nz, get_err + ld hl, buffer + call read_data ;grab the data + ld a,0 + ret + + + ; when an error occurs, we get acc.0 set from a call to ide_drq + ; or ide_wait_not_busy (which read the drive's status register). If + ; that error bit is set, we should jump here to read the drive's + ; explanation of the error, to be returned to the user. If for + ; some reason the error code is zero (shouldn't happen), we'll + ; return 255, so that the main program can always depend on a + ; return of zero to indicate success. +get_err: + ld a,ide_err + call ide_read + ld a,c + jp z,gerr2 + ret +gerr2: + ld a, 255 + ret + + + ;write a sector, specified by the 4 bytes in "lba", + ;whatever is in the buffer gets written to the drive! + ;Return, acc is zero on success, non-zero for an error +write_sector: + call ide_wait_not_busy ; make sure drive is ready + call wr_lba ; tell it which sector we want + ld a, ide_command + ld c, ide_cmd_write + + call ide_write ;tell drive to write a sector + call ide_wait_drq ;wait unit it wants the data + bit 0,a ; check for error returned + jp nz,get_err + + ld hl, buffer + call write_data ;give the data to the drive + call ide_wait_not_busy ;wait until the write is complete + + bit 0,a + jp nz,get_err + + ld a,0 + ret + + + ; do the identify drive command, and return with the buffer + ; filled with info about the drive +drive_id: + call ide_wait_not_busy + ld a,ide_head + ld c,10100000b + call ide_write ;select the master device + call ide_wait_ready + ld a,ide_command + ld c,0ech + call ide_write ;issue the command + call ide_wait_drq + ld hl, buffer + call read_data + ret + + + ; tell the drive to spin up +spinup: + ld c,ide_cmd_spinup + ld a,ide_command + call ide_write + call ide_wait_not_busy + ret + + ; tell the drive to spin down +spindown: + call ide_wait_not_busy + ld c,ide_cmd_spindown + ld a,ide_command + call ide_write + call ide_wait_not_busy + ret + + ; initialize the IDE drive +ide_init: + ld a, ide_head + ld b, 0 + ld c, 10100000b ; select the master device + call ide_write +init1: + ld a, ide_status + call ide_read + ld a, c + + ; should probably check for a timeout here + bit 6,a ; wait for RDY bit to be set + jp z,init1 + bit 7,a + jp nz,init1 ; wait for BSY bit to be clear + + ret + + + +; IDE Status Register: +; bit 7: Busy 1=busy, 0=not busy +; bit 6: Ready 1=ready for command, 0=not ready yet +; bit 5: DF 1=fault occured inside drive +; bit 4: DSC 1=seek complete +; bit 3: DRQ 1=data request ready, 0=not ready to xfer yet +; bit 2: CORR 1=correctable error occured +; bit 1: IDX vendor specific +; bit 0: ERR 1=error occured + + + + + +;------------------------------------------------------------------ +; Not quite as low, low level I/O. These routines talk to the drive, +; using the low level I/O. Normally a main program should not call +; directly to these. + + + ;Read a block of 512 bytes (one sector) from the drive + ;and store it in memory @ HL +read_data: + ld b, 0 +rdblk2: + push bc + push hl + ld a, ide_data + call ide_read + pop hl + ld a, c + ld (hl), a + inc hl + ld a, b + ld (hl), a + inc hl + pop bc + djnz rdblk2 + ret + + + ; Write a block of 512 bytes (at HL) to the drive +write_data: + ld b,0 +wrblk2: + push bc + ld a,(hl) + ld c, a ; LSB + inc hl + ld a,(hl) + ld b, a ; MSB + inc hl + push hl + + ld a, ide_data + call ide_write + pop hl + pop bc + djnz wrblk2 + ret + + + + ; write the logical block address to the drive's registers +wr_lba: + ld a,(lba1+3) ; MSB + and 0fh + or 0e0h + ld c,a + ld a,ide_head + call ide_write + + ld a,(lba1+2) + ld c,a + ld a,ide_cyl_msb + call ide_write + + ld a,(lba1+1) + ld c,a + ld a,ide_cyl_lsb + call ide_write + + ld a,(lba1+0) ; LSB + ld c,a + ld a,ide_sector + call ide_write + + ld c,1 + ld a,ide_sec_cnt + call ide_write + + + ret + + +ide_wait_not_busy: + ld a,ide_status ;wait for RDY bit to be set + call ide_read + bit 7,c + jp nz,ide_wait_not_busy + ; should probably check for a timeout here + + ret + + +ide_wait_ready: + ld a,ide_status ; wait for RDY bit to be set + call ide_read + bit 6,c ; test for XXX + jp z,ide_wait_ready + bit 7,c + jp nz,ide_wait_ready + + ;should probably check for a timeout here + ret + + + + ; Wait for the drive to be ready to transfer data. + ; Returns the drive's status in Acc +ide_wait_drq: + ld a,ide_status ;wait for DRQ bit to be set + call ide_read + bit 7,c + jp nz,ide_wait_drq ; check for busy + bit 3,c ; wait for DRQ + jp z,ide_wait_drq + + ; should probably check for a timeout here + + ret + + + +;----------------------------------------------------------------------------- +; Low Level I/O to the drive. These are the routines that talk +; directly to the drive, via the 8255 chip. Normally a main +; program would not call to these. + + ; Do a read bus cycle to the drive, using the 8255. + ; input acc = IDE register address + ; output C = lower byte read from IDE drive + ; output B = upper byte read from IDE drive + + + + +ide_read: + push af ; save register value + push bc + call set_ppi_rd ; setup for a read cycle + pop bc + + pop af ; restore register value + call wrppictl ; write to control sigs + + or ide_rd_line ; assert RD pin + call wrppictl ; write to control sigs + + push af ; save register value + call rdppilsb ; read LSB register into A + ld c,a ; save in reg C + + call rdppimsb ; read MSB register into A + ld b,a ; save in reg C + + + pop af ; restore register value + xor ide_rd_line ; de-assert RD signal + call wrppictl ; write to control sigs + + ld a,0 + call wrppictl ; write to control sigs + ret + + + + ; Do a write bus cycle to the drive, via the 8255 + ; input acc = IDE register address + ; input register C = LSB to write + ; input register B = MSB to write + ; + +ide_write: + push af ; save IDE register value + + push bc + call set_ppi_wr ; setup for a write cycle + pop bc + + ld a,c ; get value to be written + call wrppilsb + + ld a,b ; get value to be written + call wrppimsb + + pop af ; get saved IDE register + call wrppictl ; write to control sigs + + or ide_wr_line ; assert write pin + call wrppictl ; write to control sigs + + xor ide_wr_line ; de assert WR pin + call wrppictl ; write to control sigs + + ld a,0 + call wrppictl ; write to control sigs + ret + + +;------------------------------------------------------------------------------------------- + +ide_hard_reset: + call set_ppi_rd + ld a,ide_rst_line + call wrppictl ; write to control register + ld bc,0 +rstdly: + djnz rstdly + ld a,0 + call wrppictl ; write to control registers + ret + +;----------------------------------------------------------------------------------- +; PPI setup routine to configure the appropriate PPI mode +; +;------------------------------------------------------------------------------------ + +set_ppi_rd: + ld a,(ppibase) + add a,PIOCONT ; select Control register + ld c,a + ld a,rd_ide_8255 ; configure 8255 chip, read mode + out (c),a + ret + +set_ppi_wr: + ld a,(ppibase) + add a,PIOCONT ; select Control register + ld c,a + ld a,wr_ide_8255 ; configure 8255 chip, write mode + out (c),a + ret + +;------------------------------------------------------------------------------------ + +rdppilsb: ; read LSB + ; returns data in A + push bc + ld a,(ppibase) + add a,IDELSB ; select Control register + ld c,a + in a,(c) + pop bc + ret + + +wrppilsb: ; write LSB + ; data to be written in A + push bc + push af + ld a,(ppibase) + add a,IDELSB ; select Control register + ld c,a + pop af + out (c),a + pop bc + ret + +;-------------------------------------------------------------------------- + +rdppimsb: ; read MSB + ; returns data in A + push bc + ld a,(ppibase) + add a,IDEMSB ; select MSB Register + ld c,a + in a,(c) + pop bc + ret + + +wrppimsb: ; write LSB + ; data to be written in A + push bc + push af + ld a,(ppibase) + add a,IDEMSB ; select MSB Register + ld c,a + pop af + out (c),a + pop bc + ret + +;-------------------------------------------------------------------------- + +wrppictl: ; write to control signals + ; data to be written in A + push bc + push af + ld a,(ppibase) + add a,IDECTL ; select CTL Register + ld c,a + pop af + out (c),a + pop bc + ret + +;-------------------------------------------------------------------------- +; Storage area follows + +savsp: .dw 0 ; saved stack pointer +lba1: .dw 0,0 ; LBA used for read/write operations +lba2: .dw 0,0 ; Start LBA for format +lba3: .dw 0,0 ; End LBA for format +ppibase: .db DEFBASE ; base address of PPI chip + + .fill 0C00H - $ + +buffer: .fill 512 ; sector buffer for IDE transfers +conbuf: .db 8 ; maximum chars + .db 0 ; count + .fill 8 ; size of buffer + + .fill 100 +stack: + + .end + diff --git a/Source/Apps/rtcds7.asm b/Source/Apps/rtcds7.asm new file mode 100644 index 00000000..a2ac01e5 --- /dev/null +++ b/Source/Apps/rtcds7.asm @@ -0,0 +1,703 @@ +;================================================================================================== +; PCF8584 I2C Clock Driver +;================================================================================================== +; +PCF_BASE .EQU 0F0H +PCF_ID .EQU 0AAH +CPU_CLK .EQU 12 + +REGS0 .EQU PCF_BASE +REGS1 .EQU REGS0+1 +PCF_OWN .EQU (PCF_ID >> 1) ; PCF'S ADDRESS IN SLAVE MODE +; +;T4LC512D .EQU 10100000B ; DEVICE IDENTIFIER +;T4LC512A1 .EQU 00000000B ; DEVICE ADDRESS +;T4LC512A2 .EQU 00001110B ; DEVICE ADDRESS +;T4LC512A3 .EQU 00000010B ; DEVICE ADDRESS +;T4LC512W .EQU 00000000B ; DEVICE WRITE +;T4LC512R .EQU 00000001B ; DEVICE READ +; +;I2CDEV1W .EQU (T4LC512D+T4LC512A1+T4LC512W) +;I2CDEV1R .EQU (T4LC512D+T4LC512A1+T4LC512R) +; +;I2CDEV2W .EQU (T4LC512D+T4LC512A2+T4LC512W) +;I2CDEV2R .EQU (T4LC512D+T4LC512A2+T4LC512R) +; +;I2CDEV3W .EQU (T4LC512D+T4LC512A3+T4LC512W) +;I2CDEV3R .EQU (T4LC512D+T4LC512A3+T4LC512R) +; +; CONTROL REGISTER BITS +; +PCF_PIN .EQU 10000000B +PCF_ES0 .EQU 01000000B +PCF_ES1 .EQU 00100000B +PCF_ES2 .EQU 00010000B +PCF_EN1 .EQU 00001000B +PCF_STA .EQU 00000100B +PCF_STO .EQU 00000010B +PCF_ACK .EQU 00000001B +; +PCF_START_ .EQU (PCF_PIN | PCF_ES0 | PCF_STA | PCF_ACK) +PCF_STOP_ .EQU (PCF_PIN | PCF_ES0 | PCF_STO | PCF_ACK) +PCF_REPSTART_ .EQU ( PCF_ES0 | PCF_STA | PCF_ACK) +PCF_IDLE_ .EQU (PCF_PIN | PCF_ES0 | PCF_ACK) +; +; STATUS REGISTER BITS +; +;PCF_PIN .EQU 10000000B +PCF_INI .EQU 01000000B ; 1 if not initialized +PCF_STS .EQU 00100000B +PCF_BER .EQU 00010000B +PCF_AD0 .EQU 00001000B +PCF_LRB .EQU 00001000B +PCF_AAS .EQU 00000100B +PCF_LAB .EQU 00000010B +PCF_BB .EQU 00000001B +; +; CLOCK CHIP FREQUENCIES +; +PCF_CLK3 .EQU 000H +PCF_CLK443 .EQU 010H +PCF_CLK6 .EQU 014H +PCF_CLK8 .EQU 018H +PCF_CLK12 .EQU 01cH +; +; TRANSMISSION FREQUENCIES +; +PCF_TRNS90 .EQU 000H ; 90 kHz */ +PCF_TRNS45 .EQU 001H ; 45 kHz */ +PCF_TRNS11 .EQU 002H ; 11 kHz */ +PCF_TRNS15 .EQU 003H ; 1.5 kHz */ +; +; TIMEOUT AND DELAY VALUES (ARBITRARY) +; +PCF_PINTO .EQU 65000 +PCF_ACKTO .EQU 65000 +PCF_BBTO .EQU 65000 +PCF_LABDLY .EQU 65000 +; +; DATA PORT REGISTERS +; +#IF (CPU_CLK = 443) +PCF_CLK .EQU PCF_CLK443 +#ELSE + #IF (CPU_CLK = 8) +PCF_CLK .EQU PCF_CLK8 + #ELSE + #IF (CPU_CLK = 12) +PCF_CLK .EQU PCF_CLK12 + #ELSE ***ERROR + #ENDIF + #ENDIF +#ENDIF +; +DS7_OUT .EQU 10000000B ; SELECT SQUARE WAVE FUNCTION +DS7_SQWE .EQU 00010000B ; ENABLE SQUARE WAVE OUTPUT +DS7_RATE .EQU 00000000B ; SET 1HZ OUPUT +; +DS7_DS1307 .EQU 11010000B ; DEVICE IDENTIFIER +DS7_W .EQU 00000000B ; DEVICE WRITE +DS7_R .EQU 00000001B ; DEVICE READ +; +DS7_READ .EQU (DS7_DS1307 | DS7_R) ; READ +DS7_WRITE .EQU (DS7_DS1307 | DS7_W) ; WRITE +; +DS7_CTL .EQU (DS7_OUT | DS7_SQWE | DS7_RATE) +; + .ORG 100H +; +; + CALL DS7_RDC ; READ CLOCK DATA INTO BUFFER + CALL DS7_DISP ; DISPLAY TIME AND DATE FROM BUFFER + RET +; +;----------------------------------------------------------------------------- +; RTC READ +; +; 1. ISSUE SLAVE ADDRESS WITH START CONDITION AND WRITE STATUS +; 2. OUTPUT THE ADDRESS TO ACCESS. (00H = START OF DS1307 REGISTERS) +; 3. OUTPUT REPEAT START TO TRANSITION TO READ PROCESS +; 4. ISSUE SLAVE ADDRESS WITH READ STATUS +; 5. DO A DUMMY READ +; 6. READ 8 BYTES STARTING AT ADDRESS PREVIOUSLY SET +; 7. END READ WITH NON-ACKNOWLEDGE +; 8. ISSUE STOP AND RELEASE BUS +; +DS7_RDC:LD A,DS7_WRITE ; SET SLAVE ADDRESS + OUT (REGS0),A +; + CALL PCF_WAIT_FOR_BB + JP NZ,PCF_BBERR +; + CALL PCF_START ; GENERATE START CONDITION + CALL PCF_WAIT_FOR_PIN; AND ISSUE THE SLAVE ADDRESS + CALL NZ,PCF_PINERR +; + LD A,0 + OUT (REGS0),A ; PUT ADDRESS MSB ON BUS + CALL PCF_WAIT_FOR_PIN + CALL NZ,PCF_PINERR +; + CALL PCF_REPSTART ; REPEAT START +; + LD A,DS7_READ ; ISSUE CONTROL BYTE + READ + OUT (REGS0),A +; + CALL PCF_READI2C ; DUMMY READ +; + LD HL,DS7_BUF ; READ 8 BYTES INTO BUFFER + LD B,8 +DS7_RL1:CALL PCF_READI2C + LD (HL),A + INC HL + DJNZ DS7_RL1 +; +#IF (0) + LD A,8 + LD DE,DS7_BUF ; DISLAY DATA READ + CALL PRTHEXBUF ; + CALL NEWLINE +#ENDIF +; + LD A,PCF_ES0 ; END WITH NOT-ACKNOWLEDGE + OUT (REGS1),A ; AND RELEASE BUS + NOP + IN A,(REGS0) + NOP +DS7_WTPIN: + IN A,(REGS1) ; READ S1 REGISTER + BIT 7,A ; CHECK PIN STATUS + JP NZ,DS7_WTPIN + CALL PCF_STOP +; + IN A,(REGS0) + RET + +; +;----------------------------------------------------------------------------- +; DISPLAY CLOCK INFORMATION FROM DATA STORED IN BUFFER +; +DS7_DISP: + LD HL,DS7_CLKTBL +DS7_CLP:LD C,(HL) + INC HL + LD D,(HL) + CALL DS7_BCD + INC HL + LD A,(HL) + OR A + RET Z + CALL COUT + INC HL + JR DS7_CLP + RET +; +DS7_CLKTBL: + .DB 04H, 00111111B, '/' + .DB 05H, 00011111B, '/' + .DB 06H, 11111111B, ' ' + .DB 02H, 00011111B, ':' + .DB 01H, 01111111B, ':' + .DB 00H, 01111111B, 00H +; +DS7_BCD:PUSH HL + LD HL,DS7_BUF ; READ VALUE FROM + LD B,0 ; BUFFER, INDEXED BY A + ADD HL,BC + LD A,(HL) + AND D ; MASK OFF UNNEEDED + SRL A + SRL A + SRL A + SRL A + ADD A,30H + CALL COUT + LD A,(HL) + AND 00001111B + ADD A,30H + CALL COUT + POP HL + RET +; +DS7_BUF: .FILL 8,0 ; BUFFER FOR TIME, DATE AND CONTROL + +;----------------------------------------------------------------------------- +PCF_START: + LD A,PCF_START_ + OUT (REGS1),A + RET +; +;----------------------------------------------------------------------------- +PCF_REPSTART: + LD A,PCF_REPSTART_ + OUT (REGS1),A + RET +; +;----------------------------------------------------------------------------- +PCF_STOP: + LD A,PCF_STOP_ + OUT (REGS1),A + RET +; +;----------------------------------------------------------------------------- +;; +PCF_INIT: + LD A,PCF_PIN ; S1=80H: S0 SELECTED, SERIAL + OUT (REGS1),A ; INTERFACE OFF + NOP + IN A,(REGS1) ; CHECK TO SEE S1 NOW USED AS R/W + AND 07FH ; CTRL. PCF8584 DOES THAT WHEN ESO + JP NZ,PCF_INIERR ; IS ZERO +; + LD A,PCF_OWN ; LOAD OWN ADDRESS IN S0, + OUT (REGS0),A ; EFFECTIVE ADDRESS IS (OWN <<1) + NOP + IN A,(REGS0) ; CHECK IT IS REALLY WRITTEN + CP PCF_OWN + JP NZ,PCF_SETERR +; + LD A,+(PCF_PIN | PCF_ES1) ; S1=0A0H + OUT (REGS1),A ; NEXT BYTE IN S2 + NOP + IN A,(REGS1) + AND 07FH + CP PCF_ES1 + JP NZ,PCF_REGERR +; + LD A,PCF_CLK ; LOAD CLOCK REGISTER S2 + OUT (REGS0),A + NOP + IN A,(REGS0) ; CHECK IT'S REALLY WRITTEN, ONLY + AND 1FH ; THE LOWER 5 BITS MATTER + CP PCF_CLK + JP NZ,PCF_CLKERR +; + LD A,PCF_IDLE_ + OUT (REGS1),A + NOP + IN A,(REGS1) + CP +(PCF_PIN | PCF_BB) + JP NZ,PCF_IDLERR +; + RET +; +;----------------------------------------------------------------------------- +PCF_HANDLE_LAB: +; + LD A,PCF_PIN + OUT (REGS1),A + LD A,PCF_ES0 + OUT (REGS1),A +; + LD HL,PCF_LABDLY +PCF_LABLP: + LD A,H + OR L + DEC HL + JR NZ,PCF_LABLP +; + IN A,(REGS1) + RET +; +;----------------------------------------------------------------------------- +; +; RETURN A=00/Z IF SUCCESSFULL +; RETURN A=FF/NZ IF TIMEOUT +; RETURN A=01/NZ IF LOST ARBITRATION +; PCF_STATUS HOLDS LAST PCF STATUS +; +PCF_WAIT_FOR_PIN: + PUSH HL + LD HL,PCF_PINTO ; SET TIMEOUT VALUE + +PCF_WFP0: + IN A,(REGS1) ; GET BUS + LD (PCF_STATUS),A ; STATUS + LD B,A + + DEC HL ; HAVE WE + LD A,H ; TIMED OUT + OR L + JR Z,PCF_WFP1 ; YES WE HAVE, GO ACTION IT + + LD A,B ; + AND PCF_PIN ; IS TRANSMISSION COMPLETE? + JR NZ,PCF_WFP0 ; KEEP ASKING IF NOT OR + POP HL ; YES COMPLETE (PIN=0) RETURN WITH ZERO + RET +PCF_WFP1: + LD A,B ; DID WE LOSE ARBITRATION? + AND PCF_LAB ; IF A=0 THEN NO + CPL + JR NZ,PCF_WFP2 ; NO + CALL PCF_HANDLE_LAB ; YES GO HANDLE IT + LD (PCF_STATUS),A + XOR A ; RETURN NZ, A=01H + INC A +PCF_WFP2: + POP HL ; RET NZ, A=FF IF TIMEOUT + RET +; +PCF_STATUS .DB 00H + +;-------------------------------------------------------------------------------- +; +; RETURN NZ/FF IF TIMEOUT ERROR +; RETURN NZ/01 IF FAILED TO RECEIVE ACKNOWLEDGE +; RETURN Z/00 IF RECEIVED ACKNOWLEDGE +; +PCF_WAIT_FOR_ACK: + PUSH HL + LD HL,PCF_ACKTO +; +PCF_WFA0: + IN A,(REGS1) ; READ PIN + LD (PCF_STATUS),A ; STATUS + LD B,A +; + DEC HL ; SEE IF WE HAVE TIMED + LD A,H ; OUT WAITING FOR PIN + OR L ; EXIT IF + JR Z,PCF_WFA1 ; WE HAVE +; + LD A,B ; OTHERWISE KEEP LOOPING + AND PCF_PIN ; UNTIL WE GET PIN + JR NZ,PCF_WFA0 ; OR TIMEOUT +; + LD A,B ; WE GOT PIN SO NOW + AND PCF_LRB ; CHECK WE HAVE + LD A,1 + JR Z,PCF_WFA2 ; RECEIVED ACKNOWLEDGE + XOR A + JR PCF_WFA2 +PCF_WFA1: + CPL ; TIMOUT ERROR +PCF_WFA2: + POP HL ; EXIT WITH NZ = FF + RET +; +;-------------------------------------------------------------------------------- +; +; HL POINTS TO DATA +; DE = COUNT +; A = 0 LAST A=1 NOT LAST +; +; +;PCF_READBYTES: ; NOT FUNCTIONAL YET + + LD (PCF_LBF),A ; SAVE LAST BYTE FLAG +; + INC DE ; INCREMENT NUMBER OF BYTES TO READ BY ONE -- DUMMY READ BYTE + LD BC,0 ; SET BYTE COUNTER +; +PCF_RBL:PUSH BC + CALL PCF_WAIT_FOR_PIN ; DO WE HAVE THE BUS? + POP BC + JR Z,PCF_RB1 ; YES + CP 01H + JR Z,PCF_RB3 ; NO - LOST ARBITRATION + JR PCF_RB2 ; NO - TIMEOUT +; +PCF_RB1: + LD A,(PCF_STATUS) + AND PCF_LRB + + + ; IS THIS THE SECOND TO LAST BYTE TO GO? + + PUSH DE ; SAVE COUNT + DEC DE ; COUNT (DE) = NUMBER OF BYTES TO READ LESS 1 + EX DE,HL ; SAVE POINTER, PUT COUNT IN DE + XOR A ; CLEAR CARRY FLAG + SBC HL,BC ; DOES BYTE COUNTER = HL (NUMBER OF BYTES TO READ LESS 1) + EX DE,HL ; RESTORE POINTER + POP DE ; RESTORE COUNT + + ; Z = YES IT IS + ; NZ = NO IT ISN'T + JR NZ,PCF_RB4 +; +PCF_RB4:LD A,B ; IF FIRST READ DO A DUMMY + OR C ; READ OTHERWISE READ AND SAVE + JR NZ,PCF_RB5 + + IN A,(REGS0) ; DUMMY READ + JR PCF_RB6 + +PCF_RB5:IN A,(REGS0) ; READ AND SAVE + LD (HL),A +; +PCF_RB6: ; HAVE WE DONE ALL? + + PUSH DE ; SAVE COUNT + EX DE,HL ; SAVE POINTER, PUT COUNT IN DE + XOR A ; CLEAR CARRY FLAG + SBC HL,BC ; DOES BYTE COUNTER = HL (NUMBER OF BYTES TO READ) + EX DE,HL ; RESTORE POINTER + POP DE ; RESTORE COUNT +; + INC HL ; BUFFER POINTER + INC BC ; COUNT +; + JR NZ,PCF_RBL ; REPEAT UNTIL COUNTS MATCH + RET +; +PCF_RB2: ; TIMEOUT + CALL PCF_STOP + CALL PCF_TOERR + RET +; +PCF_RB3: ; LOST ARBITRATION + CALL PCF_ARBERR + RET +; +PCF_LBF: + .DB 0 ; LAST BYTE FLAG +; +;----------------------------------------------------------------------------- +; READ ONE BYTE FROM I2C +; RETURNS DATA IN A +; Z FLAG SET IS ACKNOWLEDGE RECEIVED (CORRECT OPERATION) +; +PCF_READI2C: + IN A,(REGS1) ; READ S1 REGISTER + BIT 7,A ; CHECK PIN STATUS + JP NZ,PCF_READI2C + BIT 3,A ; CHECK LRB=0 + JP NZ,PCF_RDERR + IN A,(REGS0) ; GET DATA + RET +;----------------------------------------------------------------------------- +; +; POLL THE BUS BUSY BIT TO DETERMINE IF BUS IS FREE. +; RETURN WITH A=00H/Z STATUS IF BUS IS FREE +; RETURN WITH A=FFH/NZ STATUS IF BUS +; +; AFTER RESET THE BUS BUSY BIT WILL BE SET TO 1 I.E. NOT BUSY +; +PCF_WAIT_FOR_BB: + LD HL,PCF_BBTO +PCF_WFBB0: + IN A,(REGS1) + AND PCF_BB + RET Z ; BUS IS FREE RETURN ZERO + DEC HL + LD A,H + OR L + JR NZ,PCF_WFBB0 ; REPEAT IF NOT TIMED OUT + CPL ; RET NZ IF TIMEOUT + RET +; +;----------------------------------------------------------------------------- +; DISPLAY ERROR MESSAGES +; +PCF_RDERR: + PUSH HL + LD HL,PCF_RDFAIL + JR PCF_PRTERR +; +PCF_INIERR: + PUSH HL + LD HL,PCF_NOPCF + JR PCF_PRTERR +; +PCF_SETERR: + PUSH HL + LD HL,PCF_WRTFAIL + JR PCF_PRTERR +; +PCF_REGERR: + PUSH HL + LD HL,PCF_REGFAIL + JR PCF_PRTERR +; +PCF_CLKERR: + PUSH HL + LD HL,PCF_CLKFAIL + JR PCF_PRTERR +; +PCF_IDLERR: + PUSH HL + LD HL,PCF_IDLFAIL + JR PCF_PRTERR +; +PCF_ACKERR: + PUSH HL + LD HL,PCF_ACKFAIL + JR PCF_PRTERR +; +PCF_RDBERR: + PUSH HL + LD HL,PCF_RDBFAIL + JR PCF_PRTERR +; +PCF_TOERR: + PUSH HL + LD HL,PCF_TOFAIL + JR PCF_PRTERR +; +PCF_ARBERR: + PUSH HL + LD HL,PCF_ARBFAIL + JR PCF_PRTERR +; +PCF_PINERR: + PUSH HL + LD HL,PCF_PINFAIL + JR PCF_PRTERR +; +PCF_BBERR: + PUSH HL + LD HL,PCF_BBFAIL + JR PCF_PRTERR +; +PCF_PRTERR: + CALL PRTSTR + CALL NEWLINE + POP HL + RET +; +PCF_NOPCF .DB "NO DEVICE FOUND$" +PCF_WRTFAIL .DB "SETTING DEVICE ID FAILED$" +PCF_REGFAIL .DB "CLOCK REGISTER SELECT ERROR$" +PCF_CLKFAIL .DB "CLOCK SET FAIL$" +PCF_IDLFAIL .DB "BUS IDLE FAILED$" +PCF_ACKFAIL .DB "FAILED TO RECEIVE ACKNOWLEDGE$" +PCF_RDFAIL .DB "READ FAILED$" +PCF_RDBFAIL .DB "READBYTES FAILED$" +PCF_TOFAIL .DB "TIMEOUT ERROR$" +PCF_ARBFAIL .DB "LOST ARBITRATION$" +PCF_PINFAIL .DB "PIN FAIL$" +PCF_BBFAIL .DB "BUS BUSY$" +; +;----------------------------------------------------------------------------- +; +BDOS .EQU 5 ;ENTRY BDOS +BS .EQU 8 ;BACKSPACE +TAB .EQU 9 ;TABULATOR +LF .EQU 0AH ;LINE-FEED +CR .EQU 0DH ;CARRIAGE-RETURN +; +; OUTPUT TEXT AT HL +; +PRTSTR: LD A,(HL) + OR A + RET Z + CALL PRINP + INC HL + JR PRTSTR +; +;Output WORD +;*********** +; +;PARAMETER: Entry WORD IN HL +;********* +; +OUTW: LD A,H + CALL OUTB + LD A,L + CALL OUTB + RET +; +;Output BYTE +;*********** +; +;PARAMETER: Entry BYTE IN A +;********* +; +OUTB: PUSH AF + RRCA + RRCA + RRCA + RRCA + AND 0FH + CALL HBTHE ;Change Half-BYTE + POP AF + AND 0FH + CALL HBTHE + RET +; +;Output HALF-BYTE +;**************** +; +;PARAMETER: Entry Half-BYTE IN A (BIT 0 - 3) +;********* +; +HBTHE: CP 0AH + JR C,HBTHE1 + ADD A,7 ;Character to Letter +HBTHE1: ADD A,30H + LD E,A + CALL PCHAR + RET +; +; +;Output on Screen +;**************** +; +PRBS: LD E,BS + CALL PCHAR + RET +; +;Output CR+LF on Screen +;********************** +; +NEWLINE: +CRLF: LD E,CR + CALL PCHAR + LD E,LF + CALL PCHAR + RET +; +;Output ASCII-Character +;********************** +; +COUT: +PRINP: PUSH AF + PUSH DE + LD E,A + CALL PCHAR + POP DE + POP AF + RET +; +;CALL BDOS with Register Save +;**************************** +; +INCHA: LD C,1 ;INPUT CHARACTER TO A + JR BDO +PCHAR: LD C,2 ;PRINT CHARACTER IN E + JR BDO +PSTRIN: LD C,9 ;PRINT STRING + JR BDO +INBUFF: LD C,10 ;READ CONSOLE-BUFFER + JR BDO +CSTS: LD C,11 ;CONSOLE-STATUS + JR BDO +OPEN: LD C,15 ;OPEN FILE + JR BDO +CLOSE: LD C,16 ;CLOSE FILE + JR BDO +DELETE: LD C,19 ;DELETE FILE + JR BDO +READS: LD C,20 ;READ SEEK + JR BDO +WRITES: LD C,21 ;WRITE SEEK + JR BDO +MAKE: LD C,22 ;MAKE FILE + JR BDO +SETDMA: LD C,26 ;SET DMA-ADDRESS +BDO: PUSH HL + PUSH DE + PUSH BC + PUSH IX + PUSH IY + CALL BDOS + POP IY + POP IX + POP BC + POP DE + POP HL + RET +; + .END diff --git a/Source/Apps/tstdskng.asm b/Source/Apps/tstdskng.asm new file mode 100644 index 00000000..d1abd87e --- /dev/null +++ b/Source/Apps/tstdskng.asm @@ -0,0 +1,1016 @@ +; +;================================================================================================== +; DSKY NEXT GENERATION TEST APPLICATION +;================================================================================================== +; +; TO BUILD: +; +; TASM -t80 -g3 -fFF TSTDSKNG.ASM TSTDSKNG.COM TSTDSKNG.LST +; +; PIO 82C55 I/O IS DECODED TO PORT $60-$67 (ADJUST BELOW AS NEEDED) +; ASSUMES UART AT PORT $68 (ADJUST BELOW AS NEEDED) +; +; THIS CODE IS BELIEVED TO BE COMPATIBLE WITH PPIDE OR PPISD +; RUNNING ON SAME PPI BUS. +; +FALSE: .EQU 0 +TRUE: .EQU !FALSE +; +DSKY_OSC: .EQU 2000000 ; OSCILLATOR FREQ IN HZ +; +BDOS: .EQU FALSE ; BDOS OR DIRECT TO 8250ISH +; +UART_BASE: .EQU $68 ; UART BASE IO ADDRESS +PPI_BASE: .EQU $60 ; PPI BASE IO PORT +; +; LED SEGMENTS (BIT VALUES) +; +; +--01--+ +; 20 02 +; +--40--+ +; 10 04 +; +--08--+ 80 +; +; KEY CODE MAP (KEY CODES) --CCCRRR +; +; 00 08 10 18 +; 01 09 11 19 +; 02 0A 12 1A +; 03 0B 13 1B +; 04 0C 14 1C +; 05 0D 15 1D +; +; LED BIT MAP (BIT VALUES) +; +; $08 $09 $0A $0B +; --- --- --- --- +; 01 01 01 01 +; 02 02 02 02 +; 04 04 04 04 +; 08 08 08 08 +; 10 10 10 10 +; 20 20 20 20 +; +PPIA: .EQU PPI_BASE + 0 ; PORT A +PPIB: .EQU PPI_BASE + 1 ; PORT B +PPIC: .EQU PPI_BASE + 2 ; PORT C +PPIX: .EQU PPI_BASE + 3 ; PIO CONTROL PORT +; +DSKY_PPIX_RD: .EQU %10010010 ; PPIX VALUE FOR READS +DSKY_PPIX_WR: .EQU %10000010 ; PPIX VALUE FOR WRITES +; +; PIO CHANNEL C: +; +; 7 6 5 4 3 2 1 0 +; RES /RD /WR CS CS 0 0 A0 +; +; SETTING BITS 3 & 4 WILL ASSERT /CS ON 3279 +; CLEAR BITS 5 OR 6 TO ASSERT READ/WRITE +; +DSKY_PPI_IDLE: .EQU %01100000 +; +DSKY_CMD_CLR: .EQU %11011111 ; CLEAR (ALL OFF) +DSKY_CMD_CLRX: .EQU %11010011 ; CLEAR (ALL ON) +DSKY_CMD_WDSP: .EQU %10010000 ; WRITE DISPLAY RAM +DSKY_CMD_RDSP: .EQU %01110000 ; READ DISPLAY RAM +DSKY_CMD_CLK: .EQU %00100000 ; SET CLK PRESCALE +DSKY_CMD_FIFO: .EQU %01000000 ; READ FIFO +; +DSKY_PRESCL: .EQU DSKY_OSC / 100000 ; PRESCALER +; + .ORG $100 +; + ; SAVE PREVIOUS STACK POINTER, AND SWITCH TO OUR STACK + LD (STACKSAV),SP + LD SP,STACK +; + CALL PRTSTRD + .DB "\r\nNextGenDSKY Test Program, v1.2, 2021-06-26$" + CALL PRTSTRD + .DB "\r\nPPI port 0x$" + LD A,PPI_BASE + CALL PRTHEXBYTE + CALL NEWLINE +; + CALL DSKY_INIT + CALL DSKY_READ +; + CALL PRTSTRD + .DB "\r\nCLEAR Command (all ON)$" + LD A,DSKY_CMD_CLRX + CALL DSKY_CMD + CALL WAITKEY + CALL DSKY_READ +; + CALL PRTSTRD + .DB "\r\nCLEAR Command (all OFF)$" + LD A,DSKY_CMD_CLR + CALL DSKY_CMD + CALL WAITKEY + CALL DSKY_READ +; + CALL PRTSTRD + .DB "\r\nIndividual segments and LEDs$" + LD HL,PAT1 + LD B,PAT1LN + LD C,0 + CALL DSKY_PUTSTR + CALL WAITKEY + CALL DSKY_READ +; + CALL PRTSTRD + .DB "\r\nIncrementing segments and LEDs$" + LD HL,PAT2 + LD B,PAT2LN + LD C,0 + CALL DSKY_PUTSTR + CALL WAITKEY + CALL DSKY_READ +; + CALL PRTSTRD + .DB "\r\nOmit individual segments and LEDs$" + LD HL,PAT3 + LD B,PAT3LN + LD C,0 + CALL DSKY_PUTSTR + CALL WAITKEY + CALL DSKY_READ +; + ; DISPLAY HEX DIGITS 0-7 +; + CALL PRTSTRD + .DB "\r\nHex digits 0-7$" + LD HL,HEX1 + LD B,HEX1LN + LD C,0 + CALL DSKY_PUTENCSTR + CALL WAITKEY + CALL DSKY_READ +; + CALL PRTSTRD + .DB "\r\nHex digits 8-F$" + LD HL,HEX2 + LD B,HEX2LN + LD C,0 + CALL DSKY_PUTENCSTR + CALL WAITKEY + CALL DSKY_READ +; + CALL DSKY_BLANK +; + ; WAIT FOR KEY THEN DISPLAY FIFO CONTENTS + CALL PRTSTRD + .DB "\r\nPress keys on pad (console key to end)...$" +; + ; CLEAR BUFFER + LD HL,DSPBUF + LD A,$10 + LD B,8 +M1: + LD (HL),A + INC HL + DJNZ M1 +; + ; DISPLAY INIITAL BUFFER + LD B,8 + LD C,0 + LD HL,DSPBUF + CALL DSKY_PUTENCSTR +; +M2: + CALL CST ; CONSOLE STATUS + JR NZ,M4 ; ABORT IF KEY PRESSED + CALL DSKY_STAT + AND $3F ; DUMP 2 HIGH BITS + JR Z,M2 ; LOOP IF STATUS ZERO + CALL PRTSTRD + .DB "\r\nFIFO status=$" + CALL PRTHEXBYTE + AND $0F ; ISOLATE THE CUR FIFO LEN + JR Z,M2 ; LOOP IF NOTHING THERE + PUSH AF + LD A,DSKY_CMD_FIFO + CALL DSKY_CMD + POP BC ; B := CUR FIFO LEN + CALL PRTSTRD + .DB ", key code(s)=$" + +M3: + PUSH BC + CALL DSKY_DIN + CALL PRTHEXBYTE + CALL PC_SPACE + ; SHIFT BUFFER + LD HL,DSPBUF+5 + LD DE,DSPBUF+7 + LD BC,6 + LDDR + ; PUT NEW VALUE AT START + PUSH AF + RRCA + RRCA + RRCA + RRCA + AND $0F + LD (DSPBUF),A + POP AF + PUSH AF + AND $0F + LD (DSPBUF+1),A + ; UPDATE THE DISPLAY + LD B,8 + LD C,0 + LD HL,DSPBUF + CALL DSKY_PUTENCSTR + POP AF + ; TOGGLE LED, KEY CODE: --CCCRRR + PUSH AF + AND $07 ; ISOLATE ROW + LD B,A ; SAVE IN B + POP AF + RRCA + RRCA + RRCA + AND $07 ; ISOLATE COLUMN + LD C,A ; SAVE IN C + CALL DSKY_TOGLED ; TOGGLE LED AT ROW/COL + POP BC ; INSIDE LOOP COUNTER + DJNZ M3 + JP M2 ; LOOP +M4: + CALL CIN ; DUMP PENDING CONSOLE KEY +; + ; DANCING LIGHTS + CALL PRTSTRD + .DB "\r\nDance, Baby, Dance (console key to end)...$" +; + LD E,$01 ; STARTING VALUE +M5: + CALL CST ; CONSOLE STATUS + JR NZ,M8 ; ABORT IF KEY PRESSED + LD B,12 ; NUMBER OF BYTES + LD C,$00 ; STARTING LOCATION (BYTE) +M6: + LD A,E + CALL DSKY_PUTBYTE + INC C ; NEXT LOCATION + DJNZ M6 ; INNER LOOP FOR ALL BYTES + RLC E ; ROTATE THE VALUE + LD B,0 ; DELAY LOOP +M7: + CALL DLY64 + DJNZ M7 + JR M5 ; REPEAT OUTER LOOP +M8: + CALL CIN ; DUMP PENDING CONSOLE KEY +; + ; CLEAR ALL + LD A,DSKY_CMD_CLR + CALL DSKY_CMD +; +EXIT: + ; GOODBYE + CALL PRTSTRD + .DB "\r\nThank you, please call again\r\n$" +; + ; CLEAN UP AND RETURN TO OS + LD SP,(STACKSAV) +; + RET +; +; SETUP PPI FOR WRITING: PUT PPI PORT A IN OUTPUT MODE +; AVOID REWRTING PPIX IF ALREADY IN OUTPUT MODE +; +DSKY_PPIWR: + PUSH AF +; + ; CHECK FOR WRITE MODE + LD A,(DSKY_PPIX_VAL) + CP DSKY_PPIX_WR + JR Z,DSKY_PPIWR1 +; + ; SET PPI TO WRITE MODE + LD A,DSKY_PPIX_WR + OUT (PPIX),A + LD (DSKY_PPIX_VAL),A +; + ; RESTORE PORT C (MAY NOT BE NEEDED) + LD A,DSKY_PPI_IDLE + OUT (PPIC),A +; +; ; DIAGNOSTIC +; LD A,'W' +; CALL COUT +; +DSKY_PPIWR1: +; + POP AF + RET +; +; SETUP PPI FOR READING: PUT PPI PORT A IN INPUT MODE +; AVOID REWRTING PPIX IF ALREADY IN INPUT MODE +; +DSKY_PPIRD: + PUSH AF +; + ; CHECK FOR READ MODE + LD A,(DSKY_PPIX_VAL) + CP DSKY_PPIX_RD + JR Z,DSKY_PPIRD1 +; + ; SET PPI TO READ MODE + LD A,DSKY_PPIX_RD + OUT (PPIX),A + LD (DSKY_PPIX_VAL),A +; +; ; DIAGNOSTIC +; LD A,'R' +; CALL COUT +; +DSKY_PPIRD1: + POP AF + RET +; +; RELEASE USE OF PPI +; +DSKY_PPIIDLE: + JR DSKY_PPIRD ; SAME AS READ MODE +; +; +; +DSKY_INIT: + ; RESET DSKY + CALL DSKY_RES + ; SET CLOCK SCALER TO 20 + LD A,DSKY_CMD_CLK | DSKY_PRESCL + CALL DSKY_CMD + LD A,%00001000 ; dan + CALL DSKY_CMD +; + RET +; +; HARDWARE RESET 8279 BY PULSING RESET LINE +; +DSKY_RES: +; + ; SETUP PPI + CALL DSKY_PPIRD + ; INIT 8279 VALUES TO IDLE STATE + LD A,DSKY_PPI_IDLE + OUT (PPIC),A + ; PULSE RESET SIGNAL ON 8279 + SET 7,A + OUT (PPIC),A + RES 7,A + OUT (PPIC),A + ; DONE + CALL DSKY_PPIIDLE + RET +; +; COMMAND IN A +; TRASHES BC +; +DSKY_CMD: + LD B,$01 + JR DSKY_DOUT2 +; +; DATA VALUE IN A +; TRASHES BC +; +DSKY_DOUT: + LD B,$00 +; +DSKY_DOUT2: +; + ; SAVE INCOMING DATA BYTE + PUSH AF +; + ; SET PPI LINE CONFIG TO WRITE MODE + CALL DSKY_PPIWR +; + ; SETUP + LD C,PPIC +; + ; SET ADDRESS FIRST + LD A,DSKY_PPI_IDLE + OR B + OUT (C),A +; + ; ASSERT 8279 /CS + SET 3,A + SET 4,A + OUT (C),A +; + ; PPIC WORKING VALUE TO REG B NOW + LD B,A +; + ; ASSERT DATA BYTE VALUE + POP AF + OUT (PPIA),A +; + ; PULSE /WR + RES 5,B + OUT (C),B + NOP ; MAY NOT BE NEEDED + SET 5,B + OUT (C),B +; + ; DEASSERT /CS + RES 3,B + RES 4,B + OUT (C),B +; + ; CLEAR ADDRESS BIT + RES 0,B + OUT (C),B +; + ; DONE + CALL DSKY_PPIIDLE + RET +; +; STATUS VALUE IN A +; TRASHES BC +; +DSKY_STAT: + LD B,$01 + JR DSKY_DIN2 +; +; DATA VALUE RETURNED IN A +; TRASHES BC +; +DSKY_DIN: + LD B,$00 +; +DSKY_DIN2: + ; SET PPI LINE CONFIG TO WRITE MODE + CALL DSKY_PPIRD +; + ; SETUP + LD C,PPIC +; + ; SET ADDRESS FIRST + LD A,DSKY_PPI_IDLE + OR B + OUT (C),A +; + ; ASSERT 8279 /CS + SET 3,A + SET 4,A + OUT (C),A +; + ; PPIC WORKING VALUE TO REG B NOW + LD B,A +; + ; ASSERT /RD + RES 6,B + OUT (C),B +; + ; GET VALUE + IN A,(PPIA) +; + ; DEASSERT /RD + SET 6,B + OUT (C),B +; + ; DEASSERT /CS + RES 3,B + RES 4,B + OUT (C),B +; + ; CLEAR ADDRESS BIT + RES 0,B + OUT (C),B +; + ; DONE + CALL DSKY_PPIIDLE + RET +; +; BLANK THE DISPLAY (WITHOUT USING CLEAR) +; +DSKY_BLANK: + LD A,DSKY_CMD_WDSP + CALL DSKY_CMD + LD B,16 +DSKY_BLANK1: + PUSH BC + LD A,$FF + CALL DSKY_DOUT + POP BC + DJNZ DSKY_BLANK1 + RET +; +; WRITE A RAW BYTE VALUE TO DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, VALUE IN A. +; +DSKY_PUTBYTE: + PUSH BC + PUSH AF + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP AF + XOR $FF + CALL DSKY_DOUT + POP BC + RET +; +; READ A RAW BYTE VALUE FROM DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, VALUE RETURNED IN A +; +DSKY_GETBYTE: + PUSH BC + LD A,C + ADD A,DSKY_CMD_RDSP + CALL DSKY_CMD + CALL DSKY_DIN + XOR $FF + POP BC + RET +; +; WRITE A STRING OF RAW BYTE VALUES TO DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, LENGTH IN B, ADDRESS IN HL. +; +DSKY_PUTSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP BC +; +DSKY_PUTSTR1: + LD A,(HL) + XOR $FF + INC HL + PUSH BC + CALL DSKY_DOUT + POP BC + DJNZ DSKY_PUTSTR1 + RET +; +; READ A STRING OF RAW BYTE VALUES FROM DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, LENGTH IN B, ADDRESS IN HL. +; +DSKY_GETSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_RDSP + CALL DSKY_CMD + POP BC +; +DSKY_GETSTR1: + PUSH BC + CALL DSKY_DIN + POP BC + XOR $FF + LD (HL),A + INC HL + DJNZ DSKY_GETSTR1 + RET +; +; HL IS ADR OF ENCODED STRING OF BYTES +; B IS LEN OF STRING (BYTES) +; C IS POSITION IN DISPLAY RAM TO WRITE +; +DSKY_PUTENCSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP BC + EX DE,HL +DSKY_PUTENCSTR1: + LD A,(DE) + INC DE + LD HL,HEXMAP + CALL ADDHLA + LD A,(HL) + XOR $FF + PUSH BC + CALL DSKY_DOUT + POP BC + DJNZ DSKY_PUTENCSTR1 + RET +; +; TOGGLE LED AT ROW (B) AND COLUMN (C) +; +DSKY_TOGLED: + ; CONVERT B (ROW) TO BIT VALUE + XOR A + INC B + SCF +DSKY_TOGLED1: + RLA + DJNZ DSKY_TOGLED1 + LD B,A + ; LED COLS START AT 8 + LD A,8 + ADD A,C + LD C,A + ; FLIP THE BIT + CALL DSKY_GETBYTE ; GET CURRENT COL BITMAP + XOR B ; FLIP DESIRED BIT + CALL DSKY_PUTBYTE ; WRITE VLAUE BACK TO COLUMN + RET +; +; READ AND PRINT DISPLAY RAM (RAW BYTES) +; +DSKY_READ: + CALL PRTSTRD + .DB "\r\nRead display RAM: $" + LD B,16 ; 16 BYTES + LD C,0 ; POSITION 0 + LD HL,DSPBUF + CALL DSKY_GETSTR + LD B,$10 + LD HL,DSPBUF +DSKY_READ1: + LD A,(HL) + INC HL + CALL PC_SPACE + CALL PRTHEXBYTE + DJNZ DSKY_READ1 + RET +; +; OUTPUT CHARACTER FROM A +; +COUT: + PUSH AF ; + PUSH BC ; + PUSH DE ; + PUSH HL ; + +#IF BDOS + LD C,2 ; BDOS FUNC: CONSOLE OUTPUT + LD E,A ; CHARACTER TO E + CALL $0005 ; CALL BDOS +#ELSE + LD C,A +COUT1: + IN A,(UART_BASE + 05H) ; READ LINE STATUS REGISTER + AND 20H ; TEST IF UART IS READY TO SEND + JP Z,COUT1 ; IF NOT REPEAT + LD A,C ; GET TO ACCUMULATOR + OUT (UART_BASE),A ; THEN WRITE THE CHAR TO UART (UART0 = 068h + $00) +#ENDIF + + POP HL ; + POP DE ; + POP BC ; + POP AF ; + RET ; DONE +; +; INPUT CHARACTER TO A +; +CIN: + PUSH BC ; + PUSH DE ; + PUSH HL ; +#IF BDOS +CIN1: + LD C,6 ; BDOS FUNC: DIRECT CONSOLE I/O + LD E,$FF ; SET FOR INPUT + CALL $0005 ; CALL BDOS, CHARACTER TO A + OR A ; CHECK FOR NO CHAR, $00 + JR Z,CIN1 ; LOOP TIL WE GET A CHAR +#ELSE +CIN1: + CALL CST ; IS A CHAR READY TO BE READ FROM UART? + CP 00H ; + JP Z,CIN1 ; NO? TRY AGAIN + IN A,(UART_BASE) ; YES? READ THE CHAR FROM THE UART (UART0 = 068h + $00) +#ENDIF + POP HL ; + POP DE ; + POP BC ; + RET ; DONE +; +; RETURN INPUT STATUS IN A (0 = NO CHAR, !=0 CHAR WAITING) +; +CST: + PUSH BC ; + PUSH DE ; + PUSH HL ; +#IF BDOS + LD C,$0B ; BDOS FUNC: GET CONSOLE STATUS + CALL $0005 ; CALL BDOS + OR A ; SET FLAGS +#ELSE + ; CONSOLE STATUS, RETURN 0FFH IF CHARACTER READY, 00H IF NOT + IN A,(UART_BASE + 05H) ; READ LINE STATUS REGISTER (UART5 = 068h + $05) + AND 01H ; TEST IF DATA IN RECEIVE BUFFER + ; IS THERE A CHAR READY? 0=NO, 1=YES + JP Z,CST1 ; + LD A,0FFH ; YES, PUT 0FFh IN A AND RETURN +CST1: ; + ; NO, LEAVE 000h IN A AND RETURN +#ENDIF + POP HL ; + POP DE ; + POP BC ; + RET ; DONE +; +; WAIT FOR A KEY +; +WAITKEY: + PUSH AF + CALL PRTSTRD + .DB ", press a key to continue...$" + CALL CIN + CP $1B + JP Z,EXIT + POP AF + RET +; +; CONVERT BINARY VALUE IN A TO ASCII HEX CHARACTERS IN DE +; +HEXASCII: + LD D,A + CALL HEXCONV + LD E,A + LD A,D + RLCA + RLCA + RLCA + RLCA + CALL HEXCONV + LD D,A + RET +; +; CONVERT LOW NIBBLE OF A TO ASCII HEX +; +HEXCONV: + AND 0FH ;LOW NIBBLE ONLY + ADD A,90H + DAA + ADC A,40H + DAA + RET + + + + +; +;================================================================================================== +; UTILITY FUNCTIONS +;================================================================================================== +; +; +CHR_BEL: .EQU 07H +CHR_CR: .EQU 0DH +CHR_LF: .EQU 0AH +CHR_BS: .EQU 08H +CHR_ESC: .EQU 1BH +; +;__________________________________________________________________________________________________ +; +; UTILITY PROCS TO PRINT SINGLE CHARACTERS WITHOUT TRASHING ANY REGISTERS +; +PC_SPACE: + PUSH AF + LD A,' ' + JR PC_PRTCHR + +PC_PERIOD: + PUSH AF + LD A,'.' + JR PC_PRTCHR + +PC_COLON: + PUSH AF + LD A,':' + JR PC_PRTCHR + +PC_COMMA: + PUSH AF + LD A,',' + JR PC_PRTCHR + +PC_LBKT: + PUSH AF + LD A,'[' + JR PC_PRTCHR + +PC_RBKT: + PUSH AF + LD A,']' + JR PC_PRTCHR + +PC_LT: + PUSH AF + LD A,'<' + JR PC_PRTCHR + +PC_GT: + PUSH AF + LD A,'>' + JR PC_PRTCHR + +PC_LPAREN: + PUSH AF + LD A,'(' + JR PC_PRTCHR + +PC_RPAREN: + PUSH AF + LD A,')' + JR PC_PRTCHR + +PC_ASTERISK: + PUSH AF + LD A,'*' + JR PC_PRTCHR + +PC_CR: + PUSH AF + LD A,CHR_CR + JR PC_PRTCHR + +PC_LF: + PUSH AF + LD A,CHR_LF + JR PC_PRTCHR + +PC_PRTCHR: + CALL COUT + POP AF + RET + +NEWLINE2: + CALL NEWLINE +NEWLINE: + CALL PC_CR + CALL PC_LF + RET +; +; PRINT A CHARACTER REFERENCED BY POINTER AT TOP OF STACK +; USAGE: +; CALL PRTCH +; DB 'X' +; +PRTCH: + EX (SP),HL + PUSH AF + LD A,(HL) + CALL COUT + POP AF + INC HL + EX (SP),HL + RET +; +; PRINT A STRING AT ADDRESS SPECIFIED IN HL +; STRING MUST BE TERMINATED BY '$' +; USAGE: +; LD HL,MYSTR +; CALL PRTSTR +; ... +; MYSTR: DB "HELLO$" +; +PRTSTR: + LD A,(HL) + INC HL + CP '$' + RET Z + CALL COUT + JR PRTSTR +; +; PRINT A STRING DIRECT: REFERENCED BY POINTER AT TOP OF STACK +; STRING MUST BE TERMINATED BY '$' +; USAGE: +; CALL PRTSTRD +; DB "HELLO$" +; ... +; +PRTSTRD: + EX (SP),HL + PUSH AF + CALL PRTSTR + POP AF + EX (SP),HL + RET +; +; PRINT A STRING INDIRECT: REFERENCED BY INDIRECT POINTER AT TOP OF STACK +; STRING MUST BE TERMINATED BY '$' +; USAGE: +; CALL PRTSTRI(MYSTRING) +; MYSTRING DB "HELLO$" +; +PRTSTRI: + EX (SP),HL + PUSH AF + LD A,(HL) + INC HL + PUSH HL + LD H,(HL) + LD L,A + CALL PRTSTR + POP HL + INC HL + POP AF + EX (SP),HL + RET +; +; PRINT THE HEX BYTE VALUE IN A +; +PRTHEXBYTE: + PUSH AF + PUSH DE + CALL HEXASCII + LD A,D + CALL COUT + LD A,E + CALL COUT + POP DE + POP AF + RET +; +; PRINT THE HEX WORD VALUE IN BC +; +PRTHEXWORD: + PUSH AF + LD A,B + CALL PRTHEXBYTE + LD A,C + CALL PRTHEXBYTE + POP AF + RET +; +; PRINT THE HEX WORD VALUE IN HL +; +PRTHEXWORDHL: + PUSH AF + LD A,H + CALL PRTHEXBYTE + LD A,L + CALL PRTHEXBYTE + POP AF + RET +; +; SHORT DELAY FUNCTIONS. NO CLOCK SPEED COMPENSATION, SO THEY +; WILL RUN LONGER ON SLOWER SYSTEMS. THE NUMBER INDICATES THE +; NUMBER OF CALL/RET INVOCATIONS. A SINGLE CALL/RET IS +; 27 T-STATES ON A Z80, 25 T-STATES ON A Z180 +; +; ; Z80 Z180 +; ; ---- ---- +DLY64: CALL DLY32 ; 1728 1600 +DLY32: CALL DLY16 ; 864 800 +DLY16: CALL DLY8 ; 432 400 +DLY8: CALL DLY4 ; 216 200 +DLY4: CALL DLY2 ; 108 100 +DLY2: CALL DLY1 ; 54 50 +DLY1: RET ; 27 25 +; +; ADD HL,A +; +; A REGISTER IS DESTROYED! +; +ADDHLA: + ADD A,L + LD L,A + RET NC + INC H + RET + + + + + + +; +; STORAGE +; +DSKY_PPIX_VAL: .DB 0 +; +DSPBUF: .FILL 16,0 +; +PAT1: .DB $01,$02,$04,$08,$10,$20,$40,$80 + .DB $11,$22,$44,$88,$FF,$FF,$FF,$FF +PAT1LN: .EQU $ - PAT1 +PAT2: .DB $01,$03,$07,$0F,$1F,$3F,$7F,$FF + .DB $11,$33,$77,$FF,$00,$00,$00,$00 +PAT2LN: .EQU $ - PAT2 +PAT3: .DB $FE,$FD,$FB,$F7,$EF,$DF,$BF,$7F + .DB $77,$BB,$DD,$EE,$00,$00,$00,$00 +PAT3LN: .EQU $ - PAT3 +BLANK: .DB $00,$00,$00,$00,$00,$00,$00,$00 + .DB $00,$00,$00,$00,$00,$00,$00,$00 +BLNKLN: .EQU $ - BLANK +HEX1: .DB $0,$1,$2,$3,$4,$5,$6,$7 +HEX1LN: .EQU $ - HEX1 +HEX2: .DB $8,$9,$A,$B,$C,$D,$E,$F +HEX2LN: .EQU $ - HEX2 +; +HEXMAP: + ; '0' '1' '2' '3' '4' '5' '6' '7' + .DB $3F, $06, $5B, $4F, $66, $6D, $7D, $07 + ; '8' '9' 'A' 'B' 'C' 'D' 'E' 'F' + .DB $7F, $67, $77, $7C, $39, $5E, $79, $71 + ; + .DB $00 +; +STACKSAV: .DW 0 +STACKSIZ: .EQU $100 ; WE ARE A STACK PIG + .FILL STACKSIZ,0 +STACK: .EQU $ +; + .END diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index 4e146a79..dc192246 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -19,7 +19,7 @@ param([string]$Platform = "", [string]$Config = "", [int]$RomSize = 512, [string # setup mechanism so that multiple configuration are not needed. When building for UNA, the pre-built # UNA BIOS is simply imbedded, it is not built here. # -$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "RCZ280", "EZZ80", "UNA" +$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "RCZ280", "EZZ80", "UNA" $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO" $PlatformListZ280 = "RCZ280" @@ -183,7 +183,6 @@ if ($Platform -ne "UNA") Asm 'tastybasic' Asm 'game' Asm 'usrrom' - Asm 'imgpad1' Asm 'imgpad2' } @@ -194,15 +193,15 @@ if ($Platform -ne "UNA") "Building ${RomName} output files..." # Build 32K OS chunk containing the loader, debug monitor, and two OS images -Concat 'romldr.bin', 'eastaegg.bin','dbgmon.bin', "..\cpm22\cpm_${Bios}.bin", "..\zsdos\zsys_${Bios}.bin" osimg.bin +Concat 'romldr.bin', 'dbgmon.bin', "..\cpm22\cpm_${Bios}.bin", "..\zsdos\zsys_${Bios}.bin" osimg.bin # Build 20K OS chunk containing the loader, debug monitor, and one OS image -Concat 'romldr.bin', 'eastaegg.bin','dbgmon.bin', "..\zsdos\zsys_${Bios}.bin" osimg_small.bin +Concat 'romldr.bin','dbgmon.bin', "..\zsdos\zsys_${Bios}.bin" osimg_small.bin # Build second and third 32K chunks containing supplemental ROM apps (not for UNA) if ($Platform -ne "UNA") { - Concat '..\Forth\camel80.bin', 'nascom.bin', 'tastybasic.bin', 'game.bin', 'imgpad1.bin', 'usrrom.bin' osimg1.bin + Concat '..\Forth\camel80.bin', 'nascom.bin', 'tastybasic.bin', 'game.bin', 'eastaegg.bin', 'usrrom.bin' osimg1.bin Concat 'netboot.mod', 'imgpad2.bin' osimg2.bin } diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh index 2009fc85..21adc95f 100755 --- a/Source/HBIOS/Build.sh +++ b/Source/HBIOS/Build.sh @@ -99,20 +99,20 @@ done cp ../Forth/camel80.bin . -make dbgmon.bin romldr.bin eastaegg.bin imgpad1.bin imgpad2.bin +make dbgmon.bin romldr.bin eastaegg.bin imgpad2.bin if [ $platform != UNA ] ; then - make nascom.bin tastybasic.bin game.bin usrrom.bin imgpad1.bin imgpad2.bin + make nascom.bin tastybasic.bin game.bin usrrom.bin imgpad2.bin make hbios_rom.bin hbios_app.bin hbios_img.bin fi echo "Building $romname output files..." -cat romldr.bin eastaegg.bin dbgmon.bin ../CPM22/cpm_$BIOS.bin ../ZSDOS/zsys_$BIOS.bin >osimg.bin -cat romldr.bin eastaegg.bin dbgmon.bin ../ZSDOS/zsys_$BIOS.bin >osimg_small.bin +cat romldr.bin dbgmon.bin ../CPM22/cpm_$BIOS.bin ../ZSDOS/zsys_$BIOS.bin >osimg.bin +cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$BIOS.bin >osimg_small.bin if [ $platform != UNA ] ; then - cat camel80.bin nascom.bin tastybasic.bin game.bin imgpad1.bin usrrom.bin >osimg1.bin + cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin usrrom.bin >osimg1.bin cat netboot.mod imgpad2.bin >osimg2.bin fi diff --git a/Source/HBIOS/Config/SBC_mbc.asm b/Source/HBIOS/Config/MBC_std.asm similarity index 86% rename from Source/HBIOS/Config/SBC_mbc.asm rename to Source/HBIOS/Config/MBC_std.asm index 1baa71aa..a8c21dcd 100644 --- a/Source/HBIOS/Config/SBC_mbc.asm +++ b/Source/HBIOS/Config/MBC_std.asm @@ -22,12 +22,14 @@ ; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO ; DIRECTORIES ABOVE THIS ONE). ; -#DEFINE PLATFORM_NAME "SBC" +#DEFINE PLATFORM_NAME "Multi Board Computer" #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_sbc.asm" +#include "cfg_mbc.asm" ; -INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -MEMMGR .SET MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC] +BATCOND .SET FALSE ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +DSKYENABLE .SET FALSE ; ENABLES DSKY +DSKYMODE .SET DSKYMODE_NG ; DSKY VERTSION: DSKYMODE_[V1|NG] diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile index d98c460f..a5790a06 100644 --- a/Source/HBIOS/Makefile +++ b/Source/HBIOS/Makefile @@ -24,7 +24,7 @@ else OBJECTS += RCZ80_zrc.rom RCZ80_zrc.com RCZ80_zrc.upd OBJECTS += SBC_std.rom SBC_std.com SBC_std.upd OBJECTS += SBC_simh.rom SBC_simh.com SBC_simh.upd - OBJECTS += SBC_mbc.rom SBC_mbc.com SBC_mbc.upd + OBJECTS += MBC_std.rom MBC_std.com MBC_std.upd OBJECTS += SCZ180_126.rom SCZ180_126.com SCZ180_126.upd OBJECTS += SCZ180_130.rom SCZ180_130.com SCZ180_130.upd OBJECTS += SCZ180_131.rom SCZ180_131.com SCZ180_131.upd @@ -35,7 +35,7 @@ else endif MOREDIFF = camel80.bin game.bin hbios_rom.bin nascom.bin prefix.bin usrrom.bin \ - dbgmon.bin hbios_app.bin imgpad1.bin imgpad2.bin osimg1.bin osimg2.bin romldr.bin \ + dbgmon.bin hbios_app.bin imgpad2.bin osimg1.bin osimg2.bin romldr.bin \ eastaegg.bin hbios_img.bin osimg.bin tastybasic.bin \ game.bin usrrom.bin diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index 6cc9baa1..c83fa6a7 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "DYNO" ; -PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -63,6 +63,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -163,6 +164,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -175,7 +177,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 58686d5b..c858c2c7 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "EASYZ80" ; -PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -64,6 +64,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -194,6 +195,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -210,7 +212,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index d3dbed94..4a198c10 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -10,7 +10,7 @@ ; #DEFINE PLATFORM_NAME "ROMWBW" ; -PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -63,7 +63,6 @@ MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -91,10 +90,14 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -255,6 +258,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -266,6 +270,7 @@ PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -277,7 +282,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm new file mode 100644 index 00000000..129dc15f --- /dev/null +++ b/Source/HBIOS/cfg_mbc.asm @@ -0,0 +1,231 @@ +; +;================================================================================================== +; ROMWBW 2.X CONFIGURATION DEFAULTS FOR MBC +;================================================================================================== +; +; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD +; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY +; UNDER THIS DIRECTORY. +; +; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS +; FOR THE PLATFORM. +; +#DEFINE PLATFORM_NAME "Multi Board Computer" +; +PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] +CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +; +CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +RAM_RESERVE .EQU 0 ; RESERVE FIRST N KB OF RAM (USUALLY 0) +ROM_RESERVE .EQU 0 ; RESERVE FIRST N KB OR ROM (USUALLY 0) +MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC] +MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) +MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) +; +RTCIO .EQU $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) +CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY +; +EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT +DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS +DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS +; +LEDENABLE .EQU TRUE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) +; +BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE +CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) +MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] +DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS +UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED +UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART +UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART +UARTMFP .EQU TRUE ; UART: AUTO-DETECT MF/PIC UART +UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART +UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART +; +ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] +SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM) +TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG/N8/RC/RCV9958] +TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +; +MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .EQU TRUE ; MD: ENABLE ROM DISK +MDRAM .EQU TRUE ; MD: ENABLE RAM DISK +MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +; +FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] +FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111] +FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111] +FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +; +RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $44 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY +SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +; +PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +; +PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .EQU $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER +AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4 +; +AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .EQU CPUOSC / 4 ; DEFAULT TO CPUOSC / 4 +AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180] +; +SPKENABLE .EQU TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index 6fe370c2..726c33b9 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "MARK IV" ; -PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -66,10 +66,14 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -189,6 +193,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -199,6 +204,7 @@ PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -209,7 +215,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index 9e06dcd5..b5e2d87c 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "N8" ; -PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -48,7 +48,6 @@ N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) ; RTCIO .EQU N8_RTC ; RTC LATCH REGISTER ADR -PPIBASE .EQU N8_PPI0 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -68,11 +67,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -192,6 +195,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -209,7 +213,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index 85200727..a98fa0b8 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "RC2014" ; -PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -66,6 +66,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -207,6 +208,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -223,7 +225,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm index e9145a9a..d807eb5a 100644 --- a/Source/HBIOS/cfg_rcz280.asm +++ b/Source/HBIOS/cfg_rcz280.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "RC2014" ; -PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280] +PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -71,6 +71,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -223,6 +224,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -239,7 +241,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 0a262c07..c0b45afa 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "RC2014" ; -PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -65,6 +65,7 @@ DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -212,6 +213,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -228,7 +230,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index b4f3cadd..1ad20a3e 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "SBC" ; -PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -35,7 +35,6 @@ MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -60,11 +59,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -192,6 +195,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -210,7 +214,8 @@ PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) UFBASE .EQU $0C ; UF: REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 7a85c2e4..939f8f88 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "SCZ180" ; -PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -61,6 +61,7 @@ DIAGPORT .EQU $0D ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -202,6 +203,7 @@ PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -218,7 +220,7 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_una.asm b/Source/HBIOS/cfg_una.asm index 8f589937..f2363497 100644 --- a/Source/HBIOS/cfg_una.asm +++ b/Source/HBIOS/cfg_una.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "UNA" ; -PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA] ; BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index e5f04b71..79740aa2 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "ZETA" ; -PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -35,7 +35,6 @@ MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -52,11 +51,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -137,6 +140,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -144,6 +148,7 @@ SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -152,7 +157,8 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index 37c96223..5cbdb2eb 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -13,7 +13,7 @@ ; #DEFINE PLATFORM_NAME "ZETA V2" ; -PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] +PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE @@ -38,7 +38,6 @@ MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) ; RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -PPIBASE .EQU $60 ; PRIMARY PARALLEL PORT REGISTERS BASE ADR ; KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS @@ -63,11 +62,15 @@ DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS ; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDENABLE .EQU FALSE ; ENABLES STATUS LED +LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC] +LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; -DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) +DSKYENABLE .EQU FALSE ; ENABLES DSKY +DSKYMODE .EQU DSKYMODE_V1 ; DSKY VERSION: DSKYMODE_[V1|NG] +DSKYPPIBASE .EQU $60 ; BASE I/O ADDRESS OF DSKY PPI +DSKYOSC .EQU 3000000 ; OSCILLATOR FREQ FOR DSKYNG (IN HZ) ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP @@ -148,6 +151,7 @@ PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE @@ -155,6 +159,7 @@ SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT @@ -163,7 +168,8 @@ HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) ; PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI ; UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; diff --git a/Source/HBIOS/dbgmon.asm b/Source/HBIOS/dbgmon.asm index 5aacfe6c..28bfcf7d 100644 --- a/Source/HBIOS/dbgmon.asm +++ b/Source/HBIOS/dbgmon.asm @@ -953,8 +953,13 @@ TXT_HELP .TEXT "\r\nMonitor Commands (all values in hex):" ; #IF DSKYENABLE ; -#DEFINE DSKY_KBD +#DEFINE DSKY_KBD + #IF (DSKYMODE == DSKYMODE_V1) #INCLUDE "dsky.asm" + #ENDIF + #IF (DSKYMODE == DSKYMODE_NG) +#INCLUDE "dskyng.asm" + #ENDIF ; KY_PR .EQU KY_FW ; USE [FW] FOR [PR] (PORT READ) KY_PW .EQU KY_BK ; USE [BW] FOR [PW] (PORT WRITE) @@ -1352,7 +1357,7 @@ ENCBUF1: INC HL ; BUMP TO NEXT BYTE FOR NEXT PASS PUSH AF ; SAVE IT AND $80 ; ISOLATE HI BIT (DP) - XOR $80 ; FLIP IT + ;XOR $80 ; FLIP IT LD C,A ; SAVE IN C POP AF ; RECOVER ORIGINAL AND $7F ; REMOVE HI BIT (DP) @@ -1373,8 +1378,10 @@ ENCBUF1: POP HL ; RESTORE HL RET ; -CPUUP .DB $84,$CB,$EE,$BB,$80,$BB,$EE,$84 ; "-CPU UP-" (RAW SEG) -MSGBOOT .DB $FF,$9D,$9D,$8F,$20,$80,$80,$80 ; "Boot! " (RAW SEG) +#IF (DSKYMODE == DSKYMODE_V1) +; +CPUUP .DB $04,$4B,$6E,$3B,$00,$3B,$6E,$04 ; "-CPU UP-" (RAW SEG) +MSGBOOT .DB $7F,$1D,$1D,$0F,$A0,$00,$00,$00 ; "Boot! " (RAW SEG) ADDR .DB $17,$18,$19,$10,$00,$00,$00,$00 ; "Adr 0000" (ENCODED) PORT .DB $13,$14,$15,$16,$10,$10,$00,$00 ; "Port 00" (ENCODED) GOTO .DB $1A,$14,$10,$10,$00,$00,$00,$00 ; "Go 0000" (ENCODED) @@ -1385,6 +1392,7 @@ GOTO .DB $1A,$14,$10,$10,$00,$00,$00,$00 ; "Go 0000" (ENCODED) ;_____________________________________________________________________________ ; SEGDECODE: +; ; POS $00 $01 $02 $03 $04 $05 $06 $07 ; GLYPH '0' '1' '2' '3' '4' '5' '6' '7' .DB $7B, $30, $6D, $75, $36, $57, $5F, $70 @@ -1397,6 +1405,37 @@ SEGDECODE: ; GLYPH ' ' '-' '.' 'P' 'o' 'r' 't' 'A' 'd' 'r' 'G' .DB $00, $04, $00, $6E, $1D, $0C, $0F, $7E, $3D, $0C, $5B ; +#ENDIF +; +#IF (DSKYMODE == DSKYMODE_NG) +; +CPUUP .DB $40,$39,$73,$3E,$00,$3E,$73,$40 ; "-CPU UP-" (RAW SEG) +MSGBOOT .DB $7F,$5C,$5C,$78,$A0,$00,$00,$00 ; "Boot! " (RAW SEG) +ADDR .DB $17,$18,$19,$10,$00,$00,$00,$00 ; "Adr 0000" (ENCODED) +PORT .DB $13,$14,$15,$16,$10,$10,$00,$00 ; "Port 00" (ENCODED) +GOTO .DB $1A,$14,$10,$10,$00,$00,$00,$00 ; "Go 0000" (ENCODED) +; +;_HEX_7_SEG_DECODE_TABLE______________________________________________________ +; +; SET BIT 7 TO DISPLAY W/ DECIMAL POINT +;_____________________________________________________________________________ +; +SEGDECODE: +; + ; POS $00 $01 $02 $03 $04 $05 $06 $07 + ; GLYPH '0' '1' '2' '3' '4' '5' '6' '7' + .DB $3F, $06, $58, $4F, $66, $6D, $7D, $07 +; + ; POS $08 $09 $0A $0B $0C $0D $0E $0F + ; GLYPH '8' '9' 'A' 'B' 'C' 'D' 'E' 'F' + .DB $7F, $67, $77, $7C, $39, $5E, $79, $71 +; + ; POS $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A + ; GLYPH ' ' '-' '.' 'P' 'o' 'r' 't' 'A' 'd' 'r' 'G' + .DB $00, $40, $00, $73, $5C, $50, $78, $77, $5E, $50, $3D +; +#ENDIF +; DISPLAYBUF: .FILL 8,0 ; #ELSE diff --git a/Source/HBIOS/dsky.asm b/Source/HBIOS/dsky.asm index 26b9e92a..464836cd 100644 --- a/Source/HBIOS/dsky.asm +++ b/Source/HBIOS/dsky.asm @@ -3,10 +3,13 @@ ; DSKY ROUTINES ;================================================================================================== ; -PPIA .EQU PPIBASE + 0 ; PORT A -PPIB .EQU PPIBASE + 1 ; PORT B -PPIC .EQU PPIBASE + 2 ; PORT C -PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT +; THE DSKY MAY COSESIDE ON THE SAME PPI BUS AS A PPISD. IT MAY NOT +; SHARE A PPI BUS WITH A PPIDE. +; +PPIA .EQU DSKYPPIBASE + 0 ; PORT A +PPIB .EQU DSKYPPIBASE + 1 ; PORT B +PPIC .EQU DSKYPPIBASE + 2 ; PORT C +PPIX .EQU DSKYPPIBASE + 3 ; PPI CONTROL PORT ; ; ICM7218A KEYPAD PPISD ; -------- -------- -------- @@ -26,6 +29,15 @@ PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT ; BITS 7-6 IDENTFY THE COLUMN OF THE KEY PRESSED ; BITS 5-0 ARE A BITMAP, WITH A BIT ON TO INDICATE ROW OF KEY PRESSED ; +; +; LED SEGMENTS (BIT VALUES) +; +; +--40--+ +; 02 20 +; +--04--+ +; 08 10 +; +--01--+ 80 +; ; ____PC0________PC1________PC2________PC3____ ; PB5 | $20 [D] $60 [E] $A0 [F] $E0 [BO] ; PB4 | $10 [A] $50 [B] $90 [C] $D0 [GO] @@ -278,7 +290,12 @@ DSKY_SHOW: LD B,DSKY_BUFLEN ; NUMBER OF DIGITS LD C,PPIA DSKY_HEXOUT2: - OUTI + ;OUTI + LD A,(HL) + XOR $80 ; FIX DOT POLARITY + OUT (C),A + INC HL + DEC B JP Z,DSKY_STROBE ; DO FINAL STROBE AND RETURN CALL DSKY_STROBE ; STROBE BYTE VALUE JR DSKY_HEXOUT2 @@ -301,22 +318,22 @@ DSKY_COFF: ; CLEAR HIGH BIT TO SHOW DECIMAL POINT ; DSKY_NUMS: - .DB $FB ; 0 - .DB $B0 ; 1 - .DB $ED ; 2 - .DB $F5 ; 3 - .DB $B6 ; 4 - .DB $D7 ; 5 - .DB $DF ; 6 - .DB $F0 ; 7 - .DB $FF ; 8 - .DB $F7 ; 9 - .DB $FE ; A - .DB $9F ; B - .DB $CB ; C - .DB $BD ; D - .DB $CF ; E - .DB $CE ; F + .DB $7B ; 0 + .DB $30 ; 1 + .DB $6D ; 2 + .DB $75 ; 3 + .DB $36 ; 4 + .DB $57 ; 5 + .DB $5F ; 6 + .DB $70 ; 7 + .DB $7F ; 8 + .DB $77 ; 9 + .DB $7E ; A + .DB $1F ; B + .DB $4B ; C + .DB $3D ; D + .DB $4F ; E + .DB $4E ; F ; ; SEG DISPLAY WORKING STORAGE ; diff --git a/Source/HBIOS/dskyng.asm b/Source/HBIOS/dskyng.asm new file mode 100644 index 00000000..53305e6a --- /dev/null +++ b/Source/HBIOS/dskyng.asm @@ -0,0 +1,561 @@ +; +;================================================================================================== +; DSKY NEXT GEN ROUTINES +;================================================================================================== +; +; A DSKYNG CAN SHARE A PPI BUS WITH EITHER A PPIDE OR PPISD. +; +; LED SEGMENTS (BIT VALUES) +; +; +--01--+ +; 20 02 +; +--40--+ +; 10 04 +; +--08--+ 80 +; +; KEY CODE MAP (KEY CODES) --CCCRRR +; +; 00 08 10 18 +; 01 09 11 19 +; 02 0A 12 1A +; 03 0B 13 1B +; 04 0C 14 1C +; 05 0D 15 1D +; +; LED BIT MAP (BIT VALUES) +; +; $08 $09 $0A $0B +; --- --- --- --- +; 01 01 01 01 +; 02 02 02 02 +; 04 04 04 04 +; 08 08 08 08 +; 10 10 10 10 +; 20 20 20 20 +; +PPIA .EQU DSKYPPIBASE + 0 ; PORT A +PPIB .EQU DSKYPPIBASE + 1 ; PORT B +PPIC .EQU DSKYPPIBASE + 2 ; PORT C +PPIX .EQU DSKYPPIBASE + 3 ; PPI CONTROL PORT +; +DSKY_PPIX_RD: .EQU %10010010 ; PPIX VALUE FOR READS +DSKY_PPIX_WR: .EQU %10000010 ; PPIX VALUE FOR WRITES +; +; PIO CHANNEL C: +; +; 7 6 5 4 3 2 1 0 +; RES /RD /WR CS CS 0 0 A0 +; +; SETTING BITS 3 & 4 WILL ASSERT /CS ON 3279 +; CLEAR BITS 5 OR 6 TO ASSERT READ/WRITE +; +DSKY_PPI_IDLE: .EQU %01100000 +; +DSKY_CMD_CLR: .EQU %11011111 ; CLEAR (ALL OFF) +DSKY_CMD_CLRX: .EQU %11010011 ; CLEAR (ALL ON) +DSKY_CMD_WDSP: .EQU %10010000 ; WRITE DISPLAY RAM +DSKY_CMD_RDSP: .EQU %01110000 ; READ DISPLAY RAM +DSKY_CMD_CLK: .EQU %00100000 ; SET CLK PRESCALE +DSKY_CMD_FIFO: .EQU %01000000 ; READ FIFO +; +DSKY_PRESCL: .EQU DSKYOSC/100000 ; PRESCALER +; +;__DSKY_INIT_________________________________________________________________________________________ +; +; CONFIGURE PARALLEL PORT AND INITIALIZE 8279 +;____________________________________________________________________________________________________ +; +; +; HARDWARE RESET 8279 BY PULSING RESET LINE +; +DSKY_INIT: +; + ; SETUP PPI + CALL DSKY_PPIRD + ; INIT 8279 VALUES TO IDLE STATE + LD A,DSKY_PPI_IDLE + OUT (PPIC),A + ; PULSE RESET SIGNAL ON 8279 + SET 7,A + OUT (PPIC),A + RES 7,A + OUT (PPIC),A + ; DONE +; +DSKY_REINIT: + CALL DSKY_PPIIDLE + ; SET CLOCK SCALER TO 20 + LD A,DSKY_CMD_CLK | DSKY_PRESCL + CALL DSKY_CMD + LD A,%00001000 ; dan + CALL DSKY_CMD + ; FALL THRU +; +DSKY_RESET: + ; RESET DSKY + LD A,DSKY_CMD_CLR + CALL DSKY_CMD + RET +; +#IFDEF DSKY_KBD +; +KY_0 .EQU $00 +KY_1 .EQU $01 +KY_2 .EQU $02 +KY_3 .EQU $03 +KY_4 .EQU $04 +KY_5 .EQU $05 +KY_6 .EQU $06 +KY_7 .EQU $07 +KY_8 .EQU $08 +KY_9 .EQU $09 +KY_A .EQU $0A +KY_B .EQU $0B +KY_C .EQU $0C +KY_D .EQU $0D +KY_E .EQU $0E +KY_F .EQU $0F +KY_FW .EQU $10 ; FORWARD +KY_BK .EQU $11 ; BACKWARD +KY_CL .EQU $12 ; CLEAR +KY_EN .EQU $13 ; ENTER +KY_DE .EQU $14 ; DEPOSIT +KY_EX .EQU $15 ; EXAMINE +KY_GO .EQU $16 ; GO +KY_BO .EQU $17 ; BOOT +; +;__DSKY_STAT_________________________________________________________________________________________ +; +; CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS +;____________________________________________________________________________________________________ +; +DSKY_STAT: + CALL DSKY_ST + AND $0F ; ISOLATE THE CUR FIFO LEN + RET +; +;__DSKY_GETKEY_____________________________________________________________________________________ +; +; WAIT FOR A DSKY KEYPRESS AND RETURN +;____________________________________________________________________________________________________ +; +DSKY_GETKEY: + CALL DSKY_STAT + JR Z,DSKY_GETKEY ; LOOP IF NOTHING THERE + LD A,DSKY_CMD_FIFO + CALL DSKY_CMD + CALL DSKY_DIN + LD B,24 ; SIZE OF DECODE TABLE + LD C,0 ; INDEX + LD HL,DSKY_KEYMAP ; POINT TO BEGINNING OF TABLE +DSKY_GETKEY1: + CP (HL) ; MATCH? + JR Z,DSKY_GETKEY2 ; FOUND, DONE + INC HL + INC C ; BUMP INDEX + DJNZ DSKY_GETKEY1 ; LOOP UNTIL EOT + LD A,$FF ; NOT FOUND ERR, RETURN $FF + RET +DSKY_GETKEY2: + ; RETURN THE INDEX POSITION WHERE THE SCAN CODE WAS FOUND + LD A,C ; RETURN INDEX VALUE + RET +; +;_KEYMAP_TABLE_____________________________________________________________________________________________________________ +; +DSKY_KEYMAP: + ; POS $00 $01 $02 $03 $04 $05 $06 $07 + ; KEY [0] [1] [2] [3] [4] [5] [6] [7] + .DB $0D, $04, $0C, $14, $03, $0B, $13, $02 +; + ; POS $08 $09 $0A $0B $0C $0D $0E $0F + ; KEY [8] [9] [A] [B] [C] [D] [E] [F] + .DB $0A, $12, $01, $09, $11, $00, $08, $10 +; + ; POS $10 $11 $12 $13 $14 $15 $16 $17 + ; KEY [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO] + .DB $05, $15, $1D, $1C, $1B, $1A, $19, $18 +; +#ENDIF ; DSKY_KBD +; +;================================================================================================== +; DSKY HEX DISPLAY +;================================================================================================== +; +DSKY_HEXOUT: + LD B,DSKY_HEXBUFLEN + LD HL,DSKY_BUF + LD DE,DSKY_HEXBUF +DSKY_HEXOUT1: + LD A,(DE) ; FIRST NIBBLE + SRL A + SRL A + SRL A + SRL A + PUSH HL + LD HL,HEXMAP + CALL DSKY_ADDHLA + LD A,(HL) + POP HL + LD (HL),A + INC HL + LD A,(DE) ; SECOND NIBBLE + AND 0FH + PUSH HL + LD HL,HEXMAP + CALL DSKY_ADDHLA + LD A,(HL) + POP HL + LD (HL),A + INC HL + INC DE ; NEXT BYTE + DJNZ DSKY_HEXOUT1 + LD HL,DSKY_BUF + JR DSKY_SHOW +; +;================================================================================================== +; DSKY SHOW BUFFER +; HL: ADDRESS OF BUFFER +; ENTER @ SHOWHEX FOR HEX DECODING +; ENTER @ SHOWSEG FOR SEGMENT DECODING +;================================================================================================== +; +DSKY_SHOWHEX: + JR DSKY_SHOW +; +DSKY_SHOWSEG: + JR DSKY_SHOW +; +DSKY_SHOW: +; PUSH HL +; CALL DSKY_RESET +; POP HL + LD C,0 ; STARTING DISPLAY POSITION + LD B,DSKY_BUFLEN ; NUMBER OF CHARS + JP DSKY_PUTSTR +; +; +; +; +; COMMAND IN A +; TRASHES BC +; +DSKY_CMD: + LD B,$01 + JR DSKY_DOUT2 +; +; DATA VALUE IN A +; TRASHES BC +; +DSKY_DOUT: + LD B,$00 +; +DSKY_DOUT2: +; + ; SAVE INCOMING DATA BYTE + PUSH AF +; + ; SET PPI LINE CONFIG TO WRITE MODE + CALL DSKY_PPIWR +; + ; SETUP + LD C,PPIC +; + ; SET ADDRESS FIRST + LD A,DSKY_PPI_IDLE + OR B + OUT (C),A +; + ; ASSERT 8279 /CS + SET 3,A + SET 4,A + OUT (C),A +; + ; PPIC WORKING VALUE TO REG B NOW + LD B,A +; + ; ASSERT DATA BYTE VALUE + POP AF + OUT (PPIA),A +; + ; PULSE /WR + RES 5,B + OUT (C),B + NOP ; MAY NOT BE NEEDED + SET 5,B + OUT (C),B +; + ; DEASSERT /CS + RES 3,B + RES 4,B + OUT (C),B +; + ; CLEAR ADDRESS BIT + RES 0,B + OUT (C),B +; + ; DONE + CALL DSKY_PPIIDLE + RET +; +; STATUS VALUE IN A +; TRASHES BC +; +DSKY_ST: + LD B,$01 + JR DSKY_DIN2 +; +; DATA VALUE RETURNED IN A +; TRASHES BC +; +DSKY_DIN: + LD B,$00 +; +DSKY_DIN2: + ; SET PPI LINE CONFIG TO WRITE MODE + CALL DSKY_PPIRD +; + ; SETUP + LD C,PPIC +; + ; SET ADDRESS FIRST + LD A,DSKY_PPI_IDLE + OR B + OUT (C),A +; + ; ASSERT 8279 /CS + SET 3,A + SET 4,A + OUT (C),A +; + ; PPIC WORKING VALUE TO REG B NOW + LD B,A +; + ; ASSERT /RD + RES 6,B + OUT (C),B +; + ; GET VALUE + IN A,(PPIA) +; + ; DEASSERT /RD + SET 6,B + OUT (C),B +; + ; DEASSERT /CS + RES 3,B + RES 4,B + OUT (C),B +; + ; CLEAR ADDRESS BIT + RES 0,B + OUT (C),B +; + ; DONE + CALL DSKY_PPIIDLE + RET +; +; BLANK THE DISPLAY (WITHOUT USING CLEAR) +; +DSKY_BLANK: + LD A,DSKY_CMD_WDSP + CALL DSKY_CMD + LD B,16 +DSKY_BLANK1: + PUSH BC + LD A,$FF + CALL DSKY_DOUT + POP BC + DJNZ DSKY_BLANK1 + RET +; +; WRITE A RAW BYTE VALUE TO DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, VALUE IN A. +; +DSKY_PUTBYTE: + PUSH BC + PUSH AF + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP AF + XOR $FF + CALL DSKY_DOUT + POP BC + RET +; +; READ A RAW BYTE VALUE FROM DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, VALUE RETURNED IN A +; +DSKY_GETBYTE: + PUSH BC + LD A,C + ADD A,DSKY_CMD_RDSP + CALL DSKY_CMD + CALL DSKY_DIN + XOR $FF + POP BC + RET +; +; WRITE A STRING OF RAW BYTE VALUES TO DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, LENGTH IN B, ADDRESS IN HL. +; +DSKY_PUTSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP BC +; +DSKY_PUTSTR1: + LD A,(HL) + XOR $FF + INC HL + PUSH BC + CALL DSKY_DOUT + POP BC + DJNZ DSKY_PUTSTR1 + RET +; +; READ A STRING OF RAW BYTE VALUES FROM DSKY DISPLAY RAM +; AT LOCATION IN REGISTER C, LENGTH IN B, ADDRESS IN HL. +; +DSKY_GETSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_RDSP + CALL DSKY_CMD + POP BC +; +DSKY_GETSTR1: + PUSH BC + CALL DSKY_DIN + POP BC + XOR $FF + LD (HL),A + INC HL + DJNZ DSKY_GETSTR1 + RET +; +; HL IS ADR OF ENCODED STRING OF BYTES +; B IS LEN OF STRING (BYTES) +; C IS POSITION IN DISPLAY RAM TO WRITE +; +DSKY_PUTENCSTR: + PUSH BC + LD A,C + ADD A,DSKY_CMD_WDSP + CALL DSKY_CMD + POP BC + EX DE,HL +DSKY_PUTENCSTR1: + LD A,(DE) + INC DE + LD HL,HEXMAP + CALL DSKY_ADDHLA + LD A,(HL) + XOR $FF + PUSH BC + CALL DSKY_DOUT + POP BC + DJNZ DSKY_PUTENCSTR1 + RET +; +; SETUP PPI FOR WRITING: PUT PPI PORT A IN OUTPUT MODE +; AVOID REWRTING PPIX IF ALREADY IN OUTPUT MODE +; +DSKY_PPIWR: + PUSH AF +; + ; CHECK FOR WRITE MODE + LD A,(DSKY_PPIX_VAL) + CP DSKY_PPIX_WR + JR Z,DSKY_PPIWR1 +; + ; SET PPI TO WRITE MODE + LD A,DSKY_PPIX_WR + OUT (PPIX),A + LD (DSKY_PPIX_VAL),A +; + ; RESTORE PORT C (MAY NOT BE NEEDED) + LD A,DSKY_PPI_IDLE + OUT (PPIC),A +; +DSKY_PPIWR1: +; + POP AF + RET +; +; +; +DSKY_ADDHLA: + ADD A,L + LD L,A + RET NC + INC H + RET +; +; SETUP PPI FOR READING: PUT PPI PORT A IN INPUT MODE +; AVOID REWRTING PPIX IF ALREADY IN INPUT MODE +; +DSKY_PPIRD: + PUSH AF +; + ; CHECK FOR READ MODE + LD A,(DSKY_PPIX_VAL) + CP DSKY_PPIX_RD + JR Z,DSKY_PPIRD1 +; + ; SET PPI TO READ MODE + LD A,DSKY_PPIX_RD + OUT (PPIX),A + LD (DSKY_PPIX_VAL),A +; +; ; DIAGNOSTIC +; LD A,'R' +; CALL COUT +; +DSKY_PPIRD1: + POP AF + RET +; +; RELEASE USE OF PPI +; +DSKY_PPIIDLE: + JR DSKY_PPIRD ; SAME AS READ MODE +; +; +; + +; +; CODES FOR NUMERICS +; HIGH BIT ALWAYS SET TO SUPPRESS DECIMAL POINT +; CLEAR HIGH BIT TO SHOW DECIMAL POINT +; +HEXMAP: +DSKY_NUMS: + .DB $3F ; 0 + .DB $06 ; 1 + .DB $5B ; 2 + .DB $4F ; 3 + .DB $66 ; 4 + .DB $6D ; 5 + .DB $7D ; 6 + .DB $07 ; 7 + .DB $7F ; 8 + .DB $67 ; 9 + .DB $77 ; A + .DB $7C ; B + .DB $39 ; C + .DB $5E ; D + .DB $79 ; E + .DB $71 ; F +; +DSKY_PPIX_VAL: .DB 0 +; +; SEG DISPLAY WORKING STORAGE +; +DSKY_BUF .FILL 8,0 +DSKY_BUFLEN .EQU $ - DSKY_BUF +DSKY_HEXBUF .FILL 4,0 +DSKY_HEXBUFLEN .EQU $ - DSKY_HEXBUF diff --git a/Source/HBIOS/dsrtc.asm b/Source/HBIOS/dsrtc.asm index 4384cce7..0d113169 100644 --- a/Source/HBIOS/dsrtc.asm +++ b/Source/HBIOS/dsrtc.asm @@ -132,12 +132,12 @@ DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW) ; DSRTC_PREINIT: ; - ; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER - ; TO THEIR QUIESENT STATE - LD A,(DSRTC_OPRVAL) ; GET CURRENT SHADOW REG VAL - AND ~DSRTC_MASK ; CLEAR OUR BITS - OR DSRTC_IDLE ; SET OUR IDLE BITS - LD (DSRTC_OPRVAL),A ; SAVE IT + ;; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER + ;; TO THEIR QUIESENT STATE + ;LD A,(DSRTC_OPRVAL) ; GET CURRENT SHADOW REG VAL + ;AND ~DSRTC_MASK ; CLEAR OUR BITS + ;OR DSRTC_IDLE ; SET OUR IDLE BITS + ;LD (DSRTC_OPRVAL),A ; SAVE IT ; CALL DSRTC_DETECT ; HARDWARE DETECTION LD (DSRTC_STAT),A ; SAVE RESULT @@ -478,6 +478,7 @@ DSRTC_TSTCLK: ; E=VALUE (OUTPUT) ; DSRTC_RDBYT: + CALL DSRTC_START LD E,C CALL DSRTC_CMD CALL DSRTC_GET @@ -489,6 +490,7 @@ DSRTC_RDBYT: ; E=VALUE ; DSRTC_WRBYT: + CALL DSRTC_START PUSH DE ; SAVE VALUE TO WRITE LD E,C ; CMD TO E CALL DSRTC_CMD @@ -525,6 +527,7 @@ DSRTC_WRBYTWP: ; BURST READ CLOCK DATA INTO BUFFER AT HL ; DSRTC_RDCLK: + CALL DSRTC_START LD E,$BF ; COMMAND = $BF TO BURST READ CLOCK CALL DSRTC_CMD ; SEND COMMAND TO RTC LD B,DSRTC_BUFSIZ ; B IS LOOP COUNTER @@ -540,6 +543,7 @@ DSRTC_RDCLK1: ; BURST WRITE CLOCK DATA FROM BUFFER AT HL ; DSRTC_WRCLK: + CALL DSRTC_START LD E,$8E ; COMMAND = $8E TO WRITE CONTROL REGISTER CALL DSRTC_CMD ; SEND COMMAND LD E,$00 ; $00 = UNPROTECT @@ -668,6 +672,25 @@ DSRTC_GET1: CALL DLY1 ; DELAY 27 T-STATES DJNZ DSRTC_GET1 ; LOOP IF NOT DONE (13) RET + + +; +; START A COMMAND SEQUENCE +; INITIATES A COMMAND SEQUENCE +; DOES NOT DESTROY ANY REGISTERS. +; +; 1) CAPTURE RTC LATCH BITS +; +DSRTC_START: + ; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER + ; TO THEIR QUIESENT STATE + PUSH AF + LD A,(DSRTC_OPRVAL) ; GET CURRENT SHADOW REG VAL + AND ~DSRTC_MASK ; CLEAR OUR BITS + OR DSRTC_IDLE ; SET OUR IDLE BITS + LD (DSRTC_OPRVAL),A ; SAVE IT + POP AF + RET ; ; COMPLETE A COMMAND SEQUENCE ; FINISHES UP A COMMAND SEQUENCE. @@ -676,8 +699,10 @@ DSRTC_GET1: ; 1) SET ALL LINES BACK TO QUIESCENT STATE ; DSRTC_END: + ;PUSH AF LD A,(DSRTC_OPRVAL) ; INIT A WITH QUIESCENT STATE OUT (DSRTC_IO),A ; WRITE TO PORT + ;POP AF RET ; RETURN ; ; WORKING VARIABLES diff --git a/Source/HBIOS/imgpad1.asm b/Source/HBIOS/imgpad1.asm deleted file mode 100644 index 2aa54841..00000000 --- a/Source/HBIOS/imgpad1.asm +++ /dev/null @@ -1,12 +0,0 @@ -#INCLUDE "std.asm" -; -SLACK .EQU ($8000-BAS_SIZ-TBC_SIZ-FTH_SIZ-GAM_SIZ-USR_SIZ) - .FILL SLACK,00H -; -MON_STACK .EQU $ -; - .ECHO "Padspace space created: " - .ECHO SLACK - .ECHO " bytes.\n" - - .END \ No newline at end of file diff --git a/Source/HBIOS/pio.asm b/Source/HBIOS/pio.asm index 05f3e45b..f198f25a 100644 --- a/Source/HBIOS/pio.asm +++ b/Source/HBIOS/pio.asm @@ -929,10 +929,10 @@ DEFPIO(PIO4BASE+12,M_Output,M_Output,M_BitAllOut,M_Output,INT_N,INT_N) DEFPIO(PIOZBASE+0,M_Input,M_Input,M_BitAllOut,M_BitAllOut,INT_N,INT_N) DEFPIO(PIOZBASE+4,M_Output,M_Output,M_BitAllOut,M_BitAllOut,INT_N,INT_N) #ENDIF -; PPI_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC)) +; PIO_SBC & (PLATFORM == PLT_SBC) & (PPIDEMODE != PPIDEMODE_SBC)) -#IF PPI_SBC -DEFPPI(PPIBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut) +#IF PIO_SBC +DEFPPI(PIOSBASE,M_Output,M_Output,M_Output,M_BitAllOut,M_BitAllOut,M_BitAllOut) #ENDIF ; PIO_CNT .EQU ($ - PIO_CFG) / CFG_SIZ diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm index b62e08e9..da6011e2 100644 --- a/Source/HBIOS/ppide.asm +++ b/Source/HBIOS/ppide.asm @@ -1011,6 +1011,22 @@ PPIDE_RESET: ;OUT (PPIDE_IO_PPI),A ; DO IT LD C,(IY+PPIDE_PPI) ; PPI CONTROL WORD OUT (C),A ; WRITE IT +; +; IF A DSKYNG IS ACTIVE AND IS ON THE SAME PPI PORT AS THE PPISD BEING +; RESET, THEN THE DSKYNG WILL ALSO BE RESET. SO, THE RESET CODE IS +; BRACKETED WITH CODE TO SAVE AND RESTORE THE STATE OF THE DSKYNG. +; THERE IS NO CHECK FOR THE SPECIFIC PPI PORT SINCE IT DOES NO HARM +; IF THE DSKYNG IS SAVED AND RESTORED. +; +#IF (DSKYENABLE) + #IF (DSKYMODE == DSKYMODE_NG) + ; SAVE CONTENTS OF DSKY DISPLAY ACROSS RESET + LD B,8 + LD C,0 + LD HL,DSKY_BUF + CALL DSKY_GETSTR + #ENDIF +#ENDIF ; ; PULSE IDE RESET LINE LD A,PPIDE_CTL_RESET @@ -1024,6 +1040,17 @@ PPIDE_RESET: OUT (C),A LD DE,20 CALL VDELAY +; +#IF (DSKYENABLE) + #IF (DSKYMODE == DSKYMODE_NG) + ; REININT DSKY AND RESTORE CONTENTS + CALL DSKY_REINIT + LD B,8 + LD C,0 + LD HL,DSKY_BUF + CALL DSKY_PUTSTR + #ENDIF +#ENDIF ; LD A,%00001010 ; SET ~IEN, NO INTERRUPTS ;OUT (PPIDE_REG_CTRL),A diff --git a/Source/HBIOS/ppp.asm b/Source/HBIOS/ppp.asm index 5a4032fc..d3b59f05 100644 --- a/Source/HBIOS/ppp.asm +++ b/Source/HBIOS/ppp.asm @@ -6,9 +6,9 @@ ; TODO: ; 1) ADD SUPPORT FOR DSKY ; -PPP_IO .EQU PPIBASE + 0 ; PPP DATA I/O (PPI PORT A) -PPP_CTL .EQU PPIBASE + 2 ; PPP CTL LINES (PPI PORT C) -PPP_PPICTL .EQU PPIBASE + 3 ; PPI CONTROL PORT +PPP_IO .EQU PPPBASE + 0 ; PPP DATA I/O (PPI PORT A) +PPP_CTL .EQU PPPBASE + 2 ; PPP CTL LINES (PPI PORT C) +PPP_PPICTL .EQU PPPBASE + 3 ; PPI CONTROL PORT ; ; COMMAND BYTES ; @@ -49,7 +49,7 @@ PPP_CMDVER .EQU $F1 ; SEND FIRMWARE VERSION PPP_INIT: CALL NEWLINE ; FORMATTING PRTS("PPP: IO=0x$") - LD A,PPIBASE + LD A,PPPBASE CALL PRTHEXBYTE ; CALL PPP_INITPPP ; INIT PPP BOARD @@ -358,7 +358,7 @@ PPPCON_DEVICE: LD E,0 ; E := DEVICE NUM, ALWAYS 0 LD C,$BF ; C := DEVICE TYPE, 0xBF IS PROP TERM LD H,0 ; H := 0, DRIVER HAS NO MODES - LD L,PPIBASE ; L := BASE I/O ADDRESS + LD L,PPPBASE ; L := BASE I/O ADDRESS XOR A ; SIGNAL SUCCESS RET ; @@ -694,7 +694,7 @@ PPPSD_DEVICE: LD E,(IY+PPPSD_DEV) ; E := PHYSICAL DEVICE NUMBER LD C,%01010000 ; C := ATTRIBUTES, REMOVABLE, SD CARD LD H,0 ; H := 0, DRIVER HAS NO MODES - LD L,PPIBASE ; L := BASE I/O ADDRESS + LD L,PPPBASE ; L := BASE I/O ADDRESS XOR A ; SIGNAL SUCCESS RET ; diff --git a/Source/HBIOS/romldr.asm b/Source/HBIOS/romldr.asm index 33d3dbfa..a87a38fc 100644 --- a/Source/HBIOS/romldr.asm +++ b/Source/HBIOS/romldr.asm @@ -1078,8 +1078,16 @@ clrled: out (DIAGPORT),a ; clear diag leds #endif #if (LEDENABLE) - or $FF ; led is inverted + #if (LEDMODE == LEDMODE_STD) + ld a,$FF ; led is inverted out (LEDPORT),a ; clear led + #endif + #if (LEDMODE == LEDMODE_RTC) + ; Only bits 0 and 1 of the RTC latch are for the LEDs. Here, + ; we assume that it is OK to zero all bits of the RTC latch. + xor a ; turn off + out (LEDPORT),a ; clear led + #endif #endif #endif ret @@ -1903,9 +1911,14 @@ str_err_api .db "Unexpected hardware BIOS API failure",0 ; #if (DSKYENABLE) #define DSKY_KBD + #if (DSKYMODE == DSKYMODE_V1) VDELAY .equ vdelay DLY2 .equ dly2 #include "dsky.asm" + #endif + #if (DSKYMODE == DSKYMODE_NG) +#include "dskyng.asm" + #endif #endif ; ;======================================================================= @@ -1957,10 +1970,18 @@ str_help .db "\r\n" .db 0 ; #if (DSKYENABLE) -msg_sel .db $ff,$9d,$9d,$8f,$ec,$80,$80,$80 ; "boot? " -msg_boot .db $ff,$9d,$9d,$8f,$00,$00,$00,$80 ; "boot... " -msg_load .db $8b,$9d,$fd,$bd,$00,$00,$00,$80 ; "load... " -msg_go .db $db,$9d,$00,$00,$00,$80,$80,$80 ; "go... " + #if (DSKYMODE == DSKYMODE_V1) +msg_sel .db $7f,$1d,$1d,$0f,$6c,$00,$00,$00 ; "boot? " +msg_boot .db $7f,$1d,$1d,$0f,$80,$80,$80,$00 ; "boot... " +msg_load .db $0b,$1d,$7d,$3d,$80,$80,$80,$00 ; "load... " +msg_go .db $5b,$1d,$80,$80,$80,$00,$00,$00 ; "go... " + #endif + #if (DSKYMODE == DSKYMODE_NG) +msg_sel .db $7f,$5c,$5c,$78,$53,$00,$00,$00 ; "boot? " +msg_boot .db $7f,$5c,$5c,$78,$80,$80,$80,$00 ; "boot... " +msg_load .db $38,$5c,$5f,$5e,$80,$80,$80,$00 ; "load... " +msg_go .db $3d,$5c,$80,$80,$80,$00,$00,$00 ; "go... " + #endif #endif ; ;======================================================================= @@ -2050,13 +2071,13 @@ ra_ent(str_fth, 'F', KY_EX, BID_IMG1, $0000, FTH_LOC, FTH_SIZ, FTH_LOC) ra_ent(str_bas, 'B', KY_DE, BID_IMG1, $1700, BAS_LOC, BAS_SIZ, BAS_LOC) ra_ent(str_tbas, 'T', KY_EN, BID_IMG1, $3700, TBC_LOC, TBC_SIZ, TBC_LOC) ra_ent(str_play, 'P', $FF, BID_IMG1, $4000, GAM_LOC, GAM_SIZ, GAM_LOC) -ra_ent(str_user, 'U', $FF, BID_IMG1, $7000, USR_LOC, USR_SIZ, USR_LOC) +ra_ent(str_egg, 'E'+$80, $FF, BID_IMG1, $4900, EGG_LOC, EGG_SIZ, EGG_LOC) +ra_ent(str_user, 'U', $FF, BID_IMG1, $4B00, USR_LOC, USR_SIZ, USR_LOC) ra_ent(str_net, 'N', $FF, BID_IMG2, $0000, NET_LOC, NET_SIZ, NET_LOC) #endif #if (DSKYENABLE) -ra_ent(str_dsky, 'Y'+$80, KY_GO, bid_cur, $1000, MON_LOC, MON_SIZ, MON_DSKY) +ra_ent(str_dsky, 'Y'+$80, KY_GO, BID_IMG0, $1000, MON_LOC, MON_SIZ, MON_DSKY) #endif -ra_ent(str_egg, 'E'+$80, $FF , bid_cur, $0E00, EGG_LOC, EGG_SIZ, EGG_LOC) .dw 0 ; table terminator ; ra_tbl_app: @@ -2068,7 +2089,6 @@ ra_ent(str_zsys, 'Z', KY_FW, bid_cur, $2000, CPM_LOC, CPM_SIZ, CPM_ENT) #if (DSKYENABLE) ra_ent(str_dsky, 'Y'+$80, KY_GO, bid_cur, $1000, MON_LOC, MON_SIZ, MON_DSKY) #endif -ra_ent(str_egg, 'E'+$80, $FF , bid_cur, $0E00, EGG_LOC, EGG_SIZ, EGG_LOC) .dw 0 ; table terminator ; str_mon .db "Monitor",0 diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index 8a082a07..2932a310 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -162,10 +162,10 @@ RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE ; #IF (SDMODE == SDMODE_PPI) ; PPISD SD_DEVMAX .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS) -SD_PPIBASE .EQU PPIBASE ; BASE IO PORT FOR PPI -SD_PPIB .EQU PPIBASE + 1 ; PPI PORT B (INPUT: DOUT) -SD_PPIC .EQU PPIBASE + 2 ; PPI PORT C (OUTPUT: CS, CLK, DIN) -SD_PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT +SD_PPIBASE .EQU SDPPIBASE ; BASE IO PORT FOR PPI +SD_PPIB .EQU SDPPIBASE + 1 ; PPI PORT B (INPUT: DOUT) +SD_PPIC .EQU SDPPIBASE + 2 ; PPI PORT C (OUTPUT: CS, CLK, DIN) +SD_PPIX .EQU SDPPIBASE + 3 ; PPI CONTROL PORT SD_OPRREG .EQU SD_PPIC ; PPI PORT C IS OPR REG SD_OPRDEF .EQU %00110001 ; CS HI, DI HI SD_INPREG .EQU SD_PPIB ; INPUT REGISTER IS PPI PORT B diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 595676a3..8fa32d99 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -55,7 +55,7 @@ PLT_EZZ80 .EQU 9 ; EASY Z80 PLT_SCZ180 .EQU 10 ; SCZ180 PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD PLT_RCZ280 .EQU 12 ; RC2014 W/ Z280 -; +PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER ; ; CPU TYPES ; @@ -141,6 +141,18 @@ CONBELL_NONE .EQU 0 CONBELL_PSG .EQU 1 CONBELL_IOBIT .EQU 2 ; +; LED MODE SELECTIONS +; +LEDMODE_NONE .EQU 0 +LEDMODE_STD .EQU 1 +LEDMODE_RTC .EQU 2 +; +; DSKY MODE SELECTIONS +; +DSKYMODE_NONE .EQU 0 +DSKYMODE_V1 .EQU 1 +DSKYMODE_NG .EQU 2 +; ; FD MODE SELECTIONS ; FDMODE_NONE .EQU 0 @@ -526,7 +538,7 @@ CBIOS_LOC .EQU CBIOS_END - CBIOS_SIZ ; START OF CBIOS CPM_ENT .EQU CBIOS_LOC ; CPM ENTRY POINT (IN CBIOS) -LDR_SIZ .EQU $0E00 +LDR_SIZ .EQU $1000 MON_LOC .EQU $F000 ; LOCATION OF MONITOR FOR RUNNING SYSTEM MON_SIZ .EQU $1000 - HBX_SIZ ; SIZE OF MONITOR BINARY IMAGE @@ -553,7 +565,7 @@ GAM_SIZ .EQU $0900 GAM_END .EQU GAM_LOC + GAM_SIZ USR_LOC .EQU $0200 ; USER -USR_SIZ .EQU $1000 +USR_SIZ .EQU $8000 - FTH_SIZ - BAS_SIZ - TBC_SIZ - GAM_SIZ - EGG_SIZ USR_END .EQU USR_LOC + USR_SIZ NET_LOC .EQU $0100 ; NETWORK BOOT diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm index 09345ed4..accad61e 100644 --- a/Source/HBIOS/tms.asm +++ b/Source/HBIOS/tms.asm @@ -637,6 +637,7 @@ TMS_PUTCHAR: CALL TMS_WR ; SET THE WRITE ADDRESS POP AF ; RECOVER CHARACTER TO WRITE OUT (TMS_DATREG),A ; WRITE THE CHARACTER + TMS_IODELAY LD HL,(TMS_POS) ; LOAD CURRENT POSITION INTO HL INC HL LD (TMS_POS),HL diff --git a/Source/ver.inc b/Source/ver.inc index 7094aff8..d74d870b 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,4 +2,4 @@ #DEFINE RMN 1 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "3.1.1-pre.83" +#DEFINE BIOSVER "3.1.1-pre.86" diff --git a/Source/ver.lib b/Source/ver.lib index 245126b1..9fd10d30 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 1 rup equ 1 rtp equ 0 biosver macro - db "3.1.1-pre.83" + db "3.1.1-pre.86" endm