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Minor Pre Int Strategy Change

Use a global flag to indicate if interrupts have been enabled during the boot process.  Drivers that operate in the pre-interrupt phase can use this to manage interrupt disable bracketing.

This allows restoring the location of interrupt enable in the boot process to it's proper location.
pull/573/head
Wayne Warthen 8 months ago
parent
commit
8510158aa0
No known key found for this signature in database GPG Key ID: 8B34ED29C07EEB0A
  1. 17
      Source/HBIOS/acia.asm
  2. 22
      Source/HBIOS/asci.asm
  3. 56
      Source/HBIOS/hbios.asm
  4. 10
      Source/HBIOS/lpt.asm
  5. 20
      Source/HBIOS/pio.asm
  6. 19
      Source/HBIOS/sio.asm
  7. 18
      Source/HBIOS/uart.asm
  8. 32
      Source/HBIOS/z2u.asm

17
Source/HBIOS/acia.asm

@ -123,10 +123,8 @@ ACIA_INITUNIT:
CALL ACIA_INITSAFE CALL ACIA_INITSAFE
; ;
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE
; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
JP ACIA_INITDEVX ; IMPLEMENT IT AND RETURN
LD DE,-1 ; LEAVE CONFIG ALONE
JP ACIA_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; ;
; ;
@ -366,15 +364,22 @@ ACIA_OST:
; ;
; ;
ACIA_INITDEV: ACIA_INITDEV:
; INITDEV CAN BE CALLED PRIOR TO INTERRUPTS BEING ENABLED. WE
; NEED TO LEAVE INTERRUPTS ALONE IN THIS SCENARIO
LD A,(INTSENAB) ; INTS ENABLED?
OR A ; TEST VALUE
JR Z,ACIA_INITDEV0 ; BYPASS DI/EI IF NOT ENABLED
;
; INTERRUPTS DISABLED DURING INIT
HB_DI ; AVOID CONFLICTS HB_DI ; AVOID CONFLICTS
CALL ACIA_INITDEVX ; DO THE REAL WORK
CALL ACIA_INITDEV0 ; DO THE REAL WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS! ; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS!
; ;
ACIA_INITDEVX:
ACIA_INITDEV0:
; ;
#IF (ACIADEBUG) #IF (ACIADEBUG)
CALL NEWLINE CALL NEWLINE

22
Source/HBIOS/asci.asm

@ -170,9 +170,7 @@ ASCI_INITUNIT:
; ;
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE LD DE,-1 ; LEAVE CONFIG ALONE
; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
; THE INITDEVX ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
JP ASCI_INITDEVX ; IMPLEMENT IT AND RETURN
JP ASCI_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; ;
; ;
@ -424,20 +422,20 @@ ASCI_OST:
; REQUIRED BY THE ASCI AND STORED IN A PORT/REGISTER INITIALIZATION TABLE, ; REQUIRED BY THE ASCI AND STORED IN A PORT/REGISTER INITIALIZATION TABLE,
; WHICH IS THEN LOADED INTO THE ASCI. ; WHICH IS THEN LOADED INTO THE ASCI.
; ;
; NOTE THAT THERE ARE TWO ENTRY POINTS. INITDEV WILL DISABLE/ENABLE INTS
; AND INITDEVX WILL NOT. THIS IS DONE SO THAT THE PREINIT ROUTINE ABOVE
; CAN AVOID ENABLING/DISABLING INTS.
;
ASCI_INITDEV: ASCI_INITDEV:
; INITDEV CAN BE CALLED PRIOR TO INTERRUPTS BEING ENABLED. WE
; NEED TO LEAVE INTERRUPTS ALONE IN THIS SCENARIO
LD A,(INTSENAB) ; INTS ENABLED?
OR A ; TEST VALUE
JR Z,ASCI_INITDEV0 ; BYPASS DI/EI IF NOT ENABLED
;
; INTERRUPTS DISABLED DURING INIT
HB_DI ; DISABLE INTS HB_DI ; DISABLE INTS
CALL ASCI_INITDEVX ; DO THE WORK
CALL ASCI_INITDEV0 ; DO THE WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
ASCI_INITDEVX:
;
; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS!
ASCI_INITDEV0:
; ;
; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT) ; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
LD A,D ; TEST DE FOR LD A,D ; TEST DE FOR

56
Source/HBIOS/hbios.asm

@ -1473,6 +1473,13 @@ HB_RESTART:
#IF (CPUFAM != CPU_EZ80) #IF (CPUFAM != CPU_EZ80)
IM 1 ; INTERRUPT MODE 1 IM 1 ; INTERRUPT MODE 1
#ENDIF #ENDIF
;
; IF WE ARE RESTARTING IN RAM, WE NEED TO RESET THE INTERRUPTS
; ENABLED FLAG. IF THIS IS A NORMAL ROM START, THIS DOES
; NOTHING AND THE FLAG IS RESET BY DEFAULT.
XOR A
LD (INTSENAB),A
;
; ;
#IFDEF APPBOOT #IFDEF APPBOOT
; ;
@ -2950,27 +2957,6 @@ NXTMIO: LD A,(HL)
; ;
#ENDIF #ENDIF
; ;
;--------------------------------------------------------------------------------------------------
; ENABLE INTERRUPTS
;--------------------------------------------------------------------------------------------------
;
#IFDEF TESTING
;
INTTEST:
; TEST TO SEE IF SOMEBODY ENABLED INTS EARLY!
LD A,I
JP PO,INTTEST_Z ; IF PO, INTS DISABLED AS EXPECTED
PRTX(STR_INTWARN) ; WARNING
JR INTTEST_Z ; CONTINUE
;
STR_INTWARN .TEXT "\r\n\r\nWARNING: INTERRUPTS ENABLED TOO EARLY!!!$"
;
INTTEST_Z:
;
#ENDIF
;
HB_EI ; INTERRUPTS SHOULD BE OK NOW
;
; PERFORM A RESET OPERATION ON ALL CHARACTER DEVICES THAT HAVE BEEN ; PERFORM A RESET OPERATION ON ALL CHARACTER DEVICES THAT HAVE BEEN
; INSTALLED. THIS SHOULD CORRECT ANY PROBLEMS IF A PROBE DESTROYED ; INSTALLED. THIS SHOULD CORRECT ANY PROBLEMS IF A PROBE DESTROYED
; THE PROGRAMMING OF ANOTHER DEVICE. ; THE PROGRAMMING OF ANOTHER DEVICE.
@ -3094,6 +3080,32 @@ HB_SPDTST:
#ENDIF #ENDIF
; ;
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------
; ENABLE INTERRUPTS
;--------------------------------------------------------------------------------------------------
;
#IFDEF TESTING
;
INTTEST:
; TEST TO SEE IF SOMEBODY ENABLED INTS EARLY!
LD A,I
JP PO,INTTEST_Z ; IF PO, INTS DISABLED AS EXPECTED
PRTX(STR_INTWARN) ; WARNING
JR INTTEST_Z ; CONTINUE
;
STR_INTWARN .TEXT "\r\n\r\nWARNING: INTERRUPTS ENABLED TOO EARLY!!!$"
;
INTTEST_Z:
;
#ENDIF
;
HB_EI ; INTERRUPTS SHOULD BE OK NOW
;
#IF (INTMODE != 0)
OR $FF ; TRUE
LD (INTSENAB),A ; SET INTERRUPTS ENABLED FLAG
#ENDIF
;
;--------------------------------------------------------------------------------------------------
; DISPLAY PLATFORM INFORMATION ; DISPLAY PLATFORM INFORMATION
;-------------------------------------------------------------------------------------------------- ;--------------------------------------------------------------------------------------------------
; ;
@ -9575,6 +9587,8 @@ HB_BATCOND .DB 0 ; BATTERY CONDITION (0=LOW, 1=OK)
; ;
RTCDEFVAL .DB RTCDEF ; STORAGE FOR RTC DEFAULT VALUE RTCDEFVAL .DB RTCDEF ; STORAGE FOR RTC DEFAULT VALUE
; ;
INTSENAB .DB 0 ; INTERRUPTS ENABLED
;
#IF (BT_REC_TYPE != BT_REC_NONE) #IF (BT_REC_TYPE != BT_REC_NONE)
HB_BOOT_REC .DB 0 ; BOOT MODE (0=NORMAL, 1=RECOVERY MODE) HB_BOOT_REC .DB 0 ; BOOT MODE (0=NORMAL, 1=RECOVERY MODE)
#ENDIF #ENDIF

10
Source/HBIOS/lpt.asm

@ -140,9 +140,7 @@ LPT_INITUNIT:
; ;
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE LD DE,-1 ; LEAVE CONFIG ALONE
; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
JP LPT_INITDEVX ; IMPLEMENT IT AND RETURN
JP LPT_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; DRIVER FUNCTION TABLE ; DRIVER FUNCTION TABLE
; ;
@ -240,15 +238,17 @@ LPT_OST:
; INITIALIZE DEVICE ; INITIALIZE DEVICE
; ;
LPT_INITDEV: LPT_INITDEV:
; INTERRUPTS DISABLED DURING INIT
; ??? IS THIS NEEDED?
HB_DI ; AVOID CONFLICTS HB_DI ; AVOID CONFLICTS
CALL LPT_INITDEVX ; DO THE REAL WORK
CALL LPT_INITDEV0 ; DO THE REAL WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS! ; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS!
; ;
LPT_INITDEVX:
LPT_INITDEV0:
; ;
#IF (LPTMODE == LPTMODE_SPP) #IF (LPTMODE == LPTMODE_SPP)
; ;

20
Source/HBIOS/pio.asm

@ -85,9 +85,7 @@ PIO_INITUNIT:
; ;
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE LD DE,-1 ; LEAVE CONFIG ALONE
; CALL INITDEVX TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
; THE INITDEVX ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
JP PIO_INITDEVX ; IMPLEMENT IT AND RETURN
JP PIO_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; ;
; ;
@ -146,17 +144,21 @@ PIO_OST:
XOR A ; NO BUFFER SPACE AVAIL XOR A ; NO BUFFER SPACE AVAIL
RET RET
; ;
; NOTE THAT THERE ARE TWO ENTRY POINTS. INITDEV WILL DISABLE/ENABLE INTS
; AND INITDEVX WILL NOT. THIS IS DONE SO THAT THE PREINIT ROUTINE ABOVE
; CAN AVOID ENABLING/DISABLING INTS.
;
PIO_INITDEV: PIO_INITDEV:
; INITDEV CAN BE CALLED PRIOR TO INTERRUPTS BEING ENABLED. WE
; NEED TO LEAVE INTERRUPTS ALONE IN THIS SCENARIO
LD A,(INTSENAB) ; INTS ENABLED?
OR A ; TEST VALUE
JR Z,PIO_INITDEV0 ; BYPASS DI/EI IF NOT ENABLED
;
; INTERRUPTS DISABLED DURING INIT
; ??? IS THIS NEEDED?
HB_DI ; DISABLE INTS HB_DI ; DISABLE INTS
CALL PIO_INITDEVX ; DO THE WORK
CALL PIO_INITDEV0 ; DO THE WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
PIO_INITDEVX:
PIO_INITDEV0:
; ;
; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS! ; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS!

19
Source/HBIOS/sio.asm

@ -199,9 +199,7 @@ SIO_INITUNIT:
; ;
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE LD DE,-1 ; LEAVE CONFIG ALONE
; CALL INITDEVX TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
; THE INITDEVX ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
JP SIO_INITDEVX ; IMPLEMENT IT AND RETURN
JP SIO_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; ;
; ;
@ -472,17 +470,20 @@ SIO_OST:
; MARK & SPACE PARITY AND 1.5 STOP BITS IS NOT SUPPORTED BY THE SIO. ; MARK & SPACE PARITY AND 1.5 STOP BITS IS NOT SUPPORTED BY THE SIO.
; INITIALIZATION WILL NOT BE COMPLETED IF AN INVALID SETTING IS DETECTED. ; INITIALIZATION WILL NOT BE COMPLETED IF AN INVALID SETTING IS DETECTED.
; ;
; NOTE THAT THERE ARE TWO ENTRY POINTS. INITDEV WILL DISABLE/ENABLE INTS
; AND INITDEVX WILL NOT. THIS IS DONE SO THAT THE PREINIT ROUTINE ABOVE
; CAN AVOID ENABLING/DISABLING INTS.
;
SIO_INITDEV: SIO_INITDEV:
; INITDEV CAN BE CALLED PRIOR TO INTERRUPTS BEING ENABLED. WE
; NEED TO LEAVE INTERRUPTS ALONE IN THIS SCENARIO
LD A,(INTSENAB) ; INTS ENABLED?
OR A ; TEST VALUE
JR Z,SIO_INITDEV0 ; BYPASS DI/EI IF NOT ENABLED
;
; INTERRUPTS DISABLED DURING INIT
HB_DI ; DISABLE INTS HB_DI ; DISABLE INTS
CALL SIO_INITDEVX ; DO THE WORK
CALL SIO_INITDEV0 ; DO THE WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
SIO_INITDEVX:
SIO_INITDEV0:
; ;
; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY ; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS! ; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS!

18
Source/HBIOS/uart.asm

@ -193,7 +193,7 @@ UART_INITUNIT:
UART_INITUNIT1: UART_INITUNIT1:
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE LD DE,-1 ; LEAVE CONFIG ALONE
JP UART_INITDEVX ; IMPLEMENT IT AND RETURN
JP UART_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; ;
; ;
@ -500,18 +500,20 @@ UART_OST:
; ;
; ;
; ;
;
; NOTE THAT THERE ARE TWO ENTRY POINTS. INITDEV WILL DISABLE/ENABLE INTS
; AND INITDEVX WILL NOT. THIS IS DONE SO THAT THE PREINIT ROUTINE ABOVE
; CAN AVOID ENABLING/DISABLING INTS.
;
UART_INITDEV: UART_INITDEV:
; INITDEV CAN BE CALLED PRIOR TO INTERRUPTS BEING ENABLED. WE
; NEED TO LEAVE INTERRUPTS ALONE IN THIS SCENARIO
LD A,(INTSENAB) ; INTS ENABLED?
OR A ; TEST VALUE
JR Z,UART_INITDEV0 ; BYPASS DI/EI IF NOT ENABLED
;
; INTERRUPTS DISABLED DURING INIT
HB_DI ; DISABLE INTS HB_DI ; DISABLE INTS
CALL UART_INITDEVX ; DO THE WORK
CALL UART_INITDEV0 ; DO THE WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
UART_INITDEVX:
UART_INITDEV0:
; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT) ; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
LD A,D ; TEST DE FOR LD A,D ; TEST DE FOR
AND E ; ... VALUE OF -1 AND E ; ... VALUE OF -1

32
Source/HBIOS/z2u.asm

@ -133,13 +133,14 @@ Z2U_INITUNIT:
; FAILSAFE CONFIG ONTO THE CHANNEL. IF THE SUBSEQUENT "REAL" ; FAILSAFE CONFIG ONTO THE CHANNEL. IF THE SUBSEQUENT "REAL"
; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT ; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT
; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG. ; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG.
CALL Z2U_INITSAFE
LD A,%11000010 ; 8N0, DIV 16, NO C/T
LD (Z2U_CFGREG),A ; SAVE IT
LD HL,1 ; C/T DIV 1
CALL Z2U_INITDEV8 ; DO IT
; ;
; SET DEFAULT CONFIG ; SET DEFAULT CONFIG
LD DE,-1 ; LEAVE CONFIG ALONE LD DE,-1 ; LEAVE CONFIG ALONE
; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
; THE INITDEVX ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
JP Z2U_INITDEVX ; IMPLEMENT IT AND RETURN
JP Z2U_INITDEV ; IMPLEMENT IT AND RETURN
; ;
; ;
; ;
@ -434,23 +435,20 @@ Z2U_OST:
; REQUIRED BY THE Z2U AND STORED IN A PORT/REGISTER INITIALIZATION TABLE, ; REQUIRED BY THE Z2U AND STORED IN A PORT/REGISTER INITIALIZATION TABLE,
; WHICH IS THEN LOADED INTO THE Z2U. ; WHICH IS THEN LOADED INTO THE Z2U.
; ;
; NOTE THAT THERE ARE TWO ENTRY POINTS. INITDEV WILL DISABLE/ENABLE INTS
; AND INITDEVX WILL NOT. THIS IS DONE SO THAT THE PREINIT ROUTINE ABOVE
; CAN AVOID ENABLING/DISABLING INTS.
;
Z2U_INITDEV: Z2U_INITDEV:
; INITDEV CAN BE CALLED PRIOR TO INTERRUPTS BEING ENABLED. WE
; NEED TO LEAVE INTERRUPTS ALONE IN THIS SCENARIO
LD A,(INTSENAB) ; INTS ENABLED?
OR A ; TEST VALUE
JR Z,Z2U_INITDEV0 ; BYPASS DI/EI IF NOT ENABLED
;
; INTERRUPTS DISABLED DURING INIT
HB_DI ; DISABLE INTS HB_DI ; DISABLE INTS
CALL Z2U_INITDEVX ; DO THE WORK
CALL Z2U_INITDEV0 ; DO THE WORK
HB_EI ; INTS BACK ON HB_EI ; INTS BACK ON
RET ; DONE RET ; DONE
; ;
Z2U_INITSAFE:
LD A,%11000010 ; 8N0, DIV 16, NO C/T
LD (Z2U_CFGREG),A ; SAVE IT
LD HL,1 ; C/T DIV 1
JR Z2U_INITDEV8 ; DO IT
;
Z2U_INITDEVX:
Z2U_INITDEV0:
; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT) ; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
LD A,D ; TEST DE FOR LD A,D ; TEST DE FOR
AND E ; ... VALUE OF -1 AND E ; ... VALUE OF -1
@ -535,7 +533,7 @@ Z2U_INITDEV2:
LD (IY+4),E ; SAVE LOW WORD LD (IY+4),E ; SAVE LOW WORD
LD (IY+5),D ; SAVE HI WORD LD (IY+5),D ; SAVE HI WORD
; ;
Z2U_INITDEV8:
Z2U_INITDEV8: ; THIS LABEL IS USED IN INITUNIT!!!
; START BY SELECTING I/O PAGE $FE ; START BY SELECTING I/O PAGE $FE
PUSH HL ; SAVE HL PUSH HL ; SAVE HL
LD L,$FE ; Z280 UART REGISTERS AT I/O PAGE $FE LD L,$FE ; Z280 UART REGISTERS AT I/O PAGE $FE

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