From 872d51e9b6dda7c2b036edccea8fdbbc6f8c4c9f Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Tue, 10 Oct 2023 14:09:21 -0700 Subject: [PATCH] Detect CTS Stall - Detect CTS at startup to ensure it is asserted. If not, disable hardware flow control to avoid stalling the console at boot. Only for UART driver because this is the only place it is currently relevant. --- Source/HBIOS/Config/DUO_std.asm | 1 - Source/HBIOS/Config/DYNO_std.asm | 2 -- Source/HBIOS/Config/MBC_std.asm | 1 - Source/HBIOS/Config/ZETA2_std.asm | 1 - Source/HBIOS/Config/ZETA_std.asm | 1 - Source/HBIOS/cfg_duo.asm | 2 +- Source/HBIOS/cfg_dyno.asm | 2 +- Source/HBIOS/cfg_heath.asm | 2 +- Source/HBIOS/cfg_master.asm | 2 +- Source/HBIOS/cfg_mbc.asm | 2 +- Source/HBIOS/cfg_mk4.asm | 2 +- Source/HBIOS/cfg_n8.asm | 2 +- Source/HBIOS/cfg_rcz180.asm | 2 +- Source/HBIOS/cfg_rcz280.asm | 2 +- Source/HBIOS/cfg_rcz80.asm | 2 +- Source/HBIOS/cfg_rph.asm | 2 +- Source/HBIOS/cfg_s100.asm | 2 +- Source/HBIOS/cfg_sbc.asm | 2 +- Source/HBIOS/cfg_scz180.asm | 2 +- Source/HBIOS/cfg_z80retro.asm | 2 +- Source/HBIOS/cfg_zeta.asm | 2 +- Source/HBIOS/cfg_zeta2.asm | 2 +- Source/HBIOS/hbios.asm | 33 ------------------------------- Source/HBIOS/uart.asm | 32 ++++++++++++++++++++++++++++-- Source/ver.inc | 2 +- Source/ver.lib | 2 +- 26 files changed, 49 insertions(+), 60 deletions(-) diff --git a/Source/HBIOS/Config/DUO_std.asm b/Source/HBIOS/Config/DUO_std.asm index b948a65e..855735ea 100644 --- a/Source/HBIOS/Config/DUO_std.asm +++ b/Source/HBIOS/Config/DUO_std.asm @@ -43,6 +43,5 @@ PCFENABLE .SET TRUE ; ENABLE PCF8584 I2C CONTROLLER MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM ; UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -;UARTCFG .SET UARTCFG | SER_RTS ; ESPENABLE .SET TRUE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) diff --git a/Source/HBIOS/Config/DYNO_std.asm b/Source/HBIOS/Config/DYNO_std.asm index 176b9786..bc4b677d 100644 --- a/Source/HBIOS/Config/DYNO_std.asm +++ b/Source/HBIOS/Config/DYNO_std.asm @@ -34,8 +34,6 @@ Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG -;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) ; diff --git a/Source/HBIOS/Config/MBC_std.asm b/Source/HBIOS/Config/MBC_std.asm index bc7ede06..9ae980c8 100644 --- a/Source/HBIOS/Config/MBC_std.asm +++ b/Source/HBIOS/Config/MBC_std.asm @@ -47,7 +47,6 @@ ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259) ; UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -;UARTCFG .SET UARTCFG | SER_RTS ; ESPENABLE .SET TRUE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) ; diff --git a/Source/HBIOS/Config/ZETA2_std.asm b/Source/HBIOS/Config/ZETA2_std.asm index a3473e40..0245bfd5 100644 --- a/Source/HBIOS/Config/ZETA2_std.asm +++ b/Source/HBIOS/Config/ZETA2_std.asm @@ -31,7 +31,6 @@ INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -;UARTCFG .SET UARTCFG | SER_RTS UARTSBC .SET TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) diff --git a/Source/HBIOS/Config/ZETA_std.asm b/Source/HBIOS/Config/ZETA_std.asm index 38046ff8..da5515ce 100644 --- a/Source/HBIOS/Config/ZETA_std.asm +++ b/Source/HBIOS/Config/ZETA_std.asm @@ -31,7 +31,6 @@ INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -;UARTCFG .SET UARTCFG | SER_RTS UARTSBC .SET TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm index 9e4d8212..3a552f66 100644 --- a/Source/HBIOS/cfg_duo.asm +++ b/Source/HBIOS/cfg_duo.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_UNSUP ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index a33bbec4..56cfffa5 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm index 4f8d45c4..77335229 100644 --- a/Source/HBIOS/cfg_heath.asm +++ b/Source/HBIOS/cfg_heath.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 42dc91f8..1f8c70fa 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -27,7 +27,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm index 8c1fb1b4..b67b1d39 100644 --- a/Source/HBIOS/cfg_mbc.asm +++ b/Source/HBIOS/cfg_mbc.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_HILO ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index fdee2561..0e174fcb 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index dcfc9bdc..80d3e1a0 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index 80646606..bfcb305b 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm index 83284879..5e1399e1 100644 --- a/Source/HBIOS/cfg_rcz280.asm +++ b/Source/HBIOS/cfg_rcz280.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 12000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 6f1ef132..dac63190 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_rph.asm b/Source/HBIOS/cfg_rph.asm index 1e00a9c2..bae33dd2 100644 --- a/Source/HBIOS/cfg_rph.asm +++ b/Source/HBIOS/cfg_rph.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm index 967959e3..7e999a30 100644 --- a/Source/HBIOS/cfg_s100.asm +++ b/Source/HBIOS/cfg_s100.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_57600_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index 60e2aa21..23185ce6 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 0bedc8bc..faab26af 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm index f83f6be4..d7264eef 100644 --- a/Source/HBIOS/cfg_z80retro.asm +++ b/Source/HBIOS/cfg_z80retro.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 14745600 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index 0191ea37..4fee5070 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 20000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index 0a040380..00eebcde 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -30,7 +30,7 @@ CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index f681a456..eec6160a 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -2302,29 +2302,6 @@ HB_BOOTDLY: LD (CB_CONDEV),A ; SAVE IT HB_CONRDY: ; -; MOST SERIAL PORTS ARE CONFIGURED WITH HARDWARE FLOW CONTROL ENABLED. -; IF THERE IS A PROBLEM WITH THE RTS SIGNAL, THEN OUTPUT TO THE CONSOLE -; WILL BE STALLED WHICH CAN LEAD A USER TO THINK THE SYSTEM IS TOTALLY -; DEAD WHEN, IN FACT, IT IS JUST WAITING FOR RTS TO BE ASSERTED. ALSO, -; IF THE USER IS BOOTING TO A CRT DEVICE AND DISCONNECTS THE CONSOLE -; SERIAL PORT, THE SYSTEM WILL WAIT FOR RTS AND NEVER BOOT. SO, HERE -; WE SAVE THE ACTIVE CONSOLE CONFIGURATION, THEN TURN OFF HARDWARE -; FLOW CONTROL. THE ORIGINAL CONFIGURATION WILL BE RESTORED BELOW -; PRIOR TO LAUNCING THE ROM LOADER. -; - ; RETRIEVE THE CONFIG FROM THE CONSOLE PORT - LD B,BF_CIOQUERY ; HBIOS QUERY CIO CONFIG - LD A,(CB_CONDEV) ; GET CONSOLE DEVICE - LD (HB_BOOTCON),A ; SAVE IT FOR LATER - LD C,A ; BOOT CONSOLE TO C - CALL HB_DISPATCH ; INTERNAL HBIOS CALL - LD (HB_BOOTCFG),DE ; SAVE CONFIG - RES 5,D ; CLEAR RTS BIT - LD B,BF_CIOINIT ; HBIOS CIO INIT - LD A,(CB_CONDEV) ; GET CONSOLE DEVICE - LD C,A ; BOOT CONSOLE TO C - CALL HB_DISPATCH ; INTERNAL HBIOS CALL - #IF (WBWDEBUG == USEMIO) ; OUTPUT ANY CACHED DEBUG TEXT LD HL,MIOOUTPTR LD E,(HL) @@ -2891,16 +2868,6 @@ INITSYS3: CALL NZ,WRITESTR ; OUTPUT IF CONSOLE MOVED ; INITSYS3A: -; -; RESTORE BOOT CONSOLE CONFIGURATION -; - CALL LDELAY ; ALLOW SERIAL PORT TO FLUSH - LD B,BF_CIOINIT ; HBIOS CIO INIT - LD A,(HB_BOOTCON) ; ORIGINAL BOOT CONSOLE DEVICE - LD C,A ; BOOT CONSOLE TO C - LD DE,(HB_BOOTCFG) ; SAVED ORIGINAL CONSOLE CFG - CALL HB_DISPATCH ; INTERNAL HBIOS CALL -; CALL PRTSUM ; PRINT UNIT/DEVICE SUMMARY TABLE ; #IF 0 diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm index 5deff4ac..c8eaf42a 100644 --- a/Source/HBIOS/uart.asm +++ b/Source/HBIOS/uart.asm @@ -52,6 +52,7 @@ UART_EFR .EQU 2 ; LCR=$BF: ENHANCED FEATURE REG (READ/WRITE) UART_INTACT .EQU 7 ; INT RCV ACTIVE BIT UART_FIFOACT .EQU 6 ; FIFO ACTIVE BIT UART_AFCACT .EQU 5 ; AUTO FLOW CONTROL ACTIVE BIT +UART_CTSBAD .EQU 4 ; CTS STALL DETECTED ; #IF (PLATFORM == PLT_DUO) UARTSBASE .EQU $58 @@ -173,7 +174,19 @@ UART_INITUNIT: LD A,(HL) ; PUT IN ACCUM INC (HL) ; INCREMENT IT (FOR NEXT LOOP) LD (IY),A ; UDPATE UNIT NUM +; + ; CHECK FOR CTS STALL (CTS SHOULD BE ASSERTED HERE) + BIT 5,(IY+5) ; IS RTS REQUESTED? + JR Z,UART_INITUNIT1 ; IF NOT, SKIP CTS CHECK + UART_INP(UART_MSR) ; LOAD MODEM STATUS REG + BIT 4,A ; CTS + JR NZ,UART_INITUNIT1 ; IF CTS HIGH (GOOD), SKIP AHEAD +; + ; CTS LOOKS BORKED, SHUT OFF RTS/CTS FLOW CONTROL + RES 5,(IY+5) ; CLEAR RTS BIT OF CONFIG MSB + SET UART_CTSBAD,(IY+1) ; RECORD BAD CTS ; +UART_INITUNIT1: ; SET DEFAULT CONFIG LD DE,-1 ; LEAVE CONFIG ALONE JP UART_INITDEVX ; IMPLEMENT IT AND RETURN @@ -197,8 +210,21 @@ UART_INIT1: LD A,(IY+1) ; GET UART TYPE OR A ; SET FLAGS - CALL NZ,UART_PRTCFG ; PRINT IF NOT ZERO - + JR Z,UART_INIT2 ; SKIP IF ZERO (NOT DETECTED) + PUSH AF ; SAVE TYPE VALUE + CALL UART_PRTCFG ; PRINT IF NOT ZERO + POP AF ; RESTORE TYPE VALUE + BIT UART_CTSBAD,A ; CTS STALL? + JR Z,UART_INIT2 ; IF NOT, SKIP AHEAD + CALL NEWLINE ; FORMATTING + PRTS("UART$") ; FORMATTING + LD A,(IY) ; DEVICE NUM + CALL PRTDECB ; PRINT DEVICE NUM + PRTS(": $") ; FORMATTING + LD DE,UART_STR_BADCTS ; LOAD WARNING MESSAGE + CALL WRITESTR ; ... AND PRINT IT +; +UART_INIT2: POP BC ; RESTORE LOOP CONTROL INC C ; NEXT UNIT DJNZ UART_INIT1 ; LOOP TILL DONE @@ -992,6 +1018,8 @@ UART_STR_16850 .DB "16850$" ; UART_PAR_MAP .DB "NONENMNS" ; +UART_STR_BADCTS .DB "CTS STALL, HARDWARE FLOW CONTROL SUSPENDED$" +; ; WORKING VARIABLES ; UART_DEV .DB 0 ; DEVICE NUM USED DURING INIT diff --git a/Source/ver.inc b/Source/ver.inc index 47e64d1c..801a7216 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 4 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.4.0-dev.5" +#DEFINE BIOSVER "3.4.0-dev.6" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index b124f9b1..03c673ed 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 4 rup equ 0 rtp equ 0 biosver macro - db "3.4.0-dev.5" + db "3.4.0-dev.6" endm