From 8945580ff5cdc503322e1ab41706707f132e1df7 Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sat, 30 Jan 2021 16:17:34 -0800
Subject: [PATCH] Z280 Cleanup

- Z280 UART MODE command support
- BNKCALL handles calls into HBIOS using system mode
---
 Doc/ChangeLog.txt           |  2 +-
 Source/HBIOS/cfg_master.asm |  1 +
 Source/HBIOS/cfg_rcz280.asm |  1 +
 Source/HBIOS/hbios.asm      | 59 +++++++++++--------------------------
 Source/HBIOS/z2u.asm        | 36 ++++++++++++++++++++--
 Source/ver.inc              |  2 +-
 Source/ver.lib              |  2 +-
 7 files changed, 56 insertions(+), 47 deletions(-)

diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt
index a65e6837..bab6a99f 100644
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -15,7 +15,7 @@ Version 3.1.1
 - PMS: Creation of process to update ROM system area w/o updating ROM disk contents
 - PMS: Added "updater.asm" which allows uploading and updating ROM in one step
 - WBW: Support for Z280 w/ native memory and interrupt mode 3
-- WBW: Support for Z280 UART (only for interrupt mode 3)
+- WBW: Support for Z280 UART (interrupt driven only in interrupt mode 3)
 
 Version 3.1
 -----------
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index b50d2843..fd2f474e 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -130,6 +130,7 @@ ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
 ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
 Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UOSC		.EQU	1843200		; Z2U:  OSC FREQUENCY IN MHZ
 Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
 Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
 ;
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 42b28a98..c8cfc087 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -103,6 +103,7 @@ UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
 Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UOSC		.EQU	1843200		; Z2U:  OSC FREQUENCY IN MHZ
 Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
 Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
 ;
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 41c1319b..2c15b811 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -588,54 +588,29 @@ HBX_BC_ITER:
 HBX_BNKCALL:
 ;
 #IF (MEMMGR == MM_Z280)
-	JR	HBX_BNKCALL2
-
 	CP	BID_BIOS		; CALLING HBIOS?
-	JR	NZ,HBX_BNKCALL2		; NOPE, DO NORMAL PROCESSING
-	
-	;PUSH	AF
-	;LD	A,'['
-	;.DB	$ED,$71			; SC
-	;.DW	COUT			; SC PARAMETER
-	;POP	AF
-	
-	;
-	;LD	A,(HB_CURBNK)		; GET CURRENT BANK
-	;LD	(HB_INVBNK),A		; SAVE INVOCATION BANK
-	;
-	;LD	A,BID_BIOS		; HBIOS BANK
-	;LD	(HB_CURBNK),A		; SET AS CURRENT BANK
-
-	LD	(HBX_BNKCALL1+2),IX	; SETUP TARGET ADDRESS
-HBX_BNKCALL1:
+	JR	NZ,HBX_BNKCALL3		; NOPE, DO NORMAL PROCESSING
 	.DB	$ED,$71			; SC
-	.DW	$FFFF			; SC PARAMETER (SET ABOVE)
-	
-	;PUSH	AF
-	;LD	A,']'
-	;.DB	$ED,$71			; SC
-	;.DW	COUT			; SC PARAMETER
-	;POP	AF
-	
-	;PUSH	AF
-	;LD	A,(HB_INVBNK)
-	;LD	(HB_CURBNK),A
-	;POP	AF
-	
-	
-	
-	RET
-#ENDIF
+	.DW	HBX_BNKCALL2		; CALL HERE IN SYSTEM MODE
+	RET				; THEN RETURN
 
 HBX_BNKCALL2:
-	LD	(HBX_TGTBNK),A		; STUFF TARGET BANK TO CALL INTO CODE BELOW
-	LD	(HBX_TGTADR),IX		; STUFF ADDRESS TO CALL INTO CODE BELOW
+	HB_EI				; INTS ARE OK
+	LD	(HBX_BNKCALL_GO+1),IX	; SETUP DEST ADR
+	.DB	$ED,$65			; PCACHE (CRITICAL!!!)
+HBX_BNKCALL_GO:
+	JP	$FFFF			; DO THE REAL WORK AND RETURN
+#ENDIF
+
+HBX_BNKCALL3:
+	LD	(HBX_BNKCALL_BNK+1),A	; STUFF TARGET BANK TO CALL INTO CODE BELOW
+	LD	(HBX_BNKCALL_ADR+1),IX	; STUFF ADDRESS TO CALL INTO CODE BELOW
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	PUSH	AF			; SAVE FOR RETURN
-HBX_TGTBNK	.EQU	$ + 1
+HBX_BNKCALL_BNK:
 	LD	A,$FF			; LOAD BANK TO CALL ($FF OVERLAID AT ENTRY)
 	CALL	HBX_BNKSEL		; ACTIVATE THE NEW BANK
-HBX_TGTADR	.EQU	$ + 1
+HBX_BNKCALL_ADR:
 	CALL	$FFFF			; CALL ROUTINE ($FFFF IS OVERLAID ABOVE)
 	EX	(SP),HL			; SAVE HL AND GET BANK TO RESTORE IN HL
 	PUSH	AF			; SAVE AF
@@ -4390,7 +4365,7 @@ W_MMU1:
 	.DB	$ED,$BF			; OUTW (C),HL        
 W_MMU2:        
 	;.DB    $ED,$65			; PCACHE
-	LD	L,0                     ; RESTORE I/O PAGE REG TO 0
+	LD	L,$00                   ; RESTORE I/O PAGE REG TO 0
 	LD	C,Z280_IOPR
 	.DB	$ED,$6E			; LDCTL (C),HL
 	POP	BC
@@ -4450,7 +4425,7 @@ Z2DMALOOP:
 	JR	NZ,Z2DMALOOP		; LOOP WHILE ACTIVE
 
 	; RETURN TO I/O PAGE $00
-	XOR	A			; I/O PAGE ZERO
+	LD	L,$00                   ; RESTORE I/O PAGE REG TO 0
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
 	.DB	$ED,$6E			; LDCTL (C),HL
 
diff --git a/Source/HBIOS/z2u.asm b/Source/HBIOS/z2u.asm
index ef3644b9..6d8199b1 100644
--- a/Source/HBIOS/z2u.asm
+++ b/Source/HBIOS/z2u.asm
@@ -410,21 +410,53 @@ Z2U_OST:
 ; CAN AVOID ENABLING/DISABLING INTS.
 ;
 Z2U_INITDEV:
-Z2U_INITSAFE:
 	HB_DI				; DISABLE INTS
 	CALL	Z2U_INITDEVX		; DO THE WORK
 	HB_EI				; INTS BACK ON
 	RET				; DONE
 ;
+Z2U_INITSAFE:
+	LD	E,%11000010		; 8N0, DIV 16, NO C/T
+	JR	Z2U_INITDEV2		; YES, DO IT
+;
 Z2U_INITDEVX:
 ;
+	LD	A,D			; HIWORD OF CONFIG
+	AND	$1F			; ISOLATE BAUD RATE
+	PUSH	AF
+;
+	LD	DE,Z2UOSC >> 16		; BAUD OSC HI WORD
+	LD	HL,Z2UOSC & $FFFF	; BAUD OSC LO WORD
+	LD	C,75			; BAUD RATE ENCODE CONSTANT
+	CALL	ENCODE			; C = ENCODED OSC
+	POP	DE			; D = UART OSC
+	JR	NZ,Z2U_INITFAIL		; HANDLE ENCODE FAILURE
+	LD	A,C			; TO A
+	SUB	D			; DIV W/ SUB OF SQUARES
+;
+	LD	E,%11000010		; 8N0, DIV 16, NO C/T
+	CP	4			; DIV 16?
+	JR	Z,Z2U_INITDEV2		; YES, DO IT
+	LD	E,%11000100		; 8N0, DIV 32, NO C/T
+	CP	5			; DIV 32?
+	JR	Z,Z2U_INITDEV2		; YES, DO IT
+	LD	E,%11000110		; 8N0, DIV 64, NO C/T
+	CP	6			; DIV 64?
+	JR	Z,Z2U_INITDEV2		; YES, DO IT
+;
+Z2U_INITFAIL:
+	OR	$FF			; SIGNAL ERROR
+	RET				; AND DONE
+;
+Z2U_INITDEV2:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	.DB	$ED,$6E			; LDCTL	(C),HL
 ;
 	; SETUP
-	LD	A,%11000010		; 8N0, DIV 16, NO C/T
+	;LD	A,%11000010		; 8N0, DIV 16, NO C/T
+	LD	A,E			; CONFIG VALUE
 	OUT	(Z280_UARTCFG),A	; SET CONFIG REGISTER
 	LD	A,%10000000		; ENABLE, NO INTS, 1 STOP BITS
 	OUT	(Z280_UARTXCTL),A	; SET CONFIG REGISTER
diff --git a/Source/ver.inc b/Source/ver.inc
index 905accbf..708cbf23 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.35"
+#DEFINE BIOSVER	"3.1.1-pre.36"
diff --git a/Source/ver.lib b/Source/ver.lib
index 90f1a10f..a71f2b66 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.35"
+	db	"3.1.1-pre.36"
 	endm