Resync

Source/HBIOS/plt_sbc.inc

@@ -20,4 +20,7 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
 PIOZBASE	.EQU	$88		; ZILOG PERIPHERALS DEFAULT PIO DEFAULT
-PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
+PIO4BASE	.EQU	$90		; ECB-4PIO  DEFAULT PIO DEFAULT
+;
+;
+FIFO_BASE       .EQU	$0C		; ECB USB-FIFO DEFAULT PORT

Source/HBIOS/std.asm

@@ -269,6 +269,14 @@ IVT_PIO3	.EQU	24
 IVT_SER2	.EQU	26
 IVT_SER3	.EQU	28
 ;
+;
+; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
+; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
+; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE, 
+; SET FORCECON TO 2 IN YOUR CUSTOM CONFIGURATION FILE i.e. "FORCECON: .SET 2"
+;
+FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
+;
 #INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
 ;
 #IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))