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https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
SIO driver now CTC aware
The SIO driver can now use a CTC (if available) to provide much more flexible baud rate programming.
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@@ -121,24 +121,22 @@ ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
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SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
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SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
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SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
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SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
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SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
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SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
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SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
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SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
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SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
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SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
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SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80]
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SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
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SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
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SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
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SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
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SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
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SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
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SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
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SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
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SIO1BDIV .EQU 1 ; SIO 1B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5)
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SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
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SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE
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;
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XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
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;
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