From 8b7e71049b790ac7aca654d8bdaa139ff9d39168 Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Fri, 25 Aug 2023 10:25:07 -0700
Subject: [PATCH] FDC Detection Update & Enable ESP Driver on Duodyne

- Based on reports from Martin R, the FDC detection algorithm has been updated to try reading the FDC MSR register twice to try and get the desired value of 0x80.
- Dan Werner's ESP board for Duodyne is working well, so the default Duodyne config has been changed to automatically detect this board.
---
 Source/Apps/FDU/fdu.doc         |  3 ++-
 Source/HBIOS/Config/DUO_std.asm |  2 ++
 Source/HBIOS/cfg_duo.asm        |  1 +
 Source/HBIOS/fd.asm             | 30 ++++++++++++++++++------------
 Source/ver.inc                  |  2 +-
 Source/ver.lib                  |  2 +-
 6 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/Source/Apps/FDU/fdu.doc b/Source/Apps/FDU/fdu.doc
index 13c14708..8ee61e1e 100644
--- a/Source/Apps/FDU/fdu.doc
+++ b/Source/Apps/FDU/fdu.doc
@@ -153,7 +153,8 @@ JP2 (/FAULT) shorted, JP3 (MINI): 2-3, JP4 (/DC/RDY): 2-3.
 
 The RCBus Scott Baker WDC-based floppy module should be jumpered
 for I/O base address 0x50 (SV1: 11-12), JP1 (/DACK): 1-2,
-JP2 (TC): 2-3.
+JP2 (TC): 2-3.  Note that pin 1 of JPX jumpers is toward the bottom
+of the board.
 
 The RCBus FDC by Alan Cox (Etched Pixels) needs to be strapped
 for base I/O address 0x48.
diff --git a/Source/HBIOS/Config/DUO_std.asm b/Source/HBIOS/Config/DUO_std.asm
index c66ff54e..b948a65e 100644
--- a/Source/HBIOS/Config/DUO_std.asm
+++ b/Source/HBIOS/Config/DUO_std.asm
@@ -44,3 +44,5 @@ MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 ;UARTCFG	.SET	UARTCFG | SER_RTS
+;
+ESPENABLE	.SET	TRUE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm
index 43849289..a454bac0 100644
--- a/Source/HBIOS/cfg_duo.asm
+++ b/Source/HBIOS/cfg_duo.asm
@@ -236,6 +236,7 @@ PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
 ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 ;
 HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
diff --git a/Source/HBIOS/fd.asm b/Source/HBIOS/fd.asm
index a79aa8d3..84933714 100644
--- a/Source/HBIOS/fd.asm
+++ b/Source/HBIOS/fd.asm
@@ -811,21 +811,27 @@ FD_DETECT:
 	IN	A,(FDC_MSR)	; READ MSR
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-	CP	$80
-	JR	Z,FD_DETECT1	; $80 IS OK
-	CP	$D0
-	JR	Z,FD_DETECT1	; $D0 IS OK
-	RET			; NOPE, ABORT WITH ZF=NZ
-;
+	
+	CP	$D0		; SPECIAL CASE: DATA PENDING?
+	JR	NZ,FD_DETECT1	; NOPE, MOVE ALONG
+	IN	A,(FDC_DATA)	; SWALLOW THE PENDING DATA
+	CALL	DLY32		; SETTLE
+	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
+	;CALL	PC_SPACE	; *DEBUG*
+	;CALL	PRTHEXBYTE	; *DEBUG*
+
 FD_DETECT1:
-	;CALL	DLY32		; WAIT A BIT FOR FDC
-	LD	DE,150		; DELAY: 16us * 150 = 2.4ms
-	CALL	VDELAY
-	IN	A,(FDC_MSR)	; READ MSR AGAIN
+	CP	$80		; WE EXPECT $80
+	RET	Z		; IF SO, ALL DONE
+
+	; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET
+	; DESIRED VALUE, SO TRY ONE MORE TIME
+	CALL	DLY32		; WAIT A BIT
+	IN	A,(FDC_MSR)	; ... AND REREAD THE STATUS
 	;CALL	PC_SPACE	; *DEBUG*
 	;CALL	PRTHEXBYTE	; *DEBUG*
-	CP	$80
-	RET			; $80 OK, ELSE NOT PRESENT
+	CP	$80		; CHECK FOR CORRECT VALUE
+	RET			; RETURN WITH ZF ACCORDING TO RESULT
 ;
 ; UNIT INITIALIZATION
 ;
diff --git a/Source/ver.inc b/Source/ver.inc
index 90fd4b8b..a1fa97f8 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	3
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.3.0-dev.47"
+#DEFINE BIOSVER	"3.3.0-dev.48"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
diff --git a/Source/ver.lib b/Source/ver.lib
index f0a0175b..587ec931 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	3
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.3.0-dev.47"
+	db	"3.3.0-dev.48"
 	endm