Additional SK Z80-512K Support

- Added support for UART clock divider (CLK2).
2026-02-06 14:11:48 -06:00 · 2021-02-11 14:28:26 -08:00
parent 4791d5f040
commit 8e7e9039f9
17 changed files with 95 additions and 11 deletions
--- a/Source/HBIOS/Config/RCZ80_skz.asm
+++ b/Source/HBIOS/Config/RCZ80_skz.asm
@@ -31,4 +31,10 @@
 LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
 LEDPORT		.SET	$6E		; STATUS LED PORT ADDRESS
 ;
+SKZENABLE	.SET	TRUE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_12		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
 WDOGMODE	.SET	WDOG_SKZ	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
+SIO0BCLK	.SET	CPUOSC / 12	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_38400_8N1	; SIO 0B: SERIAL LINE CONFIG
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -50,6 +50,8 @@ CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -52,6 +52,8 @@ CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -74,6 +74,9 @@ CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -53,6 +53,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -56,6 +56,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -53,6 +53,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -56,6 +56,8 @@ CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -52,6 +52,9 @@ CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
 ;
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -50,6 +50,8 @@ CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -48,6 +48,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -42,6 +42,8 @@ CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -53,6 +53,8 @@ CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+;
 WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -96,7 +96,7 @@ MODCNT	.SET	MODCNT + 1
 #DEFINE	DIAG(N)	\;
 #ENDIF
 ;
-#IF (LEDENABLE)
+#IF (LEDENABLE) & FALSE
 #DEFINE	LED(N)	PUSH AF
  #DEFCONT \	LD A,~N
  #DEFCONT \	OUT (LEDPORT),A
@@ -1424,6 +1424,17 @@ HB_CPU1:
 	CALL	DSRTC_PREINIT
 #ENDIF
 ;
+#IF (SKZENABLE)
+;
+	; SET THE SK Z80-512K UART CLK2 DIVIDER AS
+	; CONFIGURED.  NOTE THAT THIS IMPLICITLY
+	; CLEARS THE WATCHDOG BIT.  THE WATCHDOG
+	; WILL BE ENABLED LATER IF CONFIGURED.
+	LD	A,SKZDIV	; GET DIVIDER CODE
+	OUT	($6D),A		; IMPLEMENT IT
+;
+#ENDIF
+;
 #IF (CPUFAM == CPU_Z180)
 ;
 	; AT BOOT, Z180 PHI IS OSC / 2
@@ -1971,21 +1982,26 @@ IS_REC_M1:
  #IF (WDOGMODE == WDOG_EZZ80)
 	PRTS("EZZ80$")
  #ENDIF
-;
  #IF (WDOGMODE == WDOG_SKZ)
 	PRTS("SKZ$")
-	LD	HL,(HB_TICKS)		; GET LOW WORD
-	LD	A,H			; CHECK FOR
-	OR	L			; ... ZERO
-	JR	Z,HB_WDOFF		; SKIP IF NOT TICKING
-	IN	A,($6D)			; GET PORT VALUE
-	SET	5,A			; SET WDOG ENABLE BIT
-	OUT	($6D),A			; DO IT
  #ENDIF
 ;
 	PRTS(" IO=0x$")
 	LD	A,WDOGIO
 	CALL	PRTHEXBYTE
+;
+  #IF (WDOGMODE == WDOG_SKZ)
+	; SKZ WATCHDOG IS DISABLED EARLY IN BOOT PROCESS
+	; HERE, WE ONLY NEED TO ENABLE IT, IF APPROPRIATE
+	LD	HL,(HB_TICKS)		; GET LOW WORD
+	LD	A,H			; CHECK FOR
+	OR	L			; ... ZERO
+	JR	Z,HB_WDOFF		; SKIP IF NOT TICKING
+	IN	A,($6D)			; GET PORT VALUE
+	SET	5,A			; SET THE WATCHDOG ENABLE BIT
+	OUT	($6D),A			; ACTIVATE WATCHDOG
+  #ENDIF
+;
 	PRTS(" ENABLED$")
 	JR	HB_WDZ
 ;
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -246,6 +246,42 @@ SER_BAUD1843200	.EQU	$1D << 8
 SER_BAUD3686400	.EQU	$1E << 8
 SER_BAUD7372800	.EQU	$1F << 8
 ;
+; UART DIVIDER VALUES
+; STORED AS 5 BITS: YXXXX
+;
+DIV_1		.EQU	$00
+DIV_2		.EQU	$01
+DIV_4		.EQU	$02
+DIV_8		.EQU	$03
+DIV_16		.EQU	$04
+DIV_32		.EQU	$05
+DIV_64		.EQU	$06
+DIV_128		.EQU	$07
+DIV_256		.EQU	$08
+DIV_512		.EQU	$09
+DIV_1024	.EQU	$0A
+DIV_2048	.EQU	$0B
+DIV_4096	.EQU	$0C
+DIV_8192	.EQU	$0D
+DIV_16384	.EQU	$0E
+DIV_32768	.EQU	$0F
+DIV_3		.EQU	$10
+DIV_6		.EQU	$11
+DIV_12		.EQU	$12
+DIV_24		.EQU	$13
+DIV_48		.EQU	$14
+DIV_96		.EQU	$15
+DIV_192		.EQU	$16
+DIV_384		.EQU	$17
+DIV_768		.EQU	$18
+DIV_1536	.EQU	$19
+DIV_3072	.EQU	$1A
+DIV_6144	.EQU	$1B
+DIV_12288	.EQU	$1C
+DIV_24576	.EQU	$1D
+DIV_49152	.EQU	$1E
+DIV_98304	.EQU	$1F
+;
 SER_XON		.EQU	1 << 6
 SER_DTR		.EQU	1 << 7
 SER_RTS		.EQU	1 << 13