From 8edefc1d8f2b243b6ead991d24ffce891266b908 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Wed, 18 Sep 2024 11:39:07 -0700 Subject: [PATCH] HEATH Updates - Support HEATH MSX Graphics card in HBIOS - Support HEATH MSX Graphics card in TUNE app - Startup HEATH at 8MHz to ensure hardware compatibility/detection --- Source/Apps/Tune/tune.asm | 7 ++++++- Source/HBIOS/cfg_HEATH.asm | 8 ++++---- Source/HBIOS/h8p.asm | 11 +++++++++++ Source/HBIOS/hbios.asm | 30 ++++++++++++++++++++---------- Source/HBIOS/pkd.asm | 15 +++++++++++---- Source/HBIOS/std.asm | 3 ++- 6 files changed, 54 insertions(+), 20 deletions(-) diff --git a/Source/Apps/Tune/tune.asm b/Source/Apps/Tune/tune.asm index 21acd6cb..97d16230 100644 --- a/Source/Apps/Tune/tune.asm +++ b/Source/Apps/Tune/tune.asm @@ -51,6 +51,7 @@ ; 2024-05-10 [WBW] Hack to avoid corrupting bits 6&7 of PSG R7 for NABU! ; 2024-07-08 [WBW] Add support for Les Bird's Graphics, Sound, Joystick ; 2024-07-11 [WBW] Updated, Les Bird's module now uses same settings as EB6 +; 2024-09-17 [WBW] Add support for HEATH H8 with Les Bird's MSX Card ;_______________________________________________________________________________ ; ; ToDo: @@ -636,6 +637,9 @@ CFGSIZ .EQU $ - CFGTBL ; .DB 17, $A4, $A5, $A4, $FF, $A6, $FE ; DUODYNE .DW HWSTR_DUO +; + .DB 18, $A0, $A1, $A2, $FF, $FF, $FF ; HEATH H8 + .DW HWSTR_HEATH ; .DB 22, $41, $40, $40, $FF, $FF, $FF ; NABU .DW HWSTR_NABU @@ -668,7 +672,7 @@ TMP .DB 0 ; work around use of undocumented Z80 HBIOSMD .DB 0 ; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE OCTAVEADJ .DB 0 ; AMOUNT TO ADJUST OCTAVE UP OR DOWN -MSGBAN .DB "Tune Player for RomWBW v3.10, 11-Jul-2024",0 +MSGBAN .DB "Tune Player for RomWBW v3.11, 17-Sep-2024",0 MSGUSE .DB "Copyright (C) 2024, Wayne Warthen, GNU GPL v3",13,10 .DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10 .DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10 @@ -695,6 +699,7 @@ HWSTR_LINC .DB "Z50 LiNC Sound Module",0 HWSTR_MBC .DB "NHYODYNE Sound Module",0 HWSTR_DUO .DB "DUODYNE Sound Module",0 HWSTR_NABU .DB "NABU Onboard Sound",0 +HWSTR_HEATH .DB "HEATH H8 MSX Module",0 MSGUNSUP .db "MYM files not supported with HBIOS yet!\r\n", 0 diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index d5b38754..7375a510 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -56,7 +56,7 @@ TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) ; BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +AUTOCON .SET FALSE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT ; CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW @@ -132,7 +132,7 @@ BOOTCON .SET 0 ; BOOT CONSOLE DEVICE SECCON .SET $FF ; SECONDARY CONSOLE DEVICE CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) @@ -246,7 +246,7 @@ XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) @@ -372,7 +372,7 @@ AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] ; -AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] ; diff --git a/Source/HBIOS/h8p.asm b/Source/HBIOS/h8p.asm index 67e8aade..0996b5b3 100644 --- a/Source/HBIOS/h8p.asm +++ b/Source/HBIOS/h8p.asm @@ -47,6 +47,17 @@ H8FPIO .EQU $F0 ; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION ; H8P_PREINIT: + ; HEATH H8 PLATFORM IMPLEMENTS A CPU SPEED DIVISOR AS SET BY THE + ; 2 LS BITS OF PORT H8PSPDIO. THE OSCILLATOR IS NORMALLY 16MHZ. + ; 0=FULL (16MHZ), 1=1/2 (8MHZ), 2=1/4 (4 MHZ), 3=1/8 (2 MHZ) + ; FOR BOOT, WE SET THE DIVISOR TO HALF (8MHZ)WHICH IS THE FASTEST + ; SPEED WE CAN USE THAT STILL ENSURES ALL HARDWARE CAN BE DETECTED. + ; E.G., MSX BOARD MAXES OUT AT 8MHZ. + LD A,$01 ; 8 MHZ OPERATION + OUT (H8P_SPDIO),A ; IMPLEMENT IT + LD (H8P_SPEED),A ; UPDATE FP SHADOW +; + ; HOOK INTERRUTPS FOR FRONT PANEL OPERATION LD HL,H8P_INTR CALL HB_ADDIM1 ; diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index b77bcb09..eb9c7ce3 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -356,7 +356,7 @@ RTCDEF .SET RTCDEF | %00001000 ; INITIAL SPEED LOW DEVECHO "\n" #ENDIF -#include "ez80instr.inc" +#INCLUDE "ez80instr.inc" ; ;================================================================================================== @@ -1686,14 +1686,6 @@ Z280_INITZ: OUT (EIPC_SCDP),A ; SET SYSTEM CONTROL DATA PORT (SCDP) #ENDIF ; -; HEATH BARE METAL INIT -; -#IF (PLATFORM == PLT_HEATH) - XOR A ; 16 MHZ OPERATION? - OUT (H8P_SPDIO),A ; IMPLEMENT IT - LD (H8P_SPEED),A ; UPDATE FP SHADOW -#ENDIF -; ;-------------------------------------------------------------------------------------------------- ; PLATFORM MEMORY MANAGEMENT INITIALIZATION ;-------------------------------------------------------------------------------------------------- @@ -2206,6 +2198,10 @@ HB_START2: LD (SND_CNT),A ; SND DEVICES LD (RTC_DISPACT),A ; RTC DEVICE LD (DSKY_DISPACT),A ; DSKY DEVICE + LD HL,RTC_DISPERR ; DEFAULT RTC DISPADR + LD (RTC_DISPADR),HL ; SET IT + LD HL,DSKY_DISPERR ; DEFAULT DSKY DISPADR + LD (DSKY_DISPADR),HL ; SET IT ; ; INITIALIZE SOME HCB ENTRIES ; @@ -2397,9 +2393,11 @@ HB_CPU1: ; ; RECORD THE UPDATED CPU OSCILLATOR SPEED ; -#IF ((CPUFAM == CPU_Z180) | (CPUSPDCAP == SPD_HILO)) +#IF ((CPUFAM == CPU_Z180) | (CPUSPDCAP == SPD_HILO) | (PLATFORM=PLT_HEATH)) ; SPEED MEASURED WILL BE HALF OSCILLATOR SPEED ; SO RECORD DOUBLE THE MEASURED VALUE + ; FOR HEATH, WE ARE ASSUMING THAT THE CPU SPEED DIVISOR WAS + ; PREVIOUSLY SET TO $01 MEANING HALF OF OSCILLATOR SPEED. SLA L RL H #ENDIF @@ -2433,6 +2431,12 @@ HB_CPU2: #ENDIF #ENDIF ; +#IF (PLATFORM == PLT_HEATH) + ; ADJUST HL TO REFLECT HALF SPEED OPERATION + SRL H ; ADJUST HL ASSUMING + RR L ; HALF SPEED OPERATION +#ENDIF +; #IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_SBC)) #IF (CPUSPDDEF==SPD_HIGH) ; SET HIGH SPEED VIA RTC LATCH @@ -4589,6 +4593,9 @@ RTC_DISPERR: ; WILL ONLY SAVE THE FIRST ADDRESS SET ; RTC_SETDISP: + LD A,(RTC_DISPACT) ; GET ACTIVE FLAG + OR A ; IS IT ACTIVE? + RET NZ ; ABORT IF ALREADY ACTIVE LD (RTC_DISPADR),BC ; SAVE THE ADDRESS OR $FF ; FLAG ACTIVE VALUE LD (RTC_DISPACT),A ; SAVE IT @@ -4619,6 +4626,9 @@ DSKY_DISPERR: ; WILL ONLY SAVE THE FIRST ADDRESS SET ; DSKY_SETDISP: + LD A,(DSKY_DISPACT) ; GET ACTIVE FLAG + OR A ; IS IT ACTIVE? + RET NZ ; ABORT IF ALREADY ACTIVE LD (DSKY_DISPADR),BC ; SAVE THE ADDRESS OR $FF ; FLAG ACTIVE VALUE LD (DSKY_DISPACT),A ; SAVE IT diff --git a/Source/HBIOS/pkd.asm b/Source/HBIOS/pkd.asm index 5da7dda4..609199e4 100644 --- a/Source/HBIOS/pkd.asm +++ b/Source/HBIOS/pkd.asm @@ -14,6 +14,13 @@ ; 10 04 ; +--08--+ 80 ; +; [D] [E] [F] [BO] [F4] +; [A] [B] [C] [GO] [F3] +; [7] [8] [9] [EX] [F2] +; [4] [5] [6] [DE] [F1] +; [1] [2] [3] [EN] [SH] +; [FW] [0] [BK] [CL] [CTL] +; ; KEY CODE MAP (KEY CODES) CSCCCRRR ; |||||||| ; |||||+++-- ROW @@ -34,10 +41,10 @@ ; --- --- --- --- --- --- --- --- ; 01 01 01 01 01 ; 02 02 02 02 02 -; 04 04 04 04 04 -; 08 08 08 08 08 -; 10 10 10 10 10 -; 20 20 20 20 20 L1 L2 BUZZ +; 04 04 04 04 04 +; 08 08 08 08 08 +; 10 10 10 10 10 +; 20 20 20 20 20 L1 L2 BUZZ ; PKD_PPIA .EQU PKDPPIBASE + 0 ; PORT A PKD_PPIB .EQU PKDPPIBASE + 1 ; PORT B diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 3d9b8099..32e1bdd3 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -21,10 +21,11 @@ ; 17. DUO Andrew Lynch's Duodyne Computer ; 18. HEATH Les Bird's Heath Z80 Board ; 19. EPITX Alan Cox' Mini-ITX System -; 20. MON Jacques Pelletier's Monsputer +; 20. MON Jacques Pelletier's Monsputer ; 21. GMZ180 Doug Jacksons' Genesis Z180 System ; 22. NABU NABU w/ Les Bird's RomWBW Option Board ; 23. FZ80 S100 Computers FPGA Z80 +; 24. RCZ80 RCBus eZ80 ; ; ; INCLUDE BUILD VERSION