mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Multiple
- Complete initial support for Karl's Z280 module w/ 512K RAM/ROM module - Allow swapping Z180 serial ports via ASCISWAP config variable - Fix Z180 include file per Issue #141 from J.B. Lang
This commit is contained in:
Wayne Warthen
@@ -19,7 +19,7 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s
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# setup mechanism so that multiple configuration are not needed. When building for UNA, the pre-built
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# UNA BIOS is simply imbedded, it is not built here.
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#
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$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
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$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "RCZ280", "EZZ80", "UNA"
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$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
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#
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39
Source/HBIOS/Config/RCZ280_ext.asm
Normal file
39
Source/HBIOS/Config/RCZ280_ext.asm
Normal file
@@ -0,0 +1,39 @@
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;
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;==================================================================================================
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; RC2014 Z280 STANDARD CONFIGURATION (EXTERNAL 512K RAM/ROM BANKED MEMORY MODULE)
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;==================================================================================================
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;
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
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; YOUR FILE IN THE BUILD PROCESS.
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;
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
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; SETTINGS.
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;
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
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;
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
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; DIRECTORIES ABOVE THIS ONE).
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;
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#define BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
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;
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#include "cfg_rcz280.asm"
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;
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CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ
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;
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INTMODE .SET 1
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;
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UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
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SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
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;
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IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
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;
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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@@ -11,6 +11,7 @@ else
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OBJECTS += N8_std.rom N8_std.com
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OBJECTS += RCZ180_ext.rom RCZ180_ext.com
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OBJECTS += RCZ180_nat.rom RCZ180_nat.com
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OBJECTS += RCZ280_ext.rom RCZ280_ext.com
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OBJECTS += RCZ80_kio.rom RCZ80_kio.com
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OBJECTS += RCZ80_mt.rom RCZ80_mt.com
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OBJECTS += RCZ80_duart.rom RCZ80_duart.com
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@@ -796,8 +796,32 @@ ASCI1_BUFSZ .EQU $ - ASCI1_BUF ; SIZE OF RING BUFFER
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;
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ASCI_CFG:
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;
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#IF (ASCISWAP)
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;
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ASCI1_CFG:
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; ASCI CHANNEL B CONFIG
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.DB 0 ; DEVICE NUMBER (SET DURING INIT)
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.DB 0 ; ASCI TYPE (SET DURING INIT)
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.DB 1 ; MODULE ID
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.DB ASCI1_BASE ; BASE PORT
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.DW ASCI1CFG ; LINE CONFIGURATION
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.DW ASCI1_RCVBUF ; POINTER TO RCV BUFFER STRUCT
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;
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ASCI_CFGSIZ .EQU $ - ASCI_CFG ; SIZE OF ONE CFG TABLE ENTRY
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;
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ASCI0_CFG:
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; ASCI MODULE A CONFIG
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; ASCI CHANNEL A CONFIG
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.DB 0 ; DEVICE NUMBER (SET DURING INIT)
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.DB 0 ; ASCI TYPE (SET DURING INIT)
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.DB 0 ; MODULE ID
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.DB ASCI0_BASE ; BASE PORT
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.DW ASCI0CFG ; LINE CONFIGURATION
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.DW ASCI0_RCVBUF ; POINTER TO RCV BUFFER STRUCT
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;
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#ELSE
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;
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ASCI0_CFG:
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; ASCI CHANNEL A CONFIG
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.DB 0 ; DEVICE NUMBER (SET DURING INIT)
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.DB 0 ; ASCI TYPE (SET DURING INIT)
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.DB 0 ; MODULE ID
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@@ -808,7 +832,7 @@ ASCI0_CFG:
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ASCI_CFGSIZ .EQU $ - ASCI_CFG ; SIZE OF ONE CFG TABLE ENTRY
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;
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ASCI1_CFG:
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; ASCI MODULE B CONFIG
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; ASCI CHANNEL B CONFIG
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.DB 0 ; DEVICE NUMBER (SET DURING INIT)
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.DB 0 ; ASCI TYPE (SET DURING INIT)
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.DB 1 ; MODULE ID
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@@ -816,4 +840,7 @@ ASCI1_CFG:
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.DW ASCI1CFG ; LINE CONFIGURATION
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.DW ASCI1_RCVBUF ; POINTER TO RCV BUFFER STRUCT
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;
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#ENDIF
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;
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;
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ASCI_CFGCNT .EQU ($ - ASCI_CFG) / ASCI_CFGSIZ
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@@ -14,7 +14,7 @@
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#DEFINE PLATFORM_NAME "DYNO"
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;
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PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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@@ -79,6 +79,7 @@ DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
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UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
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;
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ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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@@ -14,7 +14,7 @@
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#DEFINE PLATFORM_NAME "EASYZ80"
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;
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PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
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CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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@@ -11,7 +11,7 @@
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#DEFINE PLATFORM_NAME "ROMWBW"
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;
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PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
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CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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@@ -40,6 +40,9 @@ Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
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Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
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Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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;
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Z280_MEMWAIT .EQU 0 ; Z280: MEMORY WAIT STATES (0-3)
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Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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;
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N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
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N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
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N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR
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@@ -119,6 +122,7 @@ UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
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;
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ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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@@ -14,7 +14,7 @@
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#DEFINE PLATFORM_NAME "MARK IV"
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;
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PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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@@ -94,6 +94,7 @@ UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
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;
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ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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@@ -14,7 +14,7 @@
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#DEFINE PLATFORM_NAME "N8"
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;
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PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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@@ -97,6 +97,7 @@ UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
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;
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ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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@@ -14,7 +14,7 @@
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#DEFINE PLATFORM_NAME "RC2014"
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;
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PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
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CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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@@ -96,6 +96,7 @@ UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
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UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
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;
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ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
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ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
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ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
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ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
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;
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217
Source/HBIOS/cfg_rcz280.asm
Normal file
217
Source/HBIOS/cfg_rcz280.asm
Normal file
@@ -0,0 +1,217 @@
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;
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;==================================================================================================
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; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 Z280 (512K RAM/ROM CARD)
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;==================================================================================================
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;
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; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
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; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
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; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
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; UNDER THIS DIRECTORY.
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;
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; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
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; FOR THE PLATFORM.
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;
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#DEFINE PLATFORM_NAME "RC2014"
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;
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PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
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CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
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BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
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BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
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USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
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TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
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;
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BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
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;
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CPUOSC .EQU 24000000 ; CPU OSC FREQ IN MHZ
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INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
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DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
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;
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
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MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
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MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
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MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
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MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
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;
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Z280_MEMWAIT .EQU 0 ; Z280: MEMORY WAIT STATES (0-3)
|
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Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
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;
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RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR
|
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;
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KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
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KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
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;
|
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CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
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CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
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CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
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CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU 7372800 ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
|
||||
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
|
||||
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
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;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
|
||||
;
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
|
||||
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
|
||||
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
|
||||
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
|
||||
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
|
||||
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT
|
||||
ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR
|
||||
ACIA0CLK .EQU 7372800 ; ACIA 0: OSC FREQ IN HZ
|
||||
ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER
|
||||
ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR
|
||||
ACIA1CLK .EQU 7372800 ; ACIA 1: OSC FREQ IN HZ
|
||||
ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER
|
||||
ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_RC ; TMS: DRIVER MODE: TMSMODE_[SCG/N8]
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
|
||||
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER
|
||||
SN7CLK .EQU 7372800 / 4 ; DEFAULT TO CPUOSC / 4
|
||||
|
||||
AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 7372800 / 4 ; DEFAULT TO CPUOSC / 4
|
||||
AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
@@ -14,7 +14,7 @@
|
||||
#DEFINE PLATFORM_NAME "RC2014"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
#DEFINE PLATFORM_NAME "SBC"
|
||||
;
|
||||
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
#DEFINE PLATFORM_NAME "SCZ180"
|
||||
;
|
||||
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
@@ -91,6 +91,7 @@ UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
|
||||
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
#DEFINE PLATFORM_NAME "ZETA"
|
||||
;
|
||||
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU_[Z80|Z180]: CPU FAMILY
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
|
||||
@@ -14,7 +14,7 @@
|
||||
#DEFINE PLATFORM_NAME "ZETA V2"
|
||||
;
|
||||
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
|
||||
@@ -428,9 +428,9 @@ HBX_BNKSEL1:
|
||||
;
|
||||
HBX_BNKCPY:
|
||||
#IF (INTMODE > 0)
|
||||
LD A,I
|
||||
;LD A,I
|
||||
DI
|
||||
PUSH AF
|
||||
;PUSH AF
|
||||
#ENDIF
|
||||
LD (HBX_BC_SP),SP ; PUT STACK
|
||||
LD SP,HBX_TMPSTK ; ... IN HI MEM
|
||||
@@ -462,8 +462,8 @@ HBX_BC_LAST:
|
||||
LD SP,$FFFF ; RESTORE STACK
|
||||
HBX_BC_SP .EQU $ - 2 ; ... TO ORIGINAL VALUE
|
||||
#IF (INTMODE > 0)
|
||||
POP AF
|
||||
JP PO,$+4
|
||||
;POP AF
|
||||
;JP PO,$+4
|
||||
EI
|
||||
#ENDIF
|
||||
RET
|
||||
@@ -824,19 +824,29 @@ HB_START:
|
||||
;
|
||||
LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY
|
||||
;
|
||||
;#IF (CPUFAM == CPU_Z280)
|
||||
; LD C,$12 ; CACHE CONTROL REGISTER
|
||||
; LD HL,$0060 ; DISABLE INSTRUCTION CACHE
|
||||
; ;LDCTL (C),HL ; SET IT (8 BITS)
|
||||
; .DB $ED,$6E
|
||||
; ;PCACHE ; PURGE ANY REMNANTS OF CACHE
|
||||
; .DB $ED,$65
|
||||
;#ENDIF
|
||||
#IF (CPUFAM == CPU_Z280)
|
||||
;LD C,$12 ; CACHE CONTROL REGISTER
|
||||
;LD HL,$0060 ; DISABLE INSTRUCTION CACHE
|
||||
;;LDCTL (C),HL ; SET IT (8 BITS)
|
||||
;.DB $ED,$6E
|
||||
;;PCACHE ; PURGE ANY REMNANTS OF CACHE
|
||||
;.DB $ED,$65
|
||||
;
|
||||
LD C,$02 ; BUS TIMING AND CONTROL REGISTER
|
||||
LD HL,$0033 ; 3 I/O WAIT STATES ADDED
|
||||
;LD HL,$00F3 ; 3 I/O W/S & 3 INT ACK W/S
|
||||
;LDCTL (C),HL ; SET IT (8 BITS)
|
||||
.DB $ED,$6E
|
||||
#ENDIF
|
||||
;
|
||||
#IF (CPUFAM == CPU_Z180)
|
||||
; SET BASE FOR CPU IO REGISTERS
|
||||
; DO NOT USE Z180_ICR FROM Z180.INC BECAUSE THE ICR
|
||||
; IS NOT YET AT THE RUNNING LOCATION. AT RESET, THE Z180
|
||||
; REGISTER BASE I/O ADDRESS IS ZERO, SO INITIALLY, ICR IS
|
||||
; AT $3F.
|
||||
LD A,Z180_BASE
|
||||
OUT0 (Z180_ICR),A
|
||||
OUT0 ($3F),A ; AT RESET, ICR IS AT $3F
|
||||
|
||||
DIAG(%00000010)
|
||||
|
||||
@@ -1090,12 +1100,13 @@ SAVE_REC_M:
|
||||
;
|
||||
; DISCOVER CPU TYPE
|
||||
;
|
||||
; THIS CODE IS DERIVED FROM UNA BY JOHN COFFMAN
|
||||
; SOME OF THIS CODE IS DERIVED FROM UNA BY JOHN COFFMAN
|
||||
;
|
||||
; 0: Z80
|
||||
; 1: Z80180 - ORIGINAL Z180 (EQUIVALENT TO HD64180)
|
||||
; 2: Z8S180 - ORIGINAL S-CLASS, REV. K, AKA SL1960, NO ASCI BRG
|
||||
; 3: Z8S180 - REVISED S-CLASS, REV. N, W/ ASCI BRG
|
||||
; 4: Z8280
|
||||
;
|
||||
LD HL,0 ; L = 0 MEANS Z80
|
||||
;
|
||||
@@ -1126,6 +1137,18 @@ SAVE_REC_M:
|
||||
;
|
||||
#ENDIF
|
||||
;
|
||||
#IF (CPUFAM == CPU_Z280)
|
||||
;
|
||||
; TEST FOR Z280 PER ZILOG DOC
|
||||
LD A,$40 ; INITIALIZE THE OPERAND
|
||||
.DB $CB,$37 ; THIS INSTRUCTION WILL SET THE S FLAG
|
||||
; ON THE Z80 CPU AND CLEAR THE S FLAG
|
||||
; ON THE Z280 MPU.
|
||||
JP M,HB_CPU1 ; IF Z80, SKIP AHEAD
|
||||
LD L,4 ; WE ARE Z280
|
||||
;
|
||||
#ENDIF
|
||||
;
|
||||
HB_CPU1:
|
||||
LD A,L
|
||||
LD (HB_CPUTYPE),A
|
||||
@@ -1174,6 +1197,16 @@ HB_CPU2:
|
||||
LD (CB_CPUKHZ),DE
|
||||
;
|
||||
#ENDIF
|
||||
;
|
||||
#IF (CPUFAM == CPU_Z280)
|
||||
;
|
||||
; Z280 PHI IS OSC / 2
|
||||
LD A,(CPUOSC / 2) / 1000000
|
||||
LD (CB_CPUMHZ),A
|
||||
LD DE,(CPUOSC / 2) / 1000
|
||||
LD (CB_CPUKHZ),DE
|
||||
;
|
||||
#ENDIF
|
||||
;
|
||||
DIAG(%00011111)
|
||||
;
|
||||
@@ -1267,7 +1300,6 @@ HB_CPU2:
|
||||
;
|
||||
#ENDIF
|
||||
;
|
||||
;
|
||||
; INITIALIZE HEAP STORAGE
|
||||
;
|
||||
; INITIALIZE POINTERS
|
||||
@@ -1454,18 +1486,22 @@ HB_SPDTST:
|
||||
; DISPLAY CPU CONFIG
|
||||
;
|
||||
CALL NEWLINE
|
||||
XOR A
|
||||
#IF (CPUFAM == CPU_Z180)
|
||||
LD A,Z180_MEMWAIT
|
||||
#ELSE
|
||||
LD A,0
|
||||
#ENDIF
|
||||
#IF (CPUFAM == CPU_Z280)
|
||||
LD A,Z280_MEMWAIT
|
||||
#ENDIF
|
||||
CALL PRTDECB
|
||||
CALL PRTSTRD
|
||||
.TEXT " MEM W/S, $"
|
||||
LD A,1
|
||||
#IF (CPUFAM == CPU_Z180)
|
||||
LD A,Z180_IOWAIT + 1
|
||||
#ELSE
|
||||
LD A,1
|
||||
#ENDIF
|
||||
#IF (CPUFAM == CPU_Z280)
|
||||
LD A,Z280_IOWAIT + 1
|
||||
#ENDIF
|
||||
CALL PRTDECB
|
||||
CALL PRTSTRD
|
||||
@@ -1489,6 +1525,28 @@ HB_SPDTST:
|
||||
CALL PRTSTRD
|
||||
.TEXT "KB RAM$"
|
||||
;
|
||||
#IF (CPUFAM == CPU_Z280)
|
||||
CALL NEWLINE
|
||||
PRTS("Z280: $")
|
||||
PRTS("MSR=$")
|
||||
LD C,$00 ; MASTER STATUS REGISTER
|
||||
;LDTCL HL,(C) ; GET VALUE
|
||||
.DB $ED,$66
|
||||
CALL PRTHEXWORDHL
|
||||
CALL PC_SPACE
|
||||
PRTS("BTCR=$")
|
||||
LD C,$02 ; BUS TIMING AND CONTROL REGISTER
|
||||
;LDTCL HL,(C) ; GET VALUE
|
||||
.DB $ED,$66
|
||||
CALL PRTHEXWORDHL
|
||||
CALL PC_SPACE
|
||||
PRTS("CCR=$")
|
||||
LD C,$12 ; CACHE CONTROL REGISTER
|
||||
;LDTCL HL,(C) ; GET VALUE
|
||||
.DB $ED,$66
|
||||
CALL PRTHEXWORDHL
|
||||
#ENDIF
|
||||
;
|
||||
; LOW BATTERY DIAGNOSTIC MESSAGE
|
||||
;
|
||||
#IF (BATCOND)
|
||||
@@ -2782,14 +2840,14 @@ SYS_SETSECS:
|
||||
;
|
||||
SYS_PEEK:
|
||||
#IF (INTMODE == 1)
|
||||
LD A,I
|
||||
;LD A,I
|
||||
DI
|
||||
PUSH AF
|
||||
;PUSH AF
|
||||
#ENDIF
|
||||
CALL HBX_PEEK ; IMPLEMENTED IN PROXY
|
||||
#IF (INTMODE == 1)
|
||||
POP AF
|
||||
JP PO,$+4
|
||||
;POP AF
|
||||
;JP PO,$+4
|
||||
EI
|
||||
#ENDIF
|
||||
XOR A
|
||||
@@ -2804,14 +2862,14 @@ SYS_PEEK:
|
||||
;
|
||||
SYS_POKE:
|
||||
#IF (INTMODE == 1)
|
||||
LD A,I
|
||||
;LD A,I
|
||||
DI
|
||||
PUSH AF
|
||||
;PUSH AF
|
||||
#ENDIF
|
||||
CALL HBX_POKE ; IMPLEMENTED IN PROXY
|
||||
#IF (INTMODE == 1)
|
||||
POP AF
|
||||
JP PO,$+4
|
||||
;POP AF
|
||||
;JP PO,$+4
|
||||
EI
|
||||
#ENDIF
|
||||
XOR A
|
||||
@@ -4261,10 +4319,11 @@ PS_PAD1:
|
||||
DJNZ PS_PAD1
|
||||
RET
|
||||
;
|
||||
HB_CPU_STR: .TEXT " Z80$" ; HB_STRZ80
|
||||
.TEXT " Z80180$" ; HB_STRZ180
|
||||
.TEXT " Z8S180-K$" ; HB_STRZS180K
|
||||
.TEXT " Z8S180-N$" ; HB_STRZS180N
|
||||
HB_CPU_STR: .TEXT " Z80$"
|
||||
.TEXT " Z80180$"
|
||||
.TEXT " Z8S180-K$"
|
||||
.TEXT " Z8S180-N$"
|
||||
.TEXT " Z80280$"
|
||||
;
|
||||
PS_STRNUL .TEXT "--$" ; DISPLAY STRING FOR NUL VALUE
|
||||
;
|
||||
|
||||
@@ -64,4 +64,4 @@ Z180_BBR .EQU Z180_BASE + $39 ; MMU BANK BASE REGISTER
|
||||
Z180_CBAR .EQU Z180_BASE + $3A ; MMU COMMON/BANK AREA REGISTER
|
||||
;
|
||||
Z180_OMCR .EQU Z180_BASE + $3E ; OPERATION MODE CONTROL
|
||||
Z180_ICR .EQU $3F ; I/O CONTROL REGISTER (NOT RELOCATED!!!)
|
||||
Z180_ICR .EQU Z180_BASE + $3F ; I/O CONTROL REGISTER
|
||||
|
||||
Reference in New Issue
Block a user