mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Reintegrate dwg -> trunk
This commit is contained in:
wayne
@@ -1,111 +0,0 @@
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; btromwbw.inc 2/17/2013 dwg - boot up CP/M, RomWBW Style ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Unlike the Monahan style of booting, the RomWBW loading ;
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; is performed by reading in the metadata sector and using ;
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; the three words at the end of the sector to determine the ;
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; loading address and starting location. ;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;-------------- BOOT UP CPM FROM HARD DISK ON S100COMPUTERS IDR BOARD ----------------
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;BOOT UP THE 8255/IDE Board HARD DISK/Flash Memory Card
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;NOTE CODE IS ALL HERE IN CASE A 2716 IS USED
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HBOOTWBW:
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POP HL ;CLEAN UP STACK
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CALL INITILIZE_IDE_BOARD ;Initilze the 8255 and drive (again just in case)
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LD D,11100000B ;Data for IDE SDH reg (512bytes, LBA mode,single drive)
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LD E,REGshd ;00001110,(0EH) CS0,A2,A1,
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CALL IDEwr8D ;Write byte to select the MASTER device
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LD B,0FFH ;Delay time to allow a Hard Disk to get up to speed
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WaitInitX:
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LD E,REGstatus ;Get status after initilization
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CALL IDErd8D ;Check Status (info in [D])
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BIT 7,D
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JR Z,SECREADX ;Zero, so all is OK to write to drive
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;Delay to allow drive to get up to speed
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PUSH BC
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LD BC,0FFFFH
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DXLAY2X: LD D,2 ;May need to adjust delay time to allow cold drive to
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DXLAY1X: DEC D ;to speed
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JR NZ,DXLAY1X
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DEC BC
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LD A,C
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OR B
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JR NZ,DXLAY2X
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POP BC
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DJNZ WaitInitX ;If after 0FFH, 0FEH, 0FDH... 0, then drive initilization problem
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IDErrorX:
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LD HL,DRIVE_NR_ERR ;Drive not ready
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JP ABORT_ERR_MSG
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SECREADX: ;Note CPMLDR will ALWAYS be on TRK 0,SEC 1,Head 0
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CALL IDEwaitnotbusy ;Make sure drive is ready
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JR C,IDErrorX ;NC if ready
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LD D,1 ;Load track 0,sec 1, head 0
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LD E,REGsector ;Send info to drive
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CALL IDEwr8D
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LD D,0 ;Send Low TRK#
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LD E,REGcyLSB
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CALL IDEwr8D
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LD D,0 ;Send High TRK#
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LD E,REGcyMSB
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CALL IDEwr8D
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LD D,SEC_COUNT ;Count of CPM sectors we wish to read
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LD E,REGcnt
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CALL IDEwr8D
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LD D,CMDread ;Send read CMD
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LD E,REGCMD
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CALL IDEwr8D ;Send sec read CMD to drive.
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CALL IDEwdrq ;Wait until it's got the data
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LD HL,CPM_ADDRESS ;DMA address where the CPMLDR resides in RAM
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LD B,0 ;256X2 bytes
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LD C,SEC_COUNT ;Count of sectors X 512
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MoreRD16X:
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LD A,REGdata ;REG regsiter address
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OUT (IDECport),A
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OR IDErdline ;08H+40H, Pulse RD line
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OUT (IDECport),A
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IN A,(IDEAport) ;read the LOWER byte
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LD (HL),A
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INC HL
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IN A,(IDEBport) ;read the UPPER byte
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LD (HL),A
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INC HL
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LD A,REGdata ;Deassert RD line
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OUT (IDECport),A
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DJNZ MoreRD16X
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DEC C
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JR NZ,MoreRD16X
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LD E,REGstatus ;Check the R/W status when done
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CALL IDErd8D
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BIT 0,D
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JR NZ,IDEerr1X ;Z if no errors
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LD HL,STARTCPM
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LD A,(HL)
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CP 31H ;EXPECT TO HAVE 31H @80H IE. LD SP,80H
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JP Z,STARTCPM ;AS THE FIRST INSTRUCTION. IF OK JP to 100H in RAM
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JP ERR_LD1 ;Boot Sector Data incorrect
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IDEerr1X:
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LD HL,IDE_RW_ERROR ;Drive R/W Error
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JP ABORT_ERR_MSG
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;;;;;;;;;;;;;;;;;;;;;;
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; eof - btromwbw.inc ;
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;;;;;;;;;;;;;;;;;;;;;;
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@@ -1,111 +0,0 @@
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;
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;==================================================================================================
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; ROMWBW 2.X CONFIGURATION FOR N8 5/8/2012
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;==================================================================================================
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;
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; BUILD CONFIGURATION OPTIONS
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;
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CPUFREQ .EQU 20 ; IN MHZ, USED TO COMPUTE DELAY FACTORS
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;
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;
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DEFCON .EQU CIODEV_UART ; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_VDU, DIODEV_PRPCON
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ALTCON .EQU DEFCON ; ALT CONSOLE DEVICE (USED WHEN CONFIG JUMPER SHORTED)
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DEFVDA .EQU VDADEV_N8V ; DEFAULT VDA (VDADEV_NONE, VDADEV_VDU, VDADEV_CVDU, VDADEV_7220, V\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
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DEFEMU .EQU EMUTYP_TTY ; DEFAULT EMULATION TYPE (EMUTYP_TTY, EMUTYP_ANSI, ...)
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;
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RAMSIZE .EQU 512 ; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
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CLRRAMDISK .EQU CLR_AUTO ; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
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;
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DSKMAP .EQU DM_RAM ; DM_ROM, DM_RAM, DM_FD, DM_IDE, DM_PPIDE, DM_SD, DM_PRPSD, DM_PPPSD
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;
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DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
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;
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UARTENABLE .EQU TRUE ; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
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UARTFIFO .EQU TRUE ; TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
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UARTAFC .EQU FALSE ; TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
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;
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VDUENABLE .EQU FALSE ; TRUE FOR VDU BOARD SUPPORT
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CVDUENABLE .EQU FALSE ; TRUE FOR CVDU BOARD SUPPORT
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UPD7220ENABLE .EQU FALSE ; TRUE FOR uPD7220 BOARD SUPPORT
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N8VENABLE .EQU TRUE ; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
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;
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DEFIOBYTE .EQU $00 ; DEFAULT INITIAL VALUE FOR CP/M IOBYTE, $00=TTY, $01=CRT (MUST HAVE CRT HARDWARE)
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ALTIOBYTE .EQU DEFIOBYTE ; ALT INITIAL VALUE (USED WHEN CONFIG JUMPER SHORTED)
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WRTCACHE .EQU TRUE ; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
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DSKTRACE .EQU FALSE ; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
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;
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FDENABLE .EQU FALSE ; TRUE FOR FLOPPY SUPPORT
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FDMODE .EQU FDMODE_N8 ; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
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FDTRACE .EQU 1 ; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
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;;
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FDMEDIA .EQU FDM144 ; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
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FDMEDIAALT .EQU FDM720 ; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
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FDMAUTO .EQU TRUE ; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
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;
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IDEENABLE .EQU FALSE ; TRUE FOR IDE SUPPORT
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IDEMODE .EQU IDEMODE_DIO ; IDEMODE_DIO, IDEMODE_DIDE
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IDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
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IDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
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IDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
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;
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PPIDEENABLE .EQU FALSE ; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
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PPIDEMODE .EQU PPIDEMODE_STD ; PPIDEMODE_STD, PPIDEMODE_DIO3
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PPIDETRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
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PPIDE8BIT .EQU FALSE ; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
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PPIDECAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
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PPIDESLOW .EQU FALSE ; ADD DELAYS TO HELP PROBLEMATIC HARDWARE (TRY THIS IF PPIDE IS UNRELIABLE)
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;
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SDENABLE .EQU FALSE ; TRUE FOR SD SUPPORT
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SDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
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SDCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
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SDCSIO .EQU TRUE ; TRUE IF USING THE CSIO PORT (N8 ONLY)
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SDCSIOFAST .EQU FALSE ; TRUE IF USING THE LOOKUP TABLE RATHER THAN SHIFTS AND ROTATES (N8 ONLY)
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PPISD .EQU FALSE ; TRUE IF USING PPISD MINI-BOARD (DO NOT COMBINE WITH PPIDE)
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S2ISD .EQU FALSE ; TRUE IF USING SCSI2IDE BOARD (DO NOT COMBINE WITH PPISD)
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;
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PRPENABLE .EQU FALSE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
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PRPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
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PRPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
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PRPSDCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
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PRPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
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;
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PPPENABLE .EQU FALSE ; TRUE FOR PARPORTPROP SUPPORT
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PPPSDENABLE .EQU TRUE ; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
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PPPSDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
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PPPSDCAPACITY .EQU 64 ; CAPACITY OF PPP SD DEVICE (IN MB)
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PPPCONENABLE .EQU TRUE ; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
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;
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HDSKENABLE .EQU FALSE ; TRUE FOR SIMH HDSK SUPPORT
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HDSKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
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HDSKCAPACITY .EQU 64 ; CAPACITY OF DEVICE (IN MB)
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;
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PPKENABLE .EQU TRUE ; TRUE FOR PARALLEL PORT KEYBOARD
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PPKTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
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KBDENABLE .EQU FALSE ; TRUE FOR PS/2 KEYBOARD ON I8242
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KBDTRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
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;
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TTYENABLE .EQU TRUE ; INCLUDE TTY EMULATION SUPPORT
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ANSIENABLE .EQU TRUE ; INCLUDE ANSI EMULATION SUPPORT
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ANSITRACE .EQU 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
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;
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BOOTTYPE .EQU BT_MENU ; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
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BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
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BOOT_DEFAULT .EQU 'R' ; SELECTION TO INVOKE AT TIMEOUT
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;
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BAUDRATE .EQU 38400 ; IN BPS: 1200, 9600, 38400, ..., 115200
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TERMTYPE .EQU TERM_ANSI ; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
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;
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; Z180_CLKDIV .EQU 1 ; 0=XTAL/2, 1=XTAL/1
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;; Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES TO INSERT (0-3)
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;; Z180_IOWAIT .EQU 3 ; IO WAIT STATES TO INSERT (0-3)
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;; Z180_CNTLB0 .EQU 20H ; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT
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;; Z180_CNTLB1 .EQU 20H ; SERIAL PORT 1 DIV, SEE Z180 CLOCKING DOCUMENT
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;;;;;;;;;;;;;;;;;;;;;;;;
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; EOF - CONFG_S100.ASM ;
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;;;;;;;;;;;;;;;;;;;;;;;;
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,6 +0,0 @@
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; ~/RomWBW/branches/s100/Source/s100cpu.inc 1/17/2013 dwg -
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; S100COMPUTERS.COM Z80 Master CPU Board Schema
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#DEFINE IC_Z80
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@@ -1,10 +0,0 @@
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; ~/RomWBW/branches/s100/Source/s100dide.inc 1/17/2013 dwg -
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; S100COMPUTERS.COM Dual IDE Board Schema
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;#DEFINE IC_SCC_8530
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;#DEFINE IC_PPI_8255
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@@ -1,38 +0,0 @@
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; ~/RomWBW/branches/s100/Source/s100iob.inc 1/17/2013 dwg -
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; S100COMPUTERS.COM Input Output Board Schema
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#DEFINE IC_SCC_8530
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#DEFINE IC_PPI_8255
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;
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;==================================================================
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; WBW: STUFF BELOW IS TEMPORARY TO ALLOW S100 TO BUILD WITHOUT ERROR
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;==================================================================
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;
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; PPI 82C55 I/O IS DECODED TO PORT 60-67
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;
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PPIBASE .EQU 60H
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PPIA .EQU PPIBASE + 0 ; PORT A
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PPIB .EQU PPIBASE + 1 ; PORT B
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PPIC .EQU PPIBASE + 2 ; PORT C
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PPIX .EQU PPIBASE + 3 ; PPI CONTROL PORT
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;
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; 16C550 SERIAL LINE UART
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;
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SIO_BASE .EQU 68H
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SIO_RBR .EQU SIO_BASE + 0 ; DLAB=0: RCVR BUFFER REG (READ ONLY)
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SIO_THR .EQU SIO_BASE + 0 ; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
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SIO_IER .EQU SIO_BASE + 1 ; DLAB=0: INT ENABLE REG
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SIO_IIR .EQU SIO_BASE + 2 ; INT IDENT REGISTER (READ ONLY)
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SIO_FCR .EQU SIO_BASE + 2 ; FIFO CONTROL REG (WRITE ONLY)
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SIO_LCR .EQU SIO_BASE + 3 ; LINE CONTROL REG
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SIO_MCR .EQU SIO_BASE + 4 ; MODEM CONTROL REG
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SIO_LSR .EQU SIO_BASE + 5 ; LINE STATUS REG
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SIO_MSR .EQU SIO_BASE + 6 ; MODEM STATUS REG
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SIO_SCR .EQU SIO_BASE + 7 ; SCRATCH REGISTER
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SIO_DLL .EQU SIO_BASE + 0 ; DLAB=1: DIVISOR LATCH (LS)
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SIO_DLM .EQU SIO_BASE + 1 ; DLAB=1: DIVISOR LATCH (MS)
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;
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;==================================================================
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@@ -1,10 +0,0 @@
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; ~/RomWBW/branches/s100/Source/s100rrf.inc 1/17/2013 dwg -
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; S100COMPUTERS.COM Ram Rom Flash Board Schema
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;#DEFINE IC_SCC_8530
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;#DEFINE IC_PPI_8255
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@@ -1,37 +0,0 @@
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; std-s100.inc 1/19/2013 dwg -
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;
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;===============================================================================
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;
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; CHARACTER DEVICES
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;
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CIODEV_UART .EQU $00
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CIODEV_N8V .EQU $50
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CIODEV_PRPCON .EQU $60
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CIODEV_PPPCON .EQU $70
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CIODEV_CRT .EQU $D0
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CIODEV_BAT .EQU $E0
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CIODEV_NUL .EQU $F0
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;
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; DISK DEVICES (ONLY FIRST NIBBLE RELEVANT, SECOND NIBBLE RESERVED FOR UNIT)
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;
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DIODEV_MD .EQU $00
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DIODEV_FD .EQU $10
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DIODEV_IDE .EQU $20
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DIODEV_ATAPI .EQU $30
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DIODEV_PPIDE .EQU $40
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DIODEV_SD .EQU $50
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DIODEV_PRPSD .EQU $60
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DIODEV_PPPSD .EQU $70
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DIODEV_HDSK .EQU $80
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;
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; VDA DEVICES (VIDEO DISPLAY ADAPTER)
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;
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VDADEV_NONE .EQU $00 ; NO VDA DEVICE
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VDADEV_VDU .EQU $10 ; ECB VDU - 6545 CHIP
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VDADEV_CVDU .EQU $20 ; ECB COLOR VDU - 8563 CHIP (NOT IMP)
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VDADEV_UPD7220 .EQU $30 ; ECB uP7220 (NOT IMPLEMENTED)
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VDADEV_N8V .EQU $40 ; N8 ONBOARD VDA SUBSYSTEM
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;;;;;;;;;;;;;;;;;;;;;;
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; eof - std-s100.inc ;
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;;;;;;;;;;;;;;;;;;;;;;
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Reference in New Issue
Block a user