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Reintegrate wbw -> trunk

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wayne
2012-11-23 14:21:38 +00:00
parent f510da9d46
commit 8f5fd86169
2 changed files with 12 additions and 11 deletions
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1
Source/dbgmon.asm
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@@ -757,7 +757,6 @@ HEXINS:
RET ; DONE
NIBLS:
CALL KIN ; GET K B. DATA
INC HL ; INC KB POINTER
CP 40H ; TEST FOR ALPHA
JR NC,ALPH ;
AND 0FH ; GET THE BITS

22
Source/uart.asm
View File

@@ -131,8 +131,9 @@ UART0_IST1: ; CHECK FOR STAT0.RDRF (DATA READY)
IN A,(SIO_LSR) ; READ LINE STATUS REGISTER
AND $01 ; TEST IF DATA IN RECEIVE BUFFER
#ENDIF
JP Z,CIO_IDLE ; DO IDLE PROCESSING
LD A,$01 ; SIGNAL DATA PENDING
JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
XOR A
INC A ; SIGNAL CHAR READY, A = 1
RET
;
;
@@ -153,14 +154,13 @@ UART0_OST:
#IF (PLATFORM == PLT_N8)
IN0 A,(CPU_STAT0)
AND $02
JR Z,UART0_OST
#ELSE
IN A,(SIO_LSR) ; READ LINE STATUS REGISTER
AND $20
JR Z,UART0_OST ; IF NOT REPEAT
#ENDIF
JP Z,CIO_IDLE ; DO IDLE PROCESSING
LD A,$01 ; SIGNAL DATA PENDING
JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
XOR A
INC A ; SIGNAL BUFFER EMPTY, A = 1
RET
;
;
@@ -205,8 +205,9 @@ UART1_IST:
UART1_IST1: ; CHECK FOR STAT0.RDRF (DATA READY)
IN0 A,(CPU_STAT1) ; READ LINE STATUS REGISTER
AND $80 ; TEST IF DATA IN RECEIVE BUFFER
JP Z,CIO_IDLE ; DO IDLE PROCESSING
LD A,$01 ; SIGNAL DATA PENDING
JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
XOR A
INC A ; SIGNAL CHAR READY, A = 1
RET
;
;
@@ -223,7 +224,8 @@ UART1_OST:
IN0 A,(CPU_STAT1)
AND $02
JR Z,UART1_OST
JP Z,CIO_IDLE ; DO IDLE PROCESSING
LD A,$01 ; SIGNAL DATA PENDING
JP Z,CIO_IDLE ; DO IDLE PROCESSING AND RETURN
XOR A
INC A ; SIGNAL BUFFER EMPTY, A = 1
RET
#ENDIF