Browse Source

Z80-Retro SD Card Support (Alan Cox)

pull/351/head v3.3.0-dev.3
Wayne Warthen 3 years ago
parent
commit
9100f199b1
  1. 1
      Doc/ChangeLog.txt
  2. 2
      Source/HBIOS/Config/Z80RETRO_std.asm
  3. 2
      Source/HBIOS/cfg_dyno.asm
  4. 2
      Source/HBIOS/cfg_master.asm
  5. 2
      Source/HBIOS/cfg_mbc.asm
  6. 2
      Source/HBIOS/cfg_mk4.asm
  7. 2
      Source/HBIOS/cfg_n8.asm
  8. 2
      Source/HBIOS/cfg_rcz180.asm
  9. 2
      Source/HBIOS/cfg_rcz280.asm
  10. 2
      Source/HBIOS/cfg_rcz80.asm
  11. 2
      Source/HBIOS/cfg_rph.asm
  12. 2
      Source/HBIOS/cfg_sbc.asm
  13. 2
      Source/HBIOS/cfg_scz180.asm
  14. 5
      Source/HBIOS/cfg_z80retro.asm
  15. 2
      Source/HBIOS/cfg_zeta.asm
  16. 2
      Source/HBIOS/cfg_zeta2.asm
  17. 143
      Source/HBIOS/sd.asm
  18. 1
      Source/HBIOS/std.asm
  19. 2
      Source/ver.inc
  20. 2
      Source/ver.lib

1
Doc/ChangeLog.txt

@ -3,6 +3,7 @@ Version 3.3
- WBW: Support Front Panel switches
- A?C: Preliminary support for Z80-Retro
- A?C: Support for SD PIO
- A?C: Support for Z80-Retro SD interface
Version 3.2.1
-------------

2
Source/HBIOS/Config/Z80RETRO_std.asm

@ -32,4 +32,4 @@ CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
;
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)

2
Source/HBIOS/cfg_dyno.asm

@ -227,7 +227,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_master.asm

@ -282,7 +282,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_mbc.asm

@ -211,7 +211,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_mk4.asm

@ -221,7 +221,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_n8.asm

@ -223,7 +223,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rcz180.asm

@ -227,7 +227,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rcz280.asm

@ -237,7 +237,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rcz80.asm

@ -231,7 +231,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_rph.asm

@ -212,7 +212,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_sbc.asm

@ -211,7 +211,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_scz180.asm

@ -227,7 +227,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

5
Source/HBIOS/cfg_z80retro.asm

@ -184,9 +184,8 @@ PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE

2
Source/HBIOS/cfg_zeta.asm

@ -155,7 +155,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

2
Source/HBIOS/cfg_zeta2.asm

@ -166,7 +166,7 @@ PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR]
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)

143
Source/HBIOS/sd.asm

@ -333,6 +333,27 @@ SD_DDRVAL .EQU %00001101 ; DATA DIRECTION REGISTER VALUE
SD_INVCS .EQU FALSE ; INVERT CS
#ENDIF
;
#IF (SDMODE == SDMODE_Z80R) ; Z80 Retro
;
; SPLIT OVER TWO REGISTERS TO DRIVE CLK. THE CS LINE IS ON THE GPIO
; WHICH IS THE SAME LATCHES THAT CONTROL MMU ON/OFF, SO DON;T GLITCH
; THEM WHEN UPDATING!
;
SD_DEVMAX .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRDEF .EQU %00000001 ; OUTPUT PORT DEFAULT STATE
SD_OPRMSK .EQU %00000101 ; OUTPUT PORT MASK
SD_OPRREG .EQU $64 ; CS VIA GPIO
SD_IOBASE .EQU $68 ; 68/69 FOR OUTPUT
SD_IOREG .EQU SD_IOBASE ; INPUT REGISTER
SD_IOCLK .EQU SD_IOBASE+1 ; CLOCK IS OFF A0
SD_GPIO .EQU $64 ; MISO IS ON THE GPIO
SD_CS0 .EQU %00000100 ; SELECT
SD_DI .EQU %00000001 ; DATA IN (CARD <- CPU) MOSI
SD_DO .EQU %00000001 ; DATA OUT (CARD -> CPU) MISO
SD_CINIT .EQU FALSE ; INITIALIZE OUTPUT PORT
SD_INVCS .EQU FALSE ; INVERT CS
#ENDIF
;
#IF (SD_DEVCNT > SD_DEVMAX)
.ECHO "*** ERROR: SDCNT EXCEEDS MAXIMUM SUPPORTED BY INTERFACE!!!\n"
!!! ; FORCE AN ASSEMBLY ERROR
@ -546,6 +567,15 @@ SD_INIT:
CALL PRTHEXBYTE
#ENDIF
;
#IF (SDMODE == SDMODE_Z80R)
PRTS(" MODE=Z80R$")
PRTS(" IO=0x$")
LD A,SD_IOBASE
CALL PRTHEXBYTE
LD A,SD_OPRDEF
LD (SD_OPRVAL),A
#ENDIF
;
#IF (SDMODE == SDMODE_USR)
PRTS(" MODE=USER$")
PRTS(" IO=0x$")
@ -1910,7 +1940,7 @@ SD_DESELECT:
AND ~SD_CS0
#ENDIF
; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO))
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
#IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1))
XOR SD_CS0 | SD_CS1
#ELSE
@ -1957,9 +1987,48 @@ SD_PUT:
SET 4,A ; SET TRANSMIT ENABLE
OUT0 (SD_CNTR),A
#ELSE
#IF (SDMODE == SDMODE_UART)
#IF (SDMODE == SDMODE_Z80R)
; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE
; WHILST THE OTHER PATHS DO ?
LD C,A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
RL C
RLA
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
#ELSE
#IF (SDMODE == SDMODE_UART)
XOR $FF ; DI IS INVERTED ON UART
#ENDIF
#ENDIF
LD C,A ; C=BYTE TO SEND
LD B,8 ; SEND 8 BITS (LOOP 8 TIMES)
LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE
@ -1975,6 +2044,7 @@ SD_PUT1:
DJNZ SD_PUT1 ; REPEAT FOR ALL 8 BITS
LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE
OUT (SD_OPRREG),A ; LEAVE WITH CLOCK LOW
#ENDIF
#ENDIF
#ENDIF
RET ; DONE
@ -1997,34 +2067,83 @@ SD_GET:
CALL MIRROR ; MSB<-->LSB MIRROR BITS
LD A,C ; KEEP RESULT
#ELSE
#IF (SDMODE == SDMODE_Z80R)
; MUST PRESERVE HL,DE
PUSH DE
LD A,1
LD C,SD_GPIO
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
OUT (SD_IOREG),A
OUT (SD_IOCLK),A
IN B,(C)
RR B
RL E
LD A,E
POP DE
#ELSE
LD B,8 ; RECEIVE 8 BITS (LOOP 8 TIMES)
LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE
SD_GET1:
XOR SD_CLK ; TOGGLE CLOCK
OUT (SD_OPRREG),A ; UPDATE CLOCK
IN A,(SD_INPREG) ; READ THE DATA WHILE CLOCK IS ACTIVE
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO))
RLA ; ROTATE INP:7 INTO CF
#ENDIF
#IF (SDMODE == SDMODE_N8)
#ENDIF
#IF (SDMODE == SDMODE_N8)
RLA ; ROTATE INP:6 INTO CF
RLA ; "
#ENDIF
#IF (SDMODE == SDMODE_UART)
#ENDIF
#IF (SDMODE == SDMODE_UART)
RLA ; ROTATE INP:5 INTO CF
RLA ; "
RLA ; "
#ENDIF
#IF (SDMODE == SDMODE_DSD)
#ENDIF
#IF (SDMODE == SDMODE_DSD)
RRA ; ROTATE INP:0 INTO CF
#ENDIF
#ENDIF
RL C ; ROTATE CF INTO C:0
LD A,(SD_OPRVAL) ; BACK TO INITIAL VALUES (TOGGLE CLOCK)
OUT (SD_OPRREG),A ; DO IT
DJNZ SD_GET1 ; REPEAT FOR ALL 8 BITS
LD A,C ; GET BYTE RECEIVED INTO A
#IF (SDMODE == SDMODE_UART)
#IF (SDMODE == SDMODE_UART)
XOR $FF ; DO IS INVERTED ON UART
#ENDIF
#ENDIF
#ENDIF
#ENDIF

1
Source/HBIOS/std.asm

@ -185,6 +185,7 @@ SDMODE_SC .EQU 8 ; SC (Steve Cousins)
SDMODE_MT .EQU 9 ; MT (Shift register SPI WIZNET for RCBUS)
SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE)
SDMODE_PIO .EQU 11 ; Z80 PIO bitbang
SDMODE_Z80R .EQU 12 ; Z80 Retro
;
; AY SOUND CHIP MODE SELECTIONS
;

2
Source/ver.inc

@ -2,7 +2,7 @@
#DEFINE RMN 3
#DEFINE RUP 0
#DEFINE RTP 0
#DEFINE BIOSVER "3.3.0-dev.2"
#DEFINE BIOSVER "3.3.0-dev.3"
#define rmj RMJ
#define rmn RMN
#define rup RUP

2
Source/ver.lib

@ -3,5 +3,5 @@ rmn equ 3
rup equ 0
rtp equ 0
biosver macro
db "3.3.0-dev.2"
db "3.3.0-dev.3"
endm

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