From 2ebd80048268c8322ca5e6dcb88c7b1f61902e32 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 24 Nov 2019 20:16:54 -0800 Subject: [PATCH] CTC Refactoring --- Source/Apps/Tune/Tune.asm | 7 +- Source/HBIOS/Config/RCZ80_kio.asm | 1 + Source/HBIOS/cfg_ezz80.asm | 3 + Source/HBIOS/cfg_master.asm | 3 + Source/HBIOS/cfg_rcz180.asm | 2 + Source/HBIOS/cfg_rcz80.asm | 3 + Source/HBIOS/cfg_sbc.asm | 4 +- Source/HBIOS/cfg_scz180.asm | 2 + Source/HBIOS/cfg_zeta2.asm | 1 + Source/HBIOS/ctc.asm | 126 ++++++++++++++ Source/HBIOS/ctcstub.asm | 20 --- Source/HBIOS/hbios.asm | 272 ++---------------------------- Source/HBIOS/sio.asm | 38 +++++ Source/HBIOS/std.asm | 8 + 14 files changed, 205 insertions(+), 285 deletions(-) create mode 100644 Source/HBIOS/ctc.asm delete mode 100644 Source/HBIOS/ctcstub.asm diff --git a/Source/Apps/Tune/Tune.asm b/Source/Apps/Tune/Tune.asm index 9d5fe6a9..2aec55fc 100644 --- a/Source/Apps/Tune/Tune.asm +++ b/Source/Apps/Tune/Tune.asm @@ -23,11 +23,14 @@ ; - Max Z80 CPU clock is about 8MHz or sound chip will not handle speed. ; - Higher CPU clock speeds are possible on Z180 because extra I/O ; wait states are added during I/O to sound chip. -; - Uses hardware timer support on Z180 processors. Otherwise, a delay -; loop calibrated to CPU speed is used. +; - Uses hardware timer support on systems that support a timer. Otherwise, +; a delay loop calibrated to CPU speed is used. ; - Delay loop is calibrated to CPU speed, but it does not compensate for ; time variations in each quark loop resulting from data decompression. ; An average quark processing time is assumed in each loop. +; - Most sound files originally targeted MSX or ZX Spectrum which used +; 1.7897725 MHz and 1.773400 MHz respectively for the PSG clock. For best +; sound playback, PSG should be run at approx. this clock rate. ;_______________________________________________________________________________ ; ; Change Log: diff --git a/Source/HBIOS/Config/RCZ80_kio.asm b/Source/HBIOS/Config/RCZ80_kio.asm index 45d7637b..d8229e6b 100644 --- a/Source/HBIOS/Config/RCZ80_kio.asm +++ b/Source/HBIOS/Config/RCZ80_kio.asm @@ -39,6 +39,7 @@ SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .SET SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR +SIO0CTCC .SET 0 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 ;SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 08a2a9ac..4d92013b 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -41,6 +41,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_EZ ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT @@ -74,6 +75,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_EZZ80 ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -82,6 +84,7 @@ SIO0BCLK .EQU 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index e8677023..a34ac222 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -59,6 +59,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT @@ -113,6 +114,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -121,6 +123,7 @@ SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index ca3bfb1f..62c5bf8b 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -80,6 +80,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -88,6 +89,7 @@ SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm index 818e0274..9c3ab068 100644 --- a/Source/HBIOS/cfg_rcz80.asm +++ b/Source/HBIOS/cfg_rcz80.asm @@ -40,6 +40,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_RC ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT @@ -83,6 +84,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -91,6 +93,7 @@ SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index 27de79c6..43da5d26 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -38,7 +38,8 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCBASE .EQU $80 ; CTC BASE FOR ECB-ZILOG-PERIPHERALS +CTCMODE .EQU CTCMODE_ZP ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] +CTCBASE .EQU $80 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS @@ -80,6 +81,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 4915200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 8 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 9f8e35ef..3ddae6ae 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -75,6 +75,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO0CTCC .EQU -1 ; SIO 0: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ADIV .EQU 1 ; SIO 0A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) @@ -83,6 +84,7 @@ SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BDIV .EQU 1 ; SIO 0B: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[RC|SMB|ZP|EZZ80] +SIO1CTCC .EQU -1 ; SIO 1: CTC CHANNEL CLOCK SCALER, (0-3), -1 FOR NONE SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ADIV .EQU 1 ; SIO 1A: SERIAL CLOCK DIVIDER, RC2014/SMB=1, ZP=2/4/8/16/32/64/128/256 (X5) diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index f83f0788..03571213 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -41,6 +41,7 @@ KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT +CTCMODE .EQU CTCMODE_Z2 ; CTC MODE: CTCMODE_[ZP|Z2|EZ|RC] CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS ; DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT diff --git a/Source/HBIOS/ctc.asm b/Source/HBIOS/ctc.asm new file mode 100644 index 00000000..7551bed9 --- /dev/null +++ b/Source/HBIOS/ctc.asm @@ -0,0 +1,126 @@ +;___CTC________________________________________________________________________________________________________________ +; +; Z80 CTC +; +; DISPLAY CONFIGURATION DETAILS +;______________________________________________________________________________________________________________________ +; +; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO +; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO +; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO +; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. +; +#IF (INTMODE != 2) + .ECHO "*** ERROR: CTC REQUIRES INTMODE 2!!!\n" + !!! ; FORCE AN ASSEMBLY ERROR +#ENDIF +; +; CONFIGURATION +; +#IF (CTCMODE == CTCMODE_ZP) +CTCPC .EQU CTCC ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCD ; TIMER CHANNEL +CTCTCC .EQU 48 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +#IF (CTCMODE == CTCMODE_Z2) +CTCPC .EQU CTCA ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCB ; TIMER CHANNEL +CTCTCC .EQU 72 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0B ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +#IF (CTCMODE == CTCMODE_EZ) +CTCPC .EQU CTCC ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCD ; TIMER CHANNEL +CTCTCC .EQU 72 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +#IF (CTCMODE == CTCMODE_RC) +CTCPC .EQU CTCC ; PRESCALE CHANNEL +CTCPCC .EQU 0 ; PRESCALE CHANNEL CONSTANT +CTCTC .EQU CTCD ; TIMER CHANNEL +CTCTCC .EQU 144 ; TIMER CHANNEL CONSTANT +CTCTIVT .EQU INT_CTC0D ; TIMER CHANNEL IVT ENTRY +#ENDIF +; +; +; +CTC_PREINIT: + ; SETUP TIMER INTERRUPT IVT SLOT + LD HL,HB_TIMINT ; TIMER INT HANDLER ADR + LD (IVT(CTCTIVT)),HL ; IVT ENTRY FOR TIMER CHANNEL +; + ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR + ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE + ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE + ; IVT CORRESPOND TO CTC CHANNELS A-D + LD A,0 + OUT (CTCBASE),A ; SETUP CTC BASE INT VECTOR +; + ; IN ORDER TO DIVIDE THE CTC INPUT CLOCK DOWN TO THE + ; DESIRED 50 HZ PERIODIC INTERRUPT, WE NEED TO CONFIGURE ONE + ; CTC CHANNEL AS A PRESCALER AND ANOTHER AS THE ACTUAL + ; TIMER INTERRUPT. THE PRESCALE CHANNEL OUTPUT MUST BE WIRED + ; TO THE TIMER CHANNEL TRIGGER INPUT VIA HARDWARE. + LD A,%01010111 ; PRESCALE CHANNEL CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 1=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCPC),A ; SETUP PRESCALE CHANNEL + LD A,CTCPCC ; PRESCALE CHANNEL CONSTANT + OUT (CTCPC),A ; SET PRESCALE CONSTANT + ; + LD A,%11010111 ; TIMER CHANNEL CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 1=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 1=ENABLE INTERRUPTS + OUT (CTCTC),A ; SETUP TIMER CHANNEL + LD A,CTCTCC ; TIMER CHANNEL CONSTANT + OUT (CTCTC),A ; SET TIMER CONSTANT +; + XOR A + RET +; +; +; +CTC_INIT: ; MINIMAL INIT +CTC_PRTCFG: + ; ANNOUNCE PORT + CALL NEWLINE ; FORMATTING + PRTS("CTC: MODE=$") ; FORMATTING +#IF (CTCMODE == CTCMODE_ZP) + PRTS("ZP$") +#ENDIF +#IF (CTCMODE == CTCMODE_Z2) + PRTS("Z2$") +#ENDIF +#IF (CTCMODE == CTCMODE_EZ) + PRTS("EZ$") +#ENDIF +#IF (CTCMODE == CTCMODE_RC) + PRTS("RC$") +#ENDIF +; LD A,(IY) ; DEVICE NUM +; CALL PRTDECB ; PRINT DEVICE NUM + PRTS(" IO=0x$") ; FORMATTING + LD A,CTCBASE ; GET BASE PORT + CALL PRTHEXBYTE ; PRINT BASE PORT +; + XOR A + RET diff --git a/Source/HBIOS/ctcstub.asm b/Source/HBIOS/ctcstub.asm deleted file mode 100644 index 4551502e..00000000 --- a/Source/HBIOS/ctcstub.asm +++ /dev/null @@ -1,20 +0,0 @@ -;___CTC________________________________________________________________________________________________________________ -; -; Z80 CTC STUB -; -; DISPLAY CONFIGURATION DETAILS -;______________________________________________________________________________________________________________________ -; -CTC_INIT: ; MINIMAL INIT -CTC_PRTCFG: - ; ANNOUNCE PORT - CALL NEWLINE ; FORMATTING - PRTS("CTC$") ; FORMATTING -; LD A,(IY) ; DEVICE NUM -; CALL PRTDECB ; PRINT DEVICE NUM - PRTS(": IO=0x$") ; FORMATTING - LD A,CTCBASE ; GET BASE PORT - CALL PRTHEXBYTE ; PRINT BASE PORT -; - XOR A - RET diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 0bc178c4..78097c77 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -1048,11 +1048,6 @@ HB_CPU2: ; #ENDIF ; -#IF (KIOENABLE) - LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN - OUT (KIOBASE+$0E),A ; DO IT -#ENDIF -; #IF (INTMODE == 2) ; SETUP Z80 IVT AND INT MODE 2 LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS @@ -1077,262 +1072,16 @@ HB_CPU2: #ENDIF #ENDIF - #IF (CTCENABLE) - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTRIES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; ASSUMING ECB-ZP WITH 4.9125MHz XTAL AND / 8 DIVIDER - ; JUMPER X5 15-16, 9-11 - ; JUMPER X5 PIN 3 (PHI_X) TO X4 PIN 7 (CTC_TG2) - ; JUMPER X4 PIN 8 (CTC_ZC2) TO X4 PIN 9 (CTC_TG3) - ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 614,400Hz - ; CTCD TIME CONSTANT = 48 - ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC - ; WHICH IS 614,400HZ / 256 / 48 = 50HZ - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCC),A ; SETUP CTCC - LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCC),A ; SETUP CTCC TIMER CONSTANT - LD A,%11010111 ; CTCD CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCD),A ; SETUP CTCD - LD A,48 ; CTCD TIMER CONSTANT = 48 - OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT - - #ELSE - .ECHO "*** ERROR: CTC REQUIRES INTMODE 2!!!\n" - !!! ; FORCE AN ASSEMBLY ERROR - #ENDIF - #ENDIF -; -#ENDIF -; -#IF (PLATFORM == PLT_ZETA2) -; -; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO -; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO -; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO -; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. -; - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0B)),HL ; IVT ENTRY FOR CTC0B -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; CTCA IS SLAVED (WIRED) TO TO CTCB TO ACT AS A PRESCALER - ; CONFIGURE CHANNEL B FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 921,200HZ - ; CTCA TIME CONSTANT = 256 - ; CTCB TIME CONSTANT = 72 - ; INT FREQ IS CTC CLK / CTCA TC / CTCB TC - ; WHICH IS 921,600HZ / 256 / 72 = 50HZ - LD A,%01010111 ; CTCA CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCA),A ; SETUP CTCA - LD A,0 ; CTCA TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCA),A ; SETUP CTCA TIMER CONSTANT - LD A,%11010111 ; CTCB CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCB),A ; SETUP CTCB - LD A,72 ; CTCB TIMER CONSTANT = 72 - OUT (CTCB),A ; SETUP CTCB TIMER CONSTANT - #ENDIF -; -#ENDIF -; -#IF (PLATFORM == PLT_EZZ80) -; -; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO -; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO -; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO -; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. -; - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER - ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 921,200HZ - ; CTCC TIME CONSTANT = 256 - ; CTCD TIME CONSTANT = 72 - ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC - ; WHICH IS 921,600HZ / 256 / 72 = 50HZ - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCC),A ; SETUP CTCC - LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCC),A ; SETUP CTCC TIMER CONSTANT - LD A,%11010111 ; CTCD CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCD),A ; SETUP CTCD - LD A,72 ; CTCD TIMER CONSTANT = 72 - OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT - #ELSE - .ECHO "*** ERROR: EZZ80 REQUIRES INTMODE 2!!!\n" - !!! ; FORCE AN ASSEMBLY ERROR - #ENDIF ; #ENDIF ; -#IF (PLATFORM == PLT_RCZ80) -; -; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO -; AT 1:1 USING CTC CHANNELS A & B. IN OTHER WORDS, IT JUST -; PASSES THE INCOMING TRIGGER OUT AT 1:1. -; - #IF (CTCENABLE == TRUE) -; - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 0=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCA),A ; SETUP CTCC - LD A,1 ; CTCC TIMER CONSTANT = 1 - OUT (CTCA),A ; SETUP CTCC TIMER CONSTANT -; - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 0=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCB),A ; SETUP CTCC - LD A,1 ; CTCC TIMER CONSTANT = 1 - OUT (CTCB),A ; SETUP CTCC TIMER CONSTANT -; -; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO -; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO -; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO -; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT. -; - #IF (INTMODE == 2) -; - ; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT - LD HL,HB_TIMINT ; TIMER INT HANDLER ADR - LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D -; - ; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR - ; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE - ; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE - ; IVT CORRESPOND TO CTC CHANNELS A-D - LD A,0 - OUT (CTCA),A ; SETUP CTC BASE INT VECTOR -; - ; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER - ; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS - ; CTC CLK = 1,843,200HZ - ; CTCC TIME CONSTANT = 256 - ; CTCD TIME CONSTANT = 144 - ; INT FREQ IS CTC CLK / CTCC TC / CTCD TC - ; WHICH IS 1,843,200HZ / 256 / 144 = 50HZ - LD A,%01010111 ; CTCC CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 0=NO INTERRUPTS - OUT (CTCC),A ; SETUP CTCC - LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256 - OUT (CTCC),A ; SETUP CTCA TIMER CONSTANT - LD A,%11010111 ; CTCD CONTROL WORD VALUE - ; |||||||+-- 1=CONTROL WORD FLAG - ; ||||||+--- 1=SOFTWARE RESET - ; |||||+---- 1=TIME CONSTANT FOLLOWS - ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED - ; |||+------ 1=RISING EDGE TRIGGER - ; ||+------- 1=PRESCALER OF 16 (NOT USED) - ; |+-------- 1=COUNTER MODE - ; +--------- 1=ENABLE INTERRUPTS - OUT (CTCD),A ; SETUP CTCD - LD A,144 ; CTCD TIMER CONSTANT = 144 - OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT - #ENDIF -; - #ENDIF +#IF (KIOENABLE) + LD A,%11111001 ; RESET ALL DEVICES, SET DAISYCHAIN + OUT (KIOBASE+$0E),A ; DO IT +#ENDIF ; +#IF (CTCENABLE) + CALL CTC_PREINIT #ENDIF ; #IF (CPUFAM == CPU_Z180) @@ -1712,7 +1461,9 @@ PC_INITTBLLEN .EQU (($ - PC_INITTBL) / 2) ;================================================================================================== ; HB_INITTBL: -;#IF (SPKENABLE & DSRTCENABLE) +#IF (CTCENABLE) + .DW CTC_INIT +#ENDIF #IF (SPKENABLE) .DW SPK_INIT ; AUDIBLE INDICATOR OF BOOT START #ENDIF @@ -1788,9 +1539,6 @@ HB_INITTBL: #IF (UFENABLE) .DW UF_INIT #ENDIF -#IF (CTCENABLE) - .DW CTC_INIT -#ENDIF ; HB_INITTBLLEN .EQU (($ - HB_INITTBL) / 2) ; @@ -3250,7 +2998,7 @@ SIZ_UF .EQU $ - ORG_UF #ENDIF #IF (CTCENABLE) ORG_CTC .EQU $ - #INCLUDE "ctcstub.asm" + #INCLUDE "ctc.asm" SIZ_CTC .EQU $ - ORG_CTC .ECHO "CTC occupies " .ECHO SIZ_CTC diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm index 1d3d8791..31000849 100644 --- a/Source/HBIOS/sio.asm +++ b/Source/HBIOS/sio.asm @@ -158,6 +158,44 @@ SIO_PREINIT2: ; #ENDIF ; +; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO +; AT 1:1 USING CTC CHANNELS A & B. IN OTHER WORDS, IT JUST +; PASSES THE INCOMING TRIGGER OUT AT 1:1. +; +#IF (SIOCNT >= 1) + #IF (SIO0CTCC >= 0) + LD A,%01010111 ; CTCC CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 0=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCA + SIO0CTCC),A ; SETUP CTCC + LD A,1 ; CTC TIMER CONSTANT = 1 + OUT (CTCA + SIO0CTCC),A ; SETUP CTC TIMER CONSTANT + #ENDIF +#ENDIF +; +#IF (SIOCNT >= 2) + #IF (SIO1CTCC >= 0) + LD A,%01010111 ; CTCC CONTROL WORD VALUE + ; |||||||+-- 1=CONTROL WORD FLAG + ; ||||||+--- 1=SOFTWARE RESET + ; |||||+---- 1=TIME CONSTANT FOLLOWS + ; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED + ; |||+------ 1=RISING EDGE TRIGGER + ; ||+------- 0=PRESCALER OF 16 (NOT USED) + ; |+-------- 1=COUNTER MODE + ; +--------- 0=NO INTERRUPTS + OUT (CTCA + SIO1CTCC),A ; SETUP CTCC + LD A,1 ; CTC TIMER CONSTANT = 1 + OUT (CTCA + SIO1CTCC),A ; SETUP CTC TIMER CONSTANT + #ENDIF +#ENDIF +; SIO_PREINIT3: XOR A ; SIGNAL SUCCESS RET ; AND RETURN diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 625c0f98..2f8776e4 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -93,6 +93,14 @@ MID_FD360 .EQU 7 MID_FD120 .EQU 8 MID_FD111 .EQU 9 ; +; ZILOG CTC MODE SELECTIONS +; +CTCMODE_NONE .EQU 0 ; NO CTC +CTCMODE_ZP .EQU 1 ; ZILOG PERIPHERALS ECB CTC +CTCMODE_Z2 .EQU 2 ; ZETA2 ONBOARD CTC +CTCMODE_EZ .EQU 3 ; EASY Z80 ONBOARD CTC +CTCMODE_RC .EQU 4 ; RC2014 CTC MODULE (ALSO KIO) +; ; DS RTC MODE SELECTIONS ; DSRTCMODE_NONE .EQU 0 ; NO DSRTC