From 915552fed821d295407ab4b107566a57e2c084e0 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 9 Nov 2025 12:15:36 -0800 Subject: [PATCH] S100 Config Cleanup --- Source/HBIOS/Config/SZ180_std.asm | 5 +- Source/HBIOS/Config/SZ80_std.asm | 4 ++ Source/HBIOS/Config/SZ80_t35.asm | 9 ++-- Source/HBIOS/cfg_DUO.asm | 2 + Source/HBIOS/cfg_DYNO.asm | 2 + Source/HBIOS/cfg_EPITX.asm | 2 + Source/HBIOS/cfg_EZZ80.asm | 2 + Source/HBIOS/cfg_GMZ180.asm | 2 + Source/HBIOS/cfg_HEATH.asm | 2 + Source/HBIOS/cfg_MBC.asm | 2 + Source/HBIOS/cfg_MK4.asm | 2 + Source/HBIOS/cfg_MON.asm | 2 + Source/HBIOS/cfg_MSX.asm | 2 + Source/HBIOS/cfg_N8.asm | 2 + Source/HBIOS/cfg_NABU.asm | 2 + Source/HBIOS/cfg_RCEZ80.asm | 2 + Source/HBIOS/cfg_RCZ180.asm | 4 +- Source/HBIOS/cfg_RCZ280.asm | 2 + Source/HBIOS/cfg_RCZ80.asm | 4 +- Source/HBIOS/cfg_RPH.asm | 2 + Source/HBIOS/cfg_SBC.asm | 2 + Source/HBIOS/cfg_SCZ180.asm | 2 + Source/HBIOS/cfg_SZ180.asm | 74 +++++++++++----------------- Source/HBIOS/cfg_SZ80.asm | 82 +++---------------------------- Source/HBIOS/cfg_Z80RETRO.asm | 2 + Source/HBIOS/cfg_ZETA.asm | 2 + Source/HBIOS/cfg_ZETA2.asm | 2 + 27 files changed, 96 insertions(+), 126 deletions(-) diff --git a/Source/HBIOS/Config/SZ180_std.asm b/Source/HBIOS/Config/SZ180_std.asm index 10b1b999..9756ecdb 100644 --- a/Source/HBIOS/Config/SZ180_std.asm +++ b/Source/HBIOS/Config/SZ180_std.asm @@ -57,10 +57,13 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 3 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; -DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) ; ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +PLDSERENABLE .SET TRUE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) +SCCENABLE .SET TRUE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +SCC0ACFG .SET SER_19200_8N1 ; SCC 0A: SERIAL LINE CONFIG +SCC0BCFG .SET SER_19200_8N1 ; SCC 0B: SERIAL LINE CONFIG SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) ; IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) diff --git a/Source/HBIOS/Config/SZ80_std.asm b/Source/HBIOS/Config/SZ80_std.asm index 5aa865a3..8cc33832 100644 --- a/Source/HBIOS/Config/SZ80_std.asm +++ b/Source/HBIOS/Config/SZ80_std.asm @@ -55,6 +55,10 @@ MEMMGR .SET MM_SZ80 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ51 FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS FPLED_IO .SET $05 ; FP: PORT ADDRESS FOR FP LEDS ; +PLDSERENABLE .SET TRUE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) +SCCENABLE .SET TRUE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) ; ESPSDENABLE .SET TRUE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) diff --git a/Source/HBIOS/Config/SZ80_t35.asm b/Source/HBIOS/Config/SZ80_t35.asm index 88cf1bf6..564abd78 100644 --- a/Source/HBIOS/Config/SZ80_t35.asm +++ b/Source/HBIOS/Config/SZ80_t35.asm @@ -42,30 +42,31 @@ ; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; -#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES +#DEFINE PLATFORM_NAME "S100 TRION Z80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED -#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION +#DEFINE DEFSERCFG SER_19200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION ; #INCLUDE "cfg_SZ80.asm" ; CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80] ; FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS ; DS5RTCENABLE .SET TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; +PLDSERENABLE .SET TRUE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) TSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SCCENABLE .SET TRUE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) ; LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) ; TVGAENABLE .SET TRUE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -; PPIDECNT .SET 3 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP PPIDE0MODE .SET PPIDEMODE_STD ; PPIDE 0: DRIVER MODE: IDEMODE_[STD|S100A|S100B] PPIDE0BASE .SET $30 ; PPIDE 0: PPI REGISTERS BASE ADR diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm index 642ef42b..34b781d1 100644 --- a/Source/HBIOS/cfg_DUO.asm +++ b/Source/HBIOS/cfg_DUO.asm @@ -229,6 +229,8 @@ SIO0BCLK .SET (7372800/4) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7 SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm index 83e5f6b4..f1c8a60a 100644 --- a/Source/HBIOS/cfg_DYNO.asm +++ b/Source/HBIOS/cfg_DYNO.asm @@ -248,6 +248,8 @@ SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm index cc0d9795..f088e2cd 100644 --- a/Source/HBIOS/cfg_EPITX.asm +++ b/Source/HBIOS/cfg_EPITX.asm @@ -244,6 +244,8 @@ SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm index e64f1e78..6d390851 100644 --- a/Source/HBIOS/cfg_EZZ80.asm +++ b/Source/HBIOS/cfg_EZZ80.asm @@ -253,6 +253,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm index 5f054879..f1522dfc 100644 --- a/Source/HBIOS/cfg_GMZ180.asm +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -243,6 +243,8 @@ SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index 5e10cbd8..d1654feb 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -253,6 +253,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm index c94574ed..88142215 100644 --- a/Source/HBIOS/cfg_MBC.asm +++ b/Source/HBIOS/cfg_MBC.asm @@ -222,6 +222,8 @@ SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7 SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm index b1c424d7..37cbb121 100644 --- a/Source/HBIOS/cfg_MK4.asm +++ b/Source/HBIOS/cfg_MK4.asm @@ -233,6 +233,8 @@ SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7 SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm index 989fdecc..810264aa 100644 --- a/Source/HBIOS/cfg_MON.asm +++ b/Source/HBIOS/cfg_MON.asm @@ -250,6 +250,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_MSX.asm b/Source/HBIOS/cfg_MSX.asm index dc318ce8..a96a7d1f 100644 --- a/Source/HBIOS/cfg_MSX.asm +++ b/Source/HBIOS/cfg_MSX.asm @@ -256,6 +256,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm index 3ffd3862..97248512 100644 --- a/Source/HBIOS/cfg_N8.asm +++ b/Source/HBIOS/cfg_N8.asm @@ -235,6 +235,8 @@ SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7 SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm index 21262f6c..0684a188 100644 --- a/Source/HBIOS/cfg_NABU.asm +++ b/Source/HBIOS/cfg_NABU.asm @@ -253,6 +253,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm index 57bff2e3..9d2f16b6 100644 --- a/Source/HBIOS/cfg_RCEZ80.asm +++ b/Source/HBIOS/cfg_RCEZ80.asm @@ -251,6 +251,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index bc8080d7..4b05b6a0 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -146,7 +146,7 @@ KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS ; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) ; @@ -248,6 +248,8 @@ SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index c92426c7..5da29efd 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -258,6 +258,8 @@ SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm index dcdc2d4c..4b92aa26 100644 --- a/Source/HBIOS/cfg_RCZ80.asm +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -149,7 +149,7 @@ KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS ; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) ; @@ -256,6 +256,8 @@ SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=73728 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm index d90cd71a..521ad9b2 100644 --- a/Source/HBIOS/cfg_RPH.asm +++ b/Source/HBIOS/cfg_RPH.asm @@ -221,6 +221,8 @@ ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ; SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm index ea5ab104..a41e3c88 100644 --- a/Source/HBIOS/cfg_SBC.asm +++ b/Source/HBIOS/cfg_SBC.asm @@ -223,6 +223,8 @@ SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7 SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm index a6807315..b1ef1195 100644 --- a/Source/HBIOS/cfg_SCZ180.asm +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -248,6 +248,8 @@ SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_SZ180.asm b/Source/HBIOS/cfg_SZ180.asm index c39bfa03..aba96380 100644 --- a/Source/HBIOS/cfg_SZ180.asm +++ b/Source/HBIOS/cfg_SZ180.asm @@ -42,7 +42,7 @@ ; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT ; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; -#DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES +#DEFINE PLATFORM_NAME "S100 Z180", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED #DEFINE DEFSERCFG SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION @@ -94,9 +94,6 @@ KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .SET $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .SET $88 ; CTC BASE I/O ADDRESS -CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER ; @@ -107,17 +104,17 @@ SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] ; FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_IO .SET $FF ; FP: PORT ADDRESS FOR FP LEDS FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_IO .SET $FF ; FP: PORT ADDRESS FOR FP SWITCHES FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED ; DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING ; LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .SET LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU] +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] LEDPORT .SET $0E ; STATUS LED PORT ADDRESS LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; @@ -146,7 +143,7 @@ KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS ; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) ; @@ -169,13 +166,6 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) -SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG -SSERSTATUS .SET $FF ; SSER: STATUS PORT -SSERDATA .SET $FF ; SSER: DATA PORT -SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK -SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED -SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK -SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED ; PLDSERENABLE .SET FALSE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) PLDSERCFG .SET SER_9600_8N1 ; PLDSER: SERIAL LINE CONFIG @@ -227,26 +217,28 @@ Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ; SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +SCCDEBUG .SET FALSE ; SCC: ENABLE DEBUG OUTPUT +SCCBOOT .SET 0 ; SCC: REBOOT ON RCV CHAR (0=DISABLED) +SCCCNT .SET 1 ; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SCCINTS .SET FALSE ; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3 +SCC0MODE .SET SCCMODE_SZ80 ; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80] +SCC0BASE .SET $A0 ; SCC 0: REGISTERS BASE ADR +SCC0ACLK .SET 4915200 ; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC0ACFG .SET DEFSERCFG ; SCC 0A: SERIAL LINE CONFIG +SCC0ACTCC .SET -1 ; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC0BCLK .SET 4915200 ; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC0BCFG .SET DEFSERCFG ; SCC 0B: SERIAL LINE CONFIG +SCC0BCTCC .SET -1 ; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC1MODE .SET SCCMODE_SZ80 ; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80] +SCC1BASE .SET $FF ; SCC 1: REGISTERS BASE ADR +SCC1ACLK .SET 4915200 ; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC1ACFG .SET DEFSERCFG ; SCC 1A: SERIAL LINE CONFIG +SCC1ACTCC .SET -1 ; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC1BCLK .SET 4915200 ; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC1BCFG .SET DEFSERCFG ; SCC 1B: SERIAL LINE CONFIG +SCC1BCTCC .SET -1 ; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; @@ -317,7 +309,7 @@ PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .SET FALSE ; PPIDE 2B (SLAVE): 8 BIT XFER ; -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|T35|GM|EZ512|K80W] SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY @@ -341,7 +333,7 @@ PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] +LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014|T35] LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR @@ -384,15 +376,8 @@ PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .SET SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] ; AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT ; SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) ; @@ -401,4 +386,3 @@ DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) ; YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm index dc6df980..4b4a813e 100644 --- a/Source/HBIOS/cfg_SZ80.asm +++ b/Source/HBIOS/cfg_SZ80.asm @@ -45,7 +45,7 @@ #DEFINE PLATFORM_NAME "S100 Z80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED -#DEFINE DEFSERCFG SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION +#DEFINE DEFSERCFG SER_19200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION ; #INCLUDE "cfg_MASTER.asm" ; @@ -87,31 +87,21 @@ KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT KIOBASE .SET $80 ; KIO BASE I/O ADDRESS ; CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .SET $88 ; CTC BASE I/O ADDRESS -CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER -CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) -CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K ; WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -WDOGIO .SET $6E ; WATCHDOG REGISTER ADR ; FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS FPLED_IO .SET $FF ; FP: PORT ADDRESS FOR FP LEDS FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_IO .SET $FF ; FP: PORT ADDRESS FOR FP SWITCHES FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED ; DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING @@ -169,15 +159,8 @@ DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) ; SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) -SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG -SSERSTATUS .SET $34 ; SSER: STATUS PORT -SSERDATA .SET $35 ; SSER: DATA PORT -SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK -SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED -SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK -SSEROINV .SET TRUE ; SSER: OUTPUT READY BIT INVERTED -; -PLDSERENABLE .SET TRUE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) +; +PLDSERENABLE .SET FALSE ; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM) PLDSERCFG .SET SER_9600_8N1 ; PLDSER: SERIAL LINE CONFIG ; TSERENABLE .SET FALSE ; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM) @@ -220,40 +203,10 @@ ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) ; ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) ; SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -SCCENABLE .SET TRUE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) SCCDEBUG .SET FALSE ; SCC: ENABLE DEBUG OUTPUT SCCBOOT .SET 0 ; SCC: REBOOT ON RCV CHAR (0=DISABLED) SCCCNT .SET 1 ; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP @@ -286,7 +239,7 @@ TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) ; @@ -353,16 +306,6 @@ SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 ; CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK -CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK ; PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) ; @@ -407,8 +350,8 @@ SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ ; ESPSDENABLE .SET TRUE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) ESPSDTRACE .SET 1 ; ESPSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -ESPSDCNT .SET 1 ; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD ESPSD_USECD .SET TRUE ; ESPSD: ENABLE CARD DETECT SIGNAL USAGE +ESPSDCNT .SET 1 ; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD ESPSD0BASE .SET $80 ; ESPSD 0: ESP32 INTERFACE IO BASE ADR ESPSD0DUAL .SET TRUE ; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD) ESPSD1BASE .SET $82 ; ESPSD 1: ESP32 INTERFACE IO BASE ADR @@ -421,20 +364,11 @@ PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) ; SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] ; AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT ; SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) ; DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) ; YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm index ec3b8ded..28d3a0fc 100644 --- a/Source/HBIOS/cfg_Z80RETRO.asm +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -228,6 +228,8 @@ SIO1BCLK .SET CPUOSC/2 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm index 8a472c66..283da8b9 100644 --- a/Source/HBIOS/cfg_ZETA.asm +++ b/Source/HBIOS/cfg_ZETA.asm @@ -197,6 +197,8 @@ ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ; SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm index 85a0d067..f2e126b0 100644 --- a/Source/HBIOS/cfg_ZETA2.asm +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -208,6 +208,8 @@ ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) ; SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; +SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)