diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index f8146f48..0e4b9e30 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1802,30 +1802,34 @@ HB_CPUSPD2:
 ; THAT SUPPORT SOFTWARE SELECTABLE CPU SPEED.  UPDATE CB_CPUKHZ
 ; IN HCB AS WE DO THIS.
 ;
-#IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_MBC) & (CPUSPDDEF==SPD_HIGH))
+#IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_MBC))
+  #IF (CPUSPDDEF==SPD_HIGH)
 	; SET HIGH SPEED VIA RTC LATCH
 	LD	A,(HB_RTCVAL)
 	OR	%00001000		; SET HI SPEED BIT
 	LD	(HB_RTCVAL),A		; SAVE SHADOW
 	OUT	(RTCIO),A		; IMPLEMENT
 	; HL IS ALREADY CORRECT FOR FULL SPEED OPERATION
-#ELSE
+  #ELSE
 	; ADJUST HL TO REFLECT HALF SPEED OPERATION
 	SRL	H		; ADJUST HL ASSUMING
 	RR	L		; HALF SPEED OPERATION
+  #ENDIF
 #ENDIF
 ;
-#IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_SBC) & (CPUSPDDEF==SPD_HIGH))
+#IF ((CPUSPDCAP==SPD_HILO) & (PLATFORM==PLT_SBC))
+  #IF (CPUSPDDEF==SPD_HIGH)
 	; SET HIGH SPEED VIA RTC LATCH
 	LD	A,(HB_RTCVAL)
 	AND	~%00001000		; CLEAR HI SPEED BIT
 	LD	(HB_RTCVAL),A		; SAVE SHADOW
 	OUT	(RTCIO),A		; IMPLEMENT
 	; HL IS ALREADY CORRECT FOR FULL SPEED OPERATION
-#ELSE
+  #ELSE
 	; ADJUST HL TO REFLECT HALF SPEED OPERATION
 	SRL	H		; ADJUST HL ASSUMING
 	RR	L		; HALF SPEED OPERATION
+  #ENDIF
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
diff --git a/Source/ver.inc b/Source/ver.inc
index 0ed9e30c..6c0cd517 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.153"
+#DEFINE BIOSVER	"3.1.1-pre.154"
diff --git a/Source/ver.lib b/Source/ver.lib
index 06000c8a..661456a8 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.153"
+	db	"3.1.1-pre.154"
 	endm