diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 43255017..e5f3174d 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -82,6 +82,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index b247529f..0cfa36dc 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -83,6 +83,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 3b0b428b..0618dadb 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -114,6 +114,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 892f05bc..7bfb167c 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -89,6 +89,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index 3948fc0e..3e70cf78 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -92,6 +92,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index a2f45aad..5715c783 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -85,6 +85,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index bd0e0281..653e282a 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -90,6 +90,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 5c2a0c7a..e529f743 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -84,6 +84,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 967b196d..de34c10f 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -84,6 +84,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index b6fe1c51..74976cdf 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -80,6 +80,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 6eca0583..e5eff0d2 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -72,6 +72,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 5be06627..cec7ef24 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -83,6 +83,8 @@ BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
 ;
 INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
+RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+;
 HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
 SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index f214d920..b4e0c6c5 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -327,13 +327,13 @@ HBX_INVOKE:
 ;
 	LD	A,(HB_CURBNK)		; GET CURRENT BANK
 	LD	(HB_INVBNK),A		; SAVE INVOCATION BANK
-;	
+;
 	LD	A,BID_BIOS		; HBIOS BANK
 	LD	(HB_CURBNK),A		; SET AS CURRENT BANK
 ;
 	.DB	$ED,$71			; SC
 	.DW	HB_DISPATCH		; SC PARAMETER
-;	
+;
 	PUSH	AF
 	LD	A,(HB_INVBNK)
 	LD	(HB_CURBNK),A
@@ -788,7 +788,7 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 ; SYSTEM OR USER MODE WAS ACTIVE AT THE TIME OF THE INTERRUPT.
 ;
 	EX	(SP),HL			; SAVE HL AND GET INT JP TABLE OFFSET
-	
+
 	; SAVE STATE (HL SAVED PREVIOUSLY ON ORIGINAL STACK FRAME)
 	PUSH	AF			; SAVE AF
 	PUSH	BC			; SAVE BC
@@ -814,7 +814,7 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 	CALL	HBX_RETI		; RETI FOR Z80 PERIPHERALS
 	RETIL
 ;
-HBX_RETI:	
+HBX_RETI:
 	RETI
 ;
   #ELSE
@@ -859,7 +859,7 @@ HBX_INT_SP	.EQU	$ - 2
 	RETI				; AND RETURN
 ;
   #ENDIF
-  
+
 #ENDIF
 ;
 ; SMALL TEMPORARY STACK FOR USE BY HBX_BNKCPY
@@ -1095,13 +1095,13 @@ Z280_BOOTPDRTBL:
 ;
 Z280_INITZ:
 ;
-  #ENDIF 
+  #ENDIF
 ;
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	LDCTL	(C),HL
-;	
+;
 #ENDIF
 ;
 #IF (CPUFAM == CPU_Z180)
@@ -1152,7 +1152,7 @@ Z280_INITZ:
 ;
 	; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
 	LD	A,Z180_CNTR_DEF		; DIV 1280, 14KHZ @ 18MHZ CLK
-	OUT0	(Z180_CNTR),A	
+	OUT0	(Z180_CNTR),A
   #ENDIF
 ;
 #ENDIF
@@ -1738,7 +1738,7 @@ NOT_REC_M0:
 ;
 	XOR	A			; FAILSAFE VALUE FOR BOOT CONSOLE DEVICE
 	LD	(CB_CONDEV),A		; SAVE IT
-;	
+;
 	LD	A,(CIO_CNT)		; GET COUNT OF CHAR DEVICES
 	CP	BOOTCON	+ 1		; COUNT - (DEVICE + 1)
 	JR	C,HB_CONRDY		; IF TOO HIGH, JUST USE FAILSAFE
@@ -1881,7 +1881,7 @@ HB_Z280BUS1:
 ; DISPLAY CPU CONFIG
 ;
 	CALL	NEWLINE
-	
+
 #IF (CPUFAM == CPU_Z280)
 	LD	A,Z280_MEMLOWAIT
 	CALL	PRTDECB
@@ -2285,6 +2285,9 @@ HB_INITTBL:
 	.DW	PCF8584_INIT
 	.DW	DS7RTC_INIT
 #ENDIF
+#IF (RP5RTCENABLE)
+	.DW	RP5RTC_INIT
+#ENDIF
 #IF (VDUENABLE)
 	.DW	VDU_INIT
 #ENDIF
@@ -2963,7 +2966,7 @@ SYS_RESINT:
 ;
 SYS_RESWARM:
 	CALL	SYS_RESINT
-;	
+;
 #IF (MEMMGR == MM_Z280)
 	JP	INITSYS4
 #ELSE
@@ -3909,13 +3912,13 @@ Z280_PRIVINST:
 	LD	(HB_MSRSAV),HL		; SAVE IT
 	POP	HL			; RECOVER HL, POP STACK
 	EX	(SP),HL			; GET ADR, SAVE HL
-;	
+;
 	PUSH	AF
 	PUSH	BC
 	PUSH	DE
-;	
+;
 	.DB	$ED,$96			; LDUP	A,(HL)
-;	
+;
 	; HANDLE DI
 	CP	$F3			; DI?
 	JR	NZ,Z280_PRIVINST2
@@ -4251,7 +4254,7 @@ Z280_BNKSEL:
 	PUSH	HL			; SAVE IT
 	LD	L,$FF			; NEW I/O PAGE
 	LDCTL	(C),HL
-;  
+;
 	; CONVERT BANK ID TO TOP 12 BITS OF PHYSICAL ADDRESS
 	; WITH $0A IN THE LOW ORDER NIBBLE:
 	; BANK ID: R000 BBBB
@@ -4263,7 +4266,7 @@ Z280_BNKSEL:
 	JR	Z,Z280_BNKSEL2		; IF NOT, ALL DONE
 	RES	6,H			; OTHERWISE, MOVE RAM BIT
 	SET	RAMLOC-16,H		; HL=0000 RBBB B000 0000
-;	
+;
 Z280_BNKSEL2:
 ;
 	; SET LOW NIBBLE
@@ -4332,19 +4335,19 @@ Z280_BNKCPY:
 ;
 	PUSH	BC			; SAVE COUNT
 	PUSH	HL			; SAVE SOURCE ADDRESS
-;	
+;
 	; SELECT I/O PAGE $FF
 	LD	C,Z280_IOPR		; I/O PAGE REGISTER
 	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	LD	(IOPRVAL),HL		; SAVE IT
 	LD	L,$FF			; I/O PAGE $FF
 	LDCTL	(C),HL
-;	
+;
 	LD	C,Z280_DMA0_DSTL	; START WITH DEST REG LO
 ;
 	LD	A,(HB_DSTBNK)		; DEST BANK TO ACCUM
 	CALL	Z2DMAADR		; SETUP DEST ADR REGS
-;	
+;
 	POP	DE			; SRC ADR TO DE
 	LD	A,(HB_SRCBNK)		; DEST BANK TO ACCUM
 	CALL	Z2DMAADR		; SETUP SOURCE ADR REGS
@@ -4399,7 +4402,7 @@ Z2DMAADR1:
 	LD	A,$0F			; A=0000 1111
 	OR	L			; A=BAAA 1111
 	LD	L,A			; L=BAAA 1111
-;	
+;
 	; MOVE THE RAM/ROM BIT.
 	; RC2014 DMA HI=0000 RBBB BAAA 1111 LO=1111 AAAA AAAA AAAA
 	; ZZ80MB DMA HI=R000 0BBB BAAA 1111 LO=1111 AAAA AAAA AAAA
@@ -4425,7 +4428,7 @@ Z2DMAADR2:
 	POP	HL			; RECOVER THE HI VAL
 	OUTW	(C),HL
 	INC	C			; BUMP TO NEXT REG
-;	
+;
 	RET
 #ENDIF
 ;
@@ -4499,6 +4502,14 @@ SIZ_INTRTC	.EQU	$ - ORG_INTRTC
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (RP5RTCENABLE)
+ORG_RP5RTC	.EQU	$
+  #INCLUDE "rp5rtc.asm"
+SIZ_RP5RTC	.EQU	$ - ORG_RP5RTC
+		.ECHO	"RP5RTC occupies "
+		.ECHO	SIZ_RP5RTC
+		.ECHO	" bytes.\n"
+#ENDIF
 #IF (ASCIENABLE)
 ORG_ASCI	.EQU	$
   #INCLUDE "asci.asm"
@@ -4944,7 +4955,7 @@ SYSCHK:
 	CP	DL_ERROR		; >= ERROR LEVEL
 	JR	C,SYSCHK1		; IF NOT, GO HOME
 	POP	AF			; RESTORE INCOMING AF VALUE
-;	
+;
 	; DISPLAY SYSCHK MESSAGE
 	PUSH	DE			; PRESERVE DE VALUE
 	LD	DE,STR_SYSCHK		; POINT TO PREFIX STRING
@@ -5151,7 +5162,7 @@ PS_PRTDC:
 	CP	5			; RAM DISK?
 	JR	Z,PS_PRTDC1		; PRINT CAPACITY IN KB
 	CP	7			; FLASH DISK?
-	JR	Z,PS_PRTDC1		; PRINT CAPACITY IN KB	
+	JR	Z,PS_PRTDC1		; PRINT CAPACITY IN KB
 ;
 	; PRINT HARD DISK STORAGE SIZE IN MB
 	LD	B,BF_DIOCAP		; HBIOS FUNC: GET CAPACTIY
@@ -5416,8 +5427,8 @@ PS_SOUND:
 	PRTS("    $")			; PAD TO NEXT COLUMN
 
 	; DEVICE COLUMN
-	
-	PUSH	BC			; 
+
+	PUSH	BC			;
 	LD	E,C
 	XOR	A
 	LD	DE,PS_SDSND		; POINT TO DEVICE TYPE NAME TABLE
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index b52536d8..78678921 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -131,7 +131,7 @@ ERR_RANGE		.EQU	-6	; PARAMETER OUT OF RANGE
 ERR_NOMEDIA		.EQU	-7	; MEDIA NOT PRESENT
 ERR_NOHW		.EQU	-8	; HARDWARE NOT PRESENT
 ERR_IO			.EQU	-9	; I/O ERROR
-ERR_READONLY		.EQU	-10	; WRITE REQUEST TO READ-ONLY MEDIA	
+ERR_READONLY		.EQU	-10	; WRITE REQUEST TO READ-ONLY MEDIA
 ERR_TIMEOUT		.EQU	-11	; DEVICE TIMEOUT
 ERR_BADCFG		.EQU	-12	; INVALID CONFIGURATION
 ERR_INTERNAL		.EQU	-13	; INTERNAL ERROR
@@ -191,6 +191,7 @@ RTCDEV_BQ	.EQU	$10		; BQ4845P
 RTCDEV_SIMH	.EQU	$20		; SIMH
 RTCDEV_INT	.EQU	$30		; PERIODIC INT TIMER
 RTCDEV_DS7	.EQU	$40		; DS1302 (I2C)
+RTCDEV_RP5	.EQU	$50		; RP5C01
 ;
 ; VIDEO DEVICE IDS
 ;
diff --git a/Source/HBIOS/rp5rtc.asm b/Source/HBIOS/rp5rtc.asm
new file mode 100644
index 00000000..f4b83abf
--- /dev/null
+++ b/Source/HBIOS/rp5rtc.asm
@@ -0,0 +1,203 @@
+;
+;==================================================================================================
+; RP5C01 CLOCK DRIVER
+;==================================================================================================
+;
+RP5RTC_BUFSIZ	.EQU	6	; SIX BYTE BUFFER (YYMMDDHHMMSS)
+;
+; RTC DEVICE INITIALIZATION ENTRY
+;
+
+RP5RTC_REG	.EQU	$B4
+RP5RTC_DAT	.EQU	$B5
+
+REG_1SEC	.EQU	$00
+REG_10SEC	.EQU	$01
+REG_MODE	.EQU	$0D
+REG_TEST	.EQU	$0E
+
+MD_TIM	.EQU	8
+MD_ALM	.EQU	4
+
+RP5RTC_INIT:
+	LD	A,(RTC_DISPACT)		; RTC DISPATCHER ALREADY SET?
+	OR	A			; SET FLAGS
+	RET	NZ			; IF ALREADY ACTIVE, ABORT
+;
+	CALL	NEWLINE		; FORMATTING
+	PRTS("RP5C01 RTC: $")
+;
+
+;	ENSURE DEVICE IS RESET AND NOT IN TEST MODE
+	LD	A, REG_TEST			; SELECT TEST REGISTER
+	OUT	(RP5RTC_REG), A
+	CALL	DLY16
+	XOR	A
+	OUT	(RP5RTC_DAT), A			; TURN OFF ALL TEST MODE BITS
+
+	CALL	RP5RTC_RDTIM
+
+	; DISPLAY CURRENT TIME
+	LD	HL, RP5RTC_BCDBUF	; POINT TO BCD BUF
+	CALL	PRTDT
+;
+	LD	BC, RP5RTC_DISPATCH
+	CALL	RTC_SETDISP
+;
+	XOR	A		; SIGNAL SUCCESS
+	RET
+;
+; RTC DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+RP5RTC_DISPATCH:
+	LD	A,B		; GET REQUESTED FUNCTION
+	AND	$0F		; ISOLATE SUB-FUNCTION
+	JP	Z,RP5RTC_GETTIM	; GET TIME
+	DEC	A
+	JP	Z,RP5RTC_SETTIM	; SET TIME
+	DEC	A
+	JP	Z,RP5RTC_GETBYT	; GET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,RP5RTC_SETBYT	; SET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,RP5RTC_GETBLK	; GET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,RP5RTC_SETBLK	; SET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,RP5RTC_GETALM	; GET ALARM
+	DEC	A
+	JP	Z,RP5RTC_SETALM	; SET ALARM
+	DEC	A
+	JP	Z,RP5RTC_DEVICE	; REPORT RTC DEVICE INFO
+	CALL	SYSCHK
+	LD	A,ERR_NOFUNC
+	OR	A
+	RET
+;
+; NVRAM FUNCTIONS ARE NOT AVAILABLE IN SIMULATOR
+;
+RP5RTC_GETBYT:
+RP5RTC_SETBYT:
+RP5RTC_GETBLK:
+RP5RTC_SETBLK:
+RP5RTC_GETALM:
+RP5RTC_SETALM:
+	CALL	SYSCHK
+	LD	A,ERR_NOTIMPL
+	OR	A
+	RET
+;
+; RTC GET TIME
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: DATE/TIME BUFFER (OUT)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+RP5RTC_GETTIM:
+	; GET THE TIME INTO TEMP BUF
+	PUSH	HL			; SAVE PTR TO CALLERS BUFFER
+;
+	CALL	RP5RTC_RDTIM
+
+	; NOW COPY TO REAL DESTINATION (INTERBANK SAFE)
+	LD	A,BID_BIOS		; COPY FROM BIOS BANK
+	LD	(HB_SRCBNK),A		; SET IT
+	LD	A,(HB_INVBNK)		; COPY TO CURRENT USER BANK
+	LD	(HB_DSTBNK),A		; SET IT
+	LD	HL,RP5RTC_BCDBUF	; SOURCE ADR
+	POP	DE			; DEST ADR
+	LD	BC,RP5RTC_BUFSIZ	; LENGTH
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+;
+; RTC SET TIME
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   HL: DATE/TIME BUFFER (IN)
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSSWW
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+RP5RTC_SETTIM:
+	; COPY TO BCD BUF
+	LD	A,(HB_INVBNK)		; COPY FROM CURRENT USER BANK
+	LD	(HB_SRCBNK),A		; SET IT
+	LD	A,BID_BIOS		; COPY TO BIOS BANK
+	LD	(HB_DSTBNK),A		; SET IT
+	LD	DE,RP5RTC_BCDBUF	; DEST ADR
+	LD	BC,RP5RTC_BUFSIZ	; LENGTH
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; REPORT RTC DEVICE INFO
+;
+RP5RTC_DEVICE:
+	LD	D,RTCDEV_RP5		; D := DEVICE TYPE
+	LD	E,0			; E := PHYSICAL DEVICE NUMBER
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,0			; L := 0, NO I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+
+;
+; READ OUT THE TIME
+RP5RTC_RDTIM:
+	LD	A, REG_MODE			; SELECT MODE REGISTER
+	OUT	(RP5RTC_REG), A
+	; CALL	DLY32
+	LD	A, MD_TIM | !MD_ALM | 0		; TURN ON TIME AND TURN OFF ALARM
+	OUT	(RP5RTC_DAT), A			; AND SET MODE 0 (REGISTER BANK 0)
+	; CALL	DLY32
+
+	LD	A, REG_1SEC			; SELECT 1 SECOND REGISTER
+	OUT	(RP5RTC_REG), A
+	; CALL	DLY32
+	IN	A, (RP5RTC_DAT)
+	AND	$0F				; RETRIEVE 1 SECOND NIBBLE
+	LD	L, A
+
+	LD	A, REG_10SEC			; SELECT 1 SECOND REGISTER
+	OUT	(RP5RTC_REG), A
+	; CALL	DLY32
+	IN	A, (RP5RTC_DAT)
+	AND	$0F
+	rlca
+	rlca
+	rlca
+	rlca					; MOVE TO TOP NIBBLE
+	OR	L				; MERGE IN LOW NIBBLE
+	LD	H, A
+						; A = SECONDS AS BCD
+	LD	(RP5RTC_SS), A
+
+	RET
+
+;
+; WORKING VARIABLES
+;
+RP5RTC_BCDBUF:	; ALL IN BINARY
+RP5RTC_YR	.DB	20
+RP5RTC_MO	.DB	01
+RP5RTC_DT	.DB	01
+RP5RTC_HH	.DB	00
+RP5RTC_MM	.DB	00
+RP5RTC_SS	.DB	00
+;;
+RP5RTC_MONTBL:	; DAYS IN MONTH + 1
+		.DB	32	; JANUARY
+		.DB	29	; FEBRUARY (NON-LEAP)
+		.DB	32	; MARCH
+		.DB	31	; APRIL
+		.DB	32	; MAY
+		.DB	31	; JUNE
+		.DB	32	; JULY
+		.DB	32	; AUGUST
+		.DB	31	; SEPTEMBER
+		.DB	32	; OCTOBER
+		.DB	31	; NOVEMBER
+		.DB	32	; DECEMBER