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https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Reintegrate wbw -> trunk
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@@ -15,12 +15,6 @@
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IM 1 ; INTERRUPT MODE 1
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LD SP,$FF00 ; START WITH SP BELOW HBIOS PROXY LOCATION
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;
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; EMIT FIRST SIGN OF LIFE TO SERIAL PORT
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;
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CALL XIO_INIT ; INIT SERIAL PORT
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LD HL,STR_BOOT ; POINT TO MESSAGE
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CALL XIO_OUTS ; SAY HELLO
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;
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; PERFORM MINIMAL Z180 SPECIFIC INITIALIZATION
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;
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#IF (PLATFORM == PLT_N8)
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@@ -45,7 +39,11 @@
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OUT0 (CPU_CBR),A ; COMMON BASE = LAST (TOP) BANK
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#ENDIF
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;
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CALL XIO_DOT
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; EMIT FIRST SIGN OF LIFE TO SERIAL PORT
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;
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CALL XIO_INIT ; INIT SERIAL PORT
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LD HL,STR_BOOT ; POINT TO MESSAGE
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CALL XIO_OUTS ; SAY HELLO
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;
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; COPY ENTIRE CONTENTS OF ROM BANK 0 TO HI RAM
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; THIS INCLUDES OURSELVES AND THE LOADER CODE
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