From 438df9a80b29def81a0384dbbc2475b5c7f2082f Mon Sep 17 00:00:00 2001 From: Les Bird Date: Mon, 15 Apr 2024 20:21:09 -0600 Subject: [PATCH] NABU Personal Computer integration - nabu.asm and nabukb.asm contain code to support the NABU hardware. --- Source/HBIOS/Build.ps1 | 2 +- Source/HBIOS/Config/NABU_std.asm | 29 +++ Source/HBIOS/ay38910.asm | 7 + Source/HBIOS/cfg_nabu.asm | 338 +++++++++++++++++++++++++++++++ Source/HBIOS/hbios.asm | 30 +++ Source/HBIOS/hbios.inc | 1 + Source/HBIOS/nabu.asm | 44 ++++ Source/HBIOS/nabukb.asm | 86 ++++++++ Source/HBIOS/tms.asm | 14 ++ Source/HBIOS/uart.asm | 10 + 10 files changed, 560 insertions(+), 1 deletion(-) create mode 100644 Source/HBIOS/Config/NABU_std.asm create mode 100644 Source/HBIOS/cfg_nabu.asm create mode 100644 Source/HBIOS/nabu.asm create mode 100644 Source/HBIOS/nabukb.asm diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index 41ac2de1..ec8bf51d 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -27,7 +27,7 @@ $ErrorAction = 'Stop' # UNA BIOS is simply imbedded, it is not built here. # -$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON" +$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU" $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX" $PlatformListZ280 = "RCZ280" diff --git a/Source/HBIOS/Config/NABU_std.asm b/Source/HBIOS/Config/NABU_std.asm new file mode 100644 index 00000000..f2bba624 --- /dev/null +++ b/Source/HBIOS/Config/NABU_std.asm @@ -0,0 +1,29 @@ +; +;================================================================================================== +; RCBUS Z80 STANDARD CONFIGURATION +;================================================================================================== +; +; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE +; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS +; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE +; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. +; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY +; YOUR FILE IN THE BUILD PROCESS. +; +; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. +; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO +; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON +; SETTINGS. +; +; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, +; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING +; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO +; DIRECTORIES ABOVE THIS ONE). +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#include "cfg_nabu.asm" +; +CPUOSC .SET 3580000 ; CPU OSC FREQ IN MHZ diff --git a/Source/HBIOS/ay38910.asm b/Source/HBIOS/ay38910.asm index cc8fac44..01ab9c80 100644 --- a/Source/HBIOS/ay38910.asm +++ b/Source/HBIOS/ay38910.asm @@ -54,10 +54,17 @@ AY_RIN .EQU AY_RSEL+AY_RCSND #ENDIF ; #IF (AYMODE == AYMODE_MSX) + #IF (PLATFORM == PLT_NABU) +AY_RSEL .EQU $40 +AY_RDAT .EQU $41 +AY_RIN .EQU AY_RSEL + .ECHO "NABU" + #ELSE AY_RSEL .EQU $A0 AY_RDAT .EQU $A1 AY_RIN .EQU $A2 .ECHO "MSX" + #ENDIF #ENDIF ; #IF (AYMODE == AYMODE_LINC) diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm new file mode 100644 index 00000000..3fe1500a --- /dev/null +++ b/Source/HBIOS/cfg_nabu.asm @@ -0,0 +1,338 @@ +; +;================================================================================================== +; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80 +;================================================================================================== +; +; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD +; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY +; UNDER THIS DIRECTORY. +; +; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS +; FOR THE PLATFORM. +; +#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" +; +#INCLUDE "hbios.inc" +; +PLATFORM .EQU PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] +CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .EQU FALSE ; ENABLE FONT COMPRESSION +TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .EQU 3580000 ; CPU OSC FREQ IN MHZ +INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS +CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) +CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC] +LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL +; +BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE +SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE +CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) +MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] +DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS +UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO ONBOARD UART +UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) +UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART +UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART +UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART +UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART +UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART +UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART +; +ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .EQU TMSMODE_MSX9958 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO] +TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .EQU TRUE ; MD: ENABLE ROM DISK +MDRAM .EQU TRUE ; MD: ENABLE RAM DISK +MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK +CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] +; +AY38910ENABLE .EQU TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .EQU AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO] +; +SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 93b6ec05..86b4b0b9 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -985,6 +985,13 @@ HBX_RETI: PUSH BC ; SAVE BC PUSH DE ; SAVE DE PUSH IY ; SAVE IY +; +#IF (PLATFORM == PLT_NABU) + PUSH HL + LD HL,($FFEA) ; TICCNT COPIED TO... + LD ($000B),HL ; ...LOW MEMORY FOR CP/M + POP HL +#ENDIF ; LD A,BID_BIOS ; HBIOS BANK CALL HBX_BNKSEL_INT ; SELECT IT @@ -2002,6 +2009,10 @@ HB_CPU1: CALL DSKY_DISPATCH #ENDIF ; +#IF (PLATFORM == PLT_NABU) + CALL NABU_PREINIT +#ENDIF +; #IF (SKZENABLE) ; ; SET THE SK Z80-512K UART CLK2 DIVIDER AS @@ -3308,6 +3319,9 @@ HB_INITTBL: .DW H8P_INIT #ENDIF #ENDIF +#IF (PLATFORM == PLT_NABU) + .DW NABU_INIT +#ENDIF #IF (AY38910ENABLE) .DW AY38910_INIT ; AUDIBLE INDICATOR OF BOOT START #ENDIF @@ -6303,6 +6317,22 @@ SIZ_H8P .EQU $ - ORG_H8P #ENDIF #ENDIF ; +#IF (PLATFORM == PLT_NABU) +ORG_NABU .EQU $ + #INCLUDE "nabu.asm" +SIZ_NABU .EQU $ - ORG_NABU + .ECHO "NABU occupies " + .ECHO SIZ_NABU + .ECHO " bytes.\n" +; +ORG_KBD .EQU $ + #INCLUDE "nabukb.asm" +SIZ_KBD .EQU $ - ORG_KBD + .ECHO "NABUKB occupies " + .ECHO SIZ_KBD + .ECHO " bytes.\n" +#ENDIF +; #IF (DSRTCENABLE) ORG_DSRTC .EQU $ #INCLUDE "dsrtc.asm" diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index 64d793a3..9c00f6e2 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -157,6 +157,7 @@ PLT_HEATH .EQU 18 ; HEATHKIT H8 Z80 SYSTEM PLT_EPITX .EQU 19 ; Z180 MINI-ITX PLT_MON .EQU 20 ; MONSPUTER PLT_STDZ180 .EQU 21 ; GENESIS Z180 SYSTEM +PLT_NABU .EQU 22 ; NABU PERSONAL COMPUTER ; ; HBIOS GLOBAL ERROR RETURN VALUES ; diff --git a/Source/HBIOS/nabu.asm b/Source/HBIOS/nabu.asm new file mode 100644 index 00000000..f6453323 --- /dev/null +++ b/Source/HBIOS/nabu.asm @@ -0,0 +1,44 @@ +; +;================================================================================================== +; NABU INTERRUPT INTERCEPTOR +;================================================================================================== +NABU_INT1CLR .EQU $68 +NABU_TICCNT .EQU $FFEA ; TICCNT AT $FFEA IS COPIED DOWN TO $000B +; +; +; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION +; +NABU_PREINIT: + LD HL,NABU_STAT + CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST + RET +; +NABU_INIT: + CALL NEWLINE ; FORMATTING + PRTS("NABU INT1$") + XOR A + OUT (NABU_INT1CLR),A + RET ; DONE +; +; INTERRUPT ENTRY POINT +; +NABU_STAT: + XOR A + OUT (NABU_INT1CLR),A ; CLEAR THE INTERRUPT + LD HL,(NABU_TICCNT) + INC HL + LD (NABU_TICCNT),HL + LD A,(NABU_HBTICK) + INC A + LD (NABU_HBTICK),A + CP $0A ; CALL HB_TICK EVERY 10 INTERRUPTS (50HZ) + RET NZ ; NOT TIME THEN JUST RETURN + CALL HB_TICK + XOR A + LD (NABU_HBTICK),A ; RESET HBTICK COUNTER + INC A ; INTERRUPT HANDLED + RET +; +NABU_HBTICK: + .DB 0 +; diff --git a/Source/HBIOS/nabukb.asm b/Source/HBIOS/nabukb.asm new file mode 100644 index 00000000..508060ee --- /dev/null +++ b/Source/HBIOS/nabukb.asm @@ -0,0 +1,86 @@ +;====================================================================== +; NABU KEYBOARD DRIVER +; +; CREATED BY: LES BIRD +; +;====================================================================== +; +; KBPORT EQU $90 +; +; POLL FOR INPUT +; KBLOOP: +; IN A,(KBPORT+1) +; BIT 1,A +; JR Z,KBLOOP +; IN A,(KBPORT) +; +; INIT: +; XOR A +; CALL SUB12 +; CALL SUB12 +; CALL SUB12 +; CALL SUB12 +; CALL SUB12 +; LD A,40H +; CALL SUB12 +; LD A,4EH +; CALL SUB12 +; LD A,04H +; CALL SUB12 +; +NABUKB_DAT .EQU $90 +; +NABUKB_INIT: + CALL NEWLINE + PRTS("NABUKB: IO=0x$") + LD A,NABUKB_DAT + CALL PRTHEXBYTE +; + XOR A + CALL NABUKB_PUT + CALL NABUKB_PUT + CALL NABUKB_PUT + CALL NABUKB_PUT + CALL NABUKB_PUT + LD A,$40 ; RESET 8251 + CALL NABUKB_PUT + LD A,$4E ; 1 STOP BIT, 8 BITS, 64X CLK + CALL NABUKB_PUT + LD A,$04 ; ENABLE RECV + CALL NABUKB_PUT +; + XOR A + RET +; +NABUKB_STAT: + IN A,(NABUKB_DAT+1) + AND $02 + JP Z,CIO_IDLE + RET +; +NABUKB_FLUSH: + XOR A + RET +; +NABUKB_READ: + IN A,(NABUKB_DAT+1) + AND $02 + JR Z,NABUKB_READ + IN A,(NABUKB_DAT) + LD E,A + CP $80 + JR C,NABUKB_READ1 + LD E,$FF +NABUKB_READ1: + XOR A + RET +; +NABUKB_PUT: + OUT (NABUKB_DAT+1),A + NOP + NOP + NOP + NOP + NOP + RET +; diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm index 5477a104..1614ea70 100644 --- a/Source/HBIOS/tms.asm +++ b/Source/HBIOS/tms.asm @@ -46,8 +46,13 @@ TMSINTEN: .EQU 5 ; INTERRUPT ENABLE BIT .ECHO "TMS: MODE=" ; #IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958)) + #IF (PLATFORM == PLT_NABU) +TMS_DATREG .EQU $A0 ; READ/WRITE DATA +TMS_CMDREG .EQU $A1 ; READ STATUS / WRITE REG SEL + #ELSE TMS_DATREG .EQU $98 ; READ/WRITE DATA TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL + #ENDIF TMS_PPIA .EQU 0 ; PPI PORT A TMS_PPIB .EQU 0 ; PPI PORT B TMS_PPIC .EQU 0 ; PPI PORT C @@ -259,6 +264,9 @@ TMS_INIT1: #IF MKYENABLE CALL MKY_INIT ; INITIALIZE MKY KEYBOARD DRIVER #ENDIF +#IF (PLATFORM == PLT_NABU) + CALL NABUKB_INIT +#ENDIF #IF (INTMODE == 1 & TMSTIMENABLE) ; ADD IM1 INT CALL LIST ENTRY @@ -319,9 +327,15 @@ TMS_FNTBL: .DW MKY_READ #ELSE + #IF (PLATFORM == PLT_NABU) + .DW NABUKB_STAT + .DW NABUKB_FLUSH + .DW NABUKB_READ + #ELSE .DW TMS_STAT .DW TMS_FLUSH .DW TMS_READ + #ENDIF #ENDIF #ENDIF #ENDIF diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm index cd8fe8fb..3d685d34 100644 --- a/Source/HBIOS/uart.asm +++ b/Source/HBIOS/uart.asm @@ -67,6 +67,7 @@ UARTCBASE .EQU $80 UARTMBASE .EQU $18 UART4BASE .EQU $C0 UARTRBASE .EQU $A0 +UARTNBASE .EQU $48 ; #IF (UARTINTS) ; @@ -1185,6 +1186,15 @@ UART_CFG_MFP: ; #ENDIF ; +#IF (PLATFORM == PLT_NABU) + .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) + .DB 0 ; UART TYPE + .DB UARTNBASE ; IO PORT BASE (RBR, THR) + .DB UARTNBASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UARTCFG ; LINE CONFIGURATION + .DW 0 ; SHOULD NEVER NEED INT HANDLER +#ENDIF +; UART_CNT .EQU ($ - UART_CFG) / 8 ; #IF ((!UARTINTS) | (INTMODE == 0))