Merge pull request #176 from wwarthen/dev

Dev

Binary/RomList.txt

@@ -177,44 +177,28 @@ RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom):
  - Support for Scott Baker floppy controllers (SMC & WDC) may
    be enabled in config
  - Support for J.B. Lang TMS9918 video card may be enabled in config
- - You must pick the _nat or _ext variant depending on which
-   memory module you are using:
-   - RCZ180_nat.rom uses the built-in Z180 memory manager
-     for use with memory modules allow direct physical
-     addressing of memory, such as the SC119
+ - You must pick the variant (_ext or _nat) depending
+   on which memory module you are using:
    - RCZ180_ext.rom uses external bank management to access
      memory, such as the 512K RAM/ROM module.
+   - RCZ180_nat.rom uses the built-in Z180 memory manager
+     for use with memory modules using direct physical
+     addressing of memory, such as the SC119.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
    video, keyboard and SD Card support if present.
 
-RCZ280 (RCZ280_ext.rom):
+RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
  - Assumes CPU oscillator of 24 MHz
- - Bus clock will be 6 MHz, so does not match RC2014 standard!!!
- - Requires 512K RAM/ROM module
+ - Bus clock will be 6 MHz or 12 MHz, so does not match RC2014 standard!!!
+ - Requires 512K RAM/ROM module (unless using ZZ80MB)
  - Auto detects Serial I/O Module (ACIA), Dual Serial
-   Module (SIO/2), and EP Dual UART.
+   Module (SIO), EP Dual UART (DUART), and built-in Z280 UART (Z2U).
+ - ACIA module is only supported on _ext variant.
+ - Built-in Z280 UART (Z2U) is buffered and interrupt driven only
+   on _nat and _nat_zz variants.  It uses polling I/O on _ext.
  - Console on whichever serial module is installed,
-   order of priority is UART, SIO, then ACIA.
- - Baud rate is determined by hardware, but normally 115200.
- - Auto support for RC2014 Compact Flash Module
- - Auto support for RC2014 PPIDE Module
- - Support for Scott Baker SIO board may be enabled in config
- - Support for Scott Baker floppy controllers (SMC & WDC) may
-   be enabled in config
- - Support for J.B. Lang TMS9918 video card may be enabled in config
- - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
-   enabled, will auto-detect and install associated
-   video, keyboard and SD Card support if present.
-
-RCZ280 (RCZ280_nat.rom):
- - Assumes CPU oscillator of 24 MHz
- - Bus clock will be 6 MHz, so does not match RC2014 standard!!!
- - Requires native RAM/ROM module (linear memory)
- - Interrupt Mode 3 only (no ACIA support possible)
- - Auto detects Dual Serial Module (SIO/2), and EP Dual UART.
- - Console on whichever serial module is installed,
-   order of priority is UART, then SIO.
+   order of priority is UART, SIO, DUART, ACIA, Z2U
  - Baud rate is determined by hardware, but normally 115200.
  - Auto support for RC2014 Compact Flash Module
  - Auto support for RC2014 PPIDE Module
@@ -222,6 +206,15 @@ RCZ280 (RCZ280_nat.rom):
  - Support for Scott Baker floppy controllers (SMC & WDC) may
    be enabled in config
  - Support for J.B. Lang TMS9918 video card may be enabled in config
+ - You must pick the variant (_ext, _nat, or _nat_zz) depending
+   on which platform or memory module you are using:
+   - RCZ280_ext.rom uses external bank management to access
+     memory, such as the 512K RAM/ROM module.
+   - RCZ280_nat.rom uses the built-in Z280 memory manager
+     for use with memory modules using direct physical
+     addressing of memory, such as the SC119.
+   - RCZ280_nat_zz.rom is specifically for the ZZ80MB platform
+     which has both CPU and memory onboard.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
    video, keyboard and SD Card support if present.

Doc/ChangeLog.txt

@@ -17,6 +17,8 @@ Version 3.1.1
 - WBW: Support for Z280 w/ native memory and interrupt mode 3
 - WBW: Support for Z280 UART (interrupt driven only in interrupt mode 3)
 - WBW: Add support Z80-512K (watchdog and LED)
+- WBW: Add support for ZZ80MB address map
+- PLS: Add support for Z180 invalid opcode trap
 
 Version 3.1
 -----------

Source/Apps/RTC.asm

@@ -39,8 +39,11 @@ PORT_N8		.EQU	$88		; RTC port for N8
 PORT_MK4	.EQU	$8A		; RTC port for MK4
 PORT_RCZ80	.EQU	$C0		; RTC port for RC2014
 PORT_RCZ180	.EQU	$0C		; RTC port for RC2014
-PORT_SCZ180	.EQU	$0C		; RTC port for SBCZ180
 PORT_EZZ80	.EQU	$C0		; RTC port for EZZ80 (actually does not have one!!!)
+PORT_SCZ180	.EQU	$0C		; RTC port for SCZ180
+PORT_DYNO	.EQU	$0C		; RTC port for DYNO
+PORT_RCZ280	.EQU	$C0		; RTC port for RCZ280
+
 
 BDOS		.EQU	5		; BDOS invocation vector
 FCB		.EQU	05CH		; Start of command line
@@ -1075,30 +1078,46 @@ HINIT:
 	JR	Z,RTC_INIT2
 	CP	$03		; ZETA 2
 	JR	Z,RTC_INIT2
+;
 	LD	C,PORT_N8
 	LD	DE,PLT_N8
 	CP	$04		; N8
 	JR	Z,RTC_INIT2
+;
 	LD	C,PORT_MK4
 	LD	DE,PLT_MK4
 	CP	$05		; Mark IV
 	JR	Z,RTC_INIT2
+;
 	LD	C,PORT_RCZ80
 	LD	DE,PLT_RCZ80
 	CP	$07		; RC2014 w/ Z80
 	JR	Z,RTC_INIT2
+;
 	LD	C,PORT_RCZ180
 	LD	DE,PLT_RCZ180
 	CP	$08		; RC2014 w/ Z180
 	JR	Z,RTC_INIT2
+;
+	LD	C,PORT_EZZ80
+	LD	DE,PLT_EZZ80
+	CP	$09		; Easy Z80
+	JR	Z,RTC_INIT2
+;
 	LD	C,PORT_SCZ180
 	LD	DE,PLT_SCZ180
 	CP	$0A		; SCZ180
 	JR	Z,RTC_INIT2
-	;LD	C,PORT_EZZ80
-	;LD	DE,PLT_EZZ80
-	;CP	$09		; Easy Z80
-	;JR	Z,RTC_INIT2
+;
+	LD	C,PORT_DYNO
+	LD	DE,PLT_DYNO
+	CP	11		; DYNO
+	JR	Z,RTC_INIT2
+;
+	LD	C,PORT_RCZ280
+	LD	DE,PLT_RCZ280
+	CP	12		; RCZ280
+	JR	Z,RTC_INIT2
 ;
 	; Unknown platform
 	LD	DE,PLTERR	; BIOS error message
@@ -1719,8 +1738,10 @@ PLT_N8		.TEXT	", N8 RTC Latch Port 0x88\r\n$"
 PLT_MK4		.TEXT	", Mark 4 RTC Latch Port 0x8A\r\n$"
 PLT_RCZ80	.TEXT	", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
 PLT_RCZ180	.TEXT	", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
-PLT_SCZ180	.TEXT	", SC Z180 RTC Module Latch Port 0x0C\r\n$"
 PLT_EZZ80	.TEXT	", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
+PLT_SCZ180	.TEXT	", SC Z180 RTC Module Latch Port 0x0C\r\n$"
+PLT_DYNO	.TEXT	", DYNO RTC Module Latch Port 0x0C\r\n$"
+PLT_RCZ280	.TEXT	", RC2014 Z280 RTC Module Latch Port 0xC0\r\n$"
 
 ;
 ; Generic FOR-NEXT loop algorithm

Source/Apps/Tune/Tune.asm

@@ -64,8 +64,8 @@ TYPMYM		.EQU	3		; FILTYP value for MYM sound file
 ;
 ; HIGH SPEED CPU CONTROL
 ;
-SBCV2004	.EQU	0		; USE SBC-V2-004 HALF CLOCK DIVIDER
-CPUFAMZ180	.EQU	1		; USE Z180 WAIT STATE MANAGEMENT
+SBCV2004	.EQU	0		; ENABLE SBC-V2-004 HALF CLOCK DIVIDER
+CPUFAMZ180	.EQU	1		; ENABLE Z180 WAIT STATE MANAGEMENT
 ;
 ;Conditional assembly - use  -D switch on TASM or uz80as assembler to control
 _ZX		.EQU    0		; 1) Version of ROUT (ZX or MSX standards)
@@ -596,6 +596,15 @@ CFGTBL:	;	PLT	RSEL	RDAT	RIN	Z180	ACR
 ;
 	.DB	$0A,	$61,	$60,	$60,	$C0,	$FF	; SCZ180 W/ RC SOUND MODULE (MF)
 	.DW	HWSTR_RCMF
+;
+	.DB	$0B,	$D8,	$D0,	$D8,	$FF,	$FF	; RCZ280 W/ RC SOUND MODULE (EB)
+	.DW	HWSTR_RCEB
+;
+	.DB	$0B,	$A0,	$A1,	$A2,	$FF,	$FF	; RCZ280 W/ RC SOUND MODULE (EB Rev 6)
+	.DW	HWSTR_RCEB6
+;
+	.DB	$0B,	$D1,	$D0,	$D0,	$FF,	$FF	; RCZ280 W/ RC SOUND MODULE (MF)
+	.DW	HWSTR_RCMF
 ;
 	.DB	$FF					; END OF TABLE MARKER
 ;
@@ -2478,10 +2487,6 @@ upsg:
 	ERRWITHMSG(MSGERR)
 
 upsg0:
-	ld	a,(WMOD)	; if WMOD = 1, CPU is z180
-	or	a		; set flags
-	jr	z,upsg1		; skip z180 stuff
-
 	di
 	call	SLOWIO
 

Source/Build.cmd

@@ -6,4 +6,5 @@ setlocal & call BuildProp || exit /b 1 & endlocal
 setlocal & call BuildShared || exit /b 1 & endlocal
 REM setlocal & call BuildBP || exit /b 1 & endlocal
 setlocal & call BuildImages || exit /b 1 & endlocal
-setlocal & call BuildROM %* || exit /b 1 & endlocal
+setlocal & call BuildROM %* || exit /b 1 & endlocal
+setlocal & call BuildZRC %* || exit /b 1 & endlocal

Source/CBIOS/cbios.asm

@@ -350,33 +350,41 @@ REBOOT:
 ;
 ;__________________________________________________________________________________________________
 WBOOT:
-	LD	SP,STACK	; STACK FOR INITIALIZATION
+;
+#IFDEF PLTWBW
+	; GIVE HBIOS A CHANCE TO DIAGNOSE ISSUES, PRIMARILY
+	; THE OCCURRENCE OF A Z180 INVALID OPCODE TRAP
+	POP	HL			; SAVE PC FOR DIAGNOSIS
+	LD	SP,STACK		; STACK FOR INITIALIZATION
+	LD	BC,$F003		; HBIOS USER RESET FUNCTION
+	RST	08			; DO IT
+#ENDIF
 ;
 #IFDEF PLTUNA
 	; RESTORE COMMAND PROCESSOR FROM UNA BIOS CACHE
-	LD	BC,$01FB	; UNA FUNC = SET BANK
-	LD	DE,(BNKBIOS)	; UBIOS_PAGE (SEE PAGES.INC)
-	RST	08		; DO IT
-	PUSH	DE		; SAVE PREVIOUS BANK
-
-	LD	HL,(CCPBUF)	; ADDRESS OF CCP BUF IN BIOS MEM
-	LD	DE,CCP_LOC	; ADDRESS IN HI MEM OF CCP
-	LD	BC,CCP_SIZ	; SIZE OF CCP
-	LDIR			; DO IT
-
-	LD	BC,$01FB	; UNA FUNC = SET BANK
-	POP	DE		; RECOVER OPERATING BANK
-	RST	08		; DO IT
+	LD	BC,$01FB		; UNA FUNC = SET BANK
+	LD	DE,(BNKBIOS)		; UBIOS_PAGE (SEE PAGES.INC)
+	RST	08			; DO IT
+	PUSH	DE			; SAVE PREVIOUS BANK
+	
+	LD	HL,(CCPBUF)		; ADDRESS OF CCP BUF IN BIOS MEM
+	LD	DE,CCP_LOC		; ADDRESS IN HI MEM OF CCP
+	LD	BC,CCP_SIZ		; SIZE OF CCP
+	LDIR				; DO IT
+	
+	LD	BC,$01FB		; UNA FUNC = SET BANK
+	POP	DE			; RECOVER OPERATING BANK
+	RST	08			; DO IT
 #ELSE
 	; RESTORE COMMAND PROCESSOR FROM CACHE IN HB BANK
-	LD	B,BF_SYSSETCPY	; HBIOS FUNC: SETUP BANK COPY
-	LD	DE,(BNKBIOS)	; D = DEST (USER BANK), E = SRC (BIOS BANK)
-	LD	HL,CCP_SIZ	; HL = COPY LEN = SIZE OF COMMAND PROCESSOR
-	RST	08		; DO IT
-	LD	B,BF_SYSBNKCPY	; HBIOS FUNC: PERFORM BANK COPY
-	LD	HL,(CCPBUF)	; COPY FROM FIXED LOCATION IN HB BANK
-	LD	DE,CCP_LOC	; TO CCP LOCATION IN USR BANK
-	RST	08		; DO IT
+	LD	B,BF_SYSSETCPY		; HBIOS FUNC: SETUP BANK COPY
+	LD	DE,(BNKBIOS)		; D = DEST (USER BANK), E = SRC (BIOS BANK)
+	LD	HL,CCP_SIZ		; HL = COPY LEN = SIZE OF COMMAND PROCESSOR
+	RST	08			; DO IT
+	LD	B,BF_SYSBNKCPY		; HBIOS FUNC: PERFORM BANK COPY
+	LD	HL,(CCPBUF)		; COPY FROM FIXED LOCATION IN HB BANK
+	LD	DE,CCP_LOC		; TO CCP LOCATION IN USR BANK
+	RST	08			; DO IT
 #ENDIF
 ;
 	; SOME APPLICATIONS STEAL THE BDOS SERIAL NUMBER STORAGE

Source/CPM3/bioskrnl.asm

@@ -172,7 +172,10 @@ boot$1:
 	;	Entry for system restarts.
 
 wboot:
-	lxi sp,boot$stack
+	pop h			; WBW: save PC for diagnosis
+	lxi sp,boot$stack	; reset stack
+	lxi b,0F003H		; WBW: HBIOS user reset func
+	rst 1			; WBW: do it
 	call set$jumps		; initialize page zero
 	call ?rlccp		; reload CCP
 	jmp ccp			; then reset jmp vectors and exit to ccp

Source/HBIOS/Build.ps1

@@ -21,13 +21,14 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s
 #
 $PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "RCZ280", "EZZ80", "UNA"
 $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
+$PlatformListZ280 = "RCZ280"
 
 #
 # Establish the build platform.  It may have been passed in on the command line.  Validate
 # $Platform and loop requesting a new value as long as it is not valid.  The valid platform
 # names are just hard-coded for now.
 #
-$PlatformList = $PlatformListZ80 + $PlatformListZ180
+$PlatformList = $PlatformListZ80 + $PlatformListZ180 + $PlatformListZ280
 $Prompt = "Platform ["
 ForEach ($PlatformName in $PlatformList) {$Prompt += $PlatformName + "|"}
 $Prompt = $Prompt.Substring(0, $Prompt.Length - 1) + "]"
@@ -72,7 +73,9 @@ while ($true)
 # TASM should be invoked with the proper CPU type.  Below, the CPU type is inferred
 # from the platform.
 #
-if ($PlatformListZ180 -contains $Platform) {$CPUType = "180"} else {$CPUType = "80"}
+$CPUType = "80"
+if ($PlatformListZ180 -contains $Platform) {$CPUType = "180"}
+if ($PlatformListZ280 -contains $Platform) {$CPUType = "280"}
 
 #
 # The $RomName variable determines the name of the image created by the script.  By default,

Source/HBIOS/Config/RCZ280_ext.asm

@@ -32,7 +32,8 @@ CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
 ;
 INTMODE		.SET	1
 ;
-Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;

Source/HBIOS/Config/RCZ280_nat.asm

@@ -34,7 +34,8 @@ MEMMGR		.SET	MM_Z280		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 ;
 INTMODE		.SET	3
 ;
-Z280_MEMWAIT	.SET	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
@@ -48,5 +49,3 @@ IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-;
-Z2UOSCEXT	.SET	TRUE		; Z2U: USE EXTERNAL OSCILLATOR

Source/HBIOS/Config/RCZ280_nat_zz.asm

@@ -0,0 +1,32 @@
+;
+;==================================================================================================
+;   RC2014 Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZ80MB)
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "Config/RCZ280_nat.asm"
+;
+RAMLOC		.SET	23		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.SET	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+;
+Z2U0HFC		.SET	TRUE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL

Source/HBIOS/Makefile

@@ -14,6 +14,7 @@ else
 	OBJECTS += RCZ180_nat.rom RCZ180_nat.com RCZ180_nat.upd
 	OBJECTS += RCZ280_ext.rom RCZ280_ext.com RCZ280_ext.upd
 	OBJECTS += RCZ280_nat.rom RCZ280_nat.com RCZ280_nat.upd
+	OBJECTS += RCZ280_nat_zz.rom RCZ280_nat_zz.com RCZ280_nat_zz.upd
 	OBJECTS += RCZ80_kio.rom RCZ80_kio.com RCZ80_kio.upd
 	OBJECTS += RCZ80_mt.rom RCZ80_mt.com RCZ80_mt.upd
 	OBJECTS += RCZ80_duart.rom RCZ80_duart.com RCZ80_duart.upd

Source/HBIOS/cfg_dyno.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
-RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_ezz80.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_master.asm

@@ -25,8 +25,9 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_NONE		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
-RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MEMMGR		.SET	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
@@ -40,7 +41,8 @@ Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
-Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
@@ -139,6 +141,7 @@ Z2UOSC		.EQU	1843200		; Z2U: OSC FREQUENCY IN MHZ
 Z2UOSCEXT	.EQU	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
 Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
 Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
+Z2U0HFC		.EQU	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
 ;
 ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT

Source/HBIOS/cfg_mk4.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
-RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_n8.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMLOC		.EQU	0		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_rcz180.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
-RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rcz280.asm

@@ -13,7 +13,7 @@
 ;
 #DEFINE PLATFORM_NAME "RC2014"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
+PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280]
 CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
@@ -28,14 +28,17 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
+Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
 ;
@@ -111,6 +114,7 @@ Z2UOSC		.EQU	1843200		; Z2U: OSC FREQUENCY IN MHZ
 Z2UOSCEXT	.EQU	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
 Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
 Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
+Z2U0HFC		.EQU	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
 ;
 ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT

Source/HBIOS/cfg_rcz80.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_sbc.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;

Source/HBIOS/cfg_scz180.asm

@@ -28,8 +28,9 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
-RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
+RAMLOC		.EQU	19		; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
+RAMBIAS		.EQU	(1 << (RAMLOC - 10))	; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2

Source/HBIOS/cfg_zeta.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
+MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;

Source/HBIOS/cfg_zeta2.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280]
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/dbgmon.asm

@@ -44,7 +44,7 @@ BUFLEN	.EQU	40			; INPUT LINE LENGTH
 ;
 UART_ENTRY:
 	LD	SP,MON_STACK		; SET THE STACK POINTER
-	EI				; INTS OK NOW
+	;EI				; INTS OK NOW
 	LD	HL,UART_ENTRY		; RESTART ADDRESS
 	CALL	INITIALIZE		; INITIALIZE SYSTEM
 
@@ -120,9 +120,9 @@ SERIALCMDLOOP:
 ;_____________________________________________________________________________
 ;
 INITIALIZE:
-	LD	A,$C3		; JP OPCODE
-	LD	(0),A		; STORE AT $0000
-	LD	(1),HL		; STORE AT $0001
+	;LD	A,$C3		; JP OPCODE
+	;LD	(0),A		; STORE AT $0000
+	;LD	(1),HL		; STORE AT $0001
 
 #IF (BIOS == BIOS_UNA)
 	; INSTALL UNA INVOCATION VECTOR FOR RST 08
@@ -132,10 +132,14 @@ INITIALIZE:
 	LD	(9),HL		; STORE AT 0x0009
 #ENDIF
 
-;#IF (BIOS == BIOS_WBW)
-;	CALL	DELAY_INIT
-;#ENDIF
-
+#IF DSKYENABLE
+	LD	B,BF_SYSGET		; HBIOS FUNC=GET SYS INFO
+	LD	C,BF_SYSGET_CPUINFO	; HBIOS SUBFUNC=GET CPU INFO
+	RST	08			; CALL HBIOS
+	LD	A,L			; PUT SPEED IN MHZ IN ACCUM
+	CALL	DELAY_INIT
+#ENDIF
+;
 	RET
 ;
 ;__BOOT_______________________________________________________________________
@@ -962,7 +966,7 @@ KY_PW	.EQU	KY_BK		; USE [BW] FOR [PW] (PORT WRITE)
 ;
 DSKY_ENTRY:
 	LD	SP,MON_STACK		; SET THE STACK POINTER
-	EI				; INTS OK NOW
+	;EI				; INTS OK NOW
 	LD	HL,DSKY_ENTRY		; RESTART ADDRESS
 	CALL	INITIALIZE
 ;

Source/HBIOS/hbios.inc

@@ -90,6 +90,7 @@ BF_SYSINT	.EQU	BF_SYS + 12	; MANAGE INTERRUPT VECTORS
 BF_SYSRES_INT		.EQU	$00	; RESET HBIOS INTERNAL
 BF_SYSRES_WARM		.EQU	$01	; WARM START (RESTART BOOT LOADER)
 BF_SYSRES_COLD		.EQU	$02	; COLD START
+BF_SYSRES_USER		.EQU	$03	; USER RESET REQUEST
 ;
 BF_SYSGET_CIOCNT	.EQU	$00	; GET CHAR UNIT COUNT
 BF_SYSGET_CIOFN		.EQU	$01	; GET CIO UNIT FN/DATA ADR

Source/HBIOS/romldr.asm

@@ -83,6 +83,20 @@ bid_cur	.equ	-1	; used below to indicate current bank
 #else
 	ret				; return w/ ints disabled
 #endif
+;
+#if (BIOS == BIOS_WBW)
+	.fill	($40 - $),$FF
+	; After initial bootup, it is conventional for a jp 0 to
+	; cause a warm start of the system.  If there is no OS running
+	; then this bit of code will suffice.  After bootup, the
+	; jp instruction at $0 is modified to point here.
+	pop	hl			; save PC in case needed for ...
+	ld	bc,$F003		; HBIOS user reset function
+	call	HB_INVOKE		; do it
+	ld	bc,$F001		; HBIOS warm start function
+	call	HB_INVOKE		; do it
+#endif
+;
 	.fill	($66 - $)
 	retn				; nmi
 ;
@@ -147,6 +161,8 @@ start1:
 	ld	de,0			; put it in user page zero
 	ld	bc,$100			; full page
 	ldir				; do it
+	ld	hl,$0040		; adr of user reset code
+	ld	(1),hl			; save at $0000
 ;
 ; Page zero in user bank is ready for interrupts now.
 ;

Source/HBIOS/std.asm

@@ -13,6 +13,7 @@
 ; 9.  EZZ80	Easy Z80, Z80 SBC w/ RC2014 bus and CTC
 ; 10. SCZ180	Steve Cousins Z180 based system
 ; 11. DYNO	Steve Garcia's Dyno Micro-ATX Motherboard
+; 12. RCZ280	Z280 CPU on RC2014 or ZZ80MB
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;
@@ -48,11 +49,12 @@ PLT_ZETA2	.EQU	3		; ZETA Z80 V2 SBC
 PLT_N8		.EQU	4		; N8 (HOME COMPUTER) Z180 SBC
 PLT_MK4		.EQU	5		; MARK IV
 PLT_UNA		.EQU	6		; UNA BIOS
-PLT_RCZ80	.EQU	7		; RC2014 W Z80
+PLT_RCZ80	.EQU	7		; RC2014 W/ Z80
 PLT_RCZ180	.EQU	8		; RC2014 W/ Z180
 PLT_EZZ80	.EQU	9		; EASY Z80
 PLT_SCZ180	.EQU	10		; SCZ180
 PLT_DYNO	.EQU	11		; DYNO MICRO-ATX MOTHERBOARD
+PLT_RCZ280	.EQU	12		; RC2014 W/ Z280
 ;
 ;
 ; CPU TYPES

Source/HBIOS/util.asm

@@ -643,26 +643,9 @@ LDELAY:
 	RET
 ;
 ; INITIALIZE DELAY SCALER BASED ON OPERATING CPU SPEED
-; HBIOS *MUST* BE INSTALLED AND AVAILABLE VIA RST 8!!!
-; CPU SCALER := MAX(1, (PHIMHZ - 2))
+; ENTER WITH A = CPU SPEED IN MHZ
 ;
 DELAY_INIT:
-  #IF (BIOS == BIOS_UNA)
-	LD	C,$F8			; UNA BIOS GET PHI FUNCTION
-	RST	08			; RETURNS SPEED IN HZ IN DE:HL
-	LD	B,4			; DIVIDE MHZ IN DE:HL BY 100000H
-DELAY_INIT0:
-	SRL	D			; ... TO GET APPROX CPU SPEED IN
-	RR	E			; ...MHZ.  THROW AWAY HL, AND
-	DJNZ	DELAY_INIT0		; ...RIGHT SHIFT DE BY 4.
-	INC	E			; FIX UP FOR VALUE TRUNCATION
-	LD	A,E			; PUT IN A
-  #ELSE
-	LD	B,BF_SYSGET		; HBIOS FUNC=GET SYS INFO
-	LD	C,BF_SYSGET_CPUINFO	; HBIOS SUBFUNC=GET CPU INFO
-	RST	08			; CALL HBIOS, RST 08 NOT YET INSTALLED
-	LD	A,L			; PUT SPEED IN MHZ IN ACCUM
-  #ENDIF
 	CP	3			; TEST FOR <= 2 (SPECIAL HANDLING)
 	JR	C,DELAY_INIT1		; IF <= 2, SPECIAL PROCESSING
 	SUB	2			; ADJUST AS REQUIRED BY DELAY FUNCTIONS

Source/HBIOS/z280.inc

@@ -57,7 +57,6 @@ Z280_UARTXCTL	.EQU	$12	; UART TRANSMIT CONTROL/STATUS REG
 Z280_UARTRCTL	.EQU	$14	; UART RECEIVE CONTROL/STATUS REG
 Z280_UARTRECV	.EQU	$16	; UART RECEIVE DATA REG
 Z280_UARTXMIT	.EQU	$18	; UART TRANSMIT DATA REG
-
 ;
 Z280_CT0_CFG	.EQU	$E0	; COUNTER/TIMER 0 CONFIG REG
 Z280_CT0_CMDST	.EQU	$E1	; COUNTER/TIMER 0 COMMAND/STATUS REG
@@ -73,4 +72,3 @@ Z280_CT2_CFG	.EQU	$F8	; COUNTER/TIMER 2 CONFIG REG
 Z280_CT2_CMDST	.EQU	$F9	; COUNTER/TIMER 2 COMMAND/STATUS REG
 Z280_CT2_TC	.EQU	$FA	; COUNTER/TIMER 2 TIME CONSTANT
 Z280_CT2_CT	.EQU	$FB	; COUNTER/TIMER 2 COUNT TIME
-

Source/HBIOS/z2u.asm

@@ -56,8 +56,13 @@
 ; UNLESS FULL BLOWN INTERRUPT MODE 3 W/ NATIVE MEMORY MANAGEMENT
 ; IS BEING USED.
 ;
-;Z2U_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
-Z2U_BUFSZ	.EQU	128		; RECEIVE RING BUFFER SIZE
+;
+;
+#IF (Z2U0HFC)
+Z2U_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
+#ELSE
+Z2U_BUFSZ	.EQU	144		; RECEIVE RING BUFFER SIZE
+#ENDIF
 ;
 Z2U_NONE	.EQU	0		; NOT PRESENT
 Z2U_PRESENT	.EQU	1		; PRESENT
@@ -173,10 +178,10 @@ Z2U_INT:
 ;
 	; START BY SELECTING I/O PAGE $FE (SAVING PREVIOUS VALUE)
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$66			; LDCTL HL,(C) ; GET CURRENT I/O PAGE
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
 	PUSH	HL			; SAVE IT
 	LD	L,$FE			; NEW COUNTER/TIMER I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -193,17 +198,19 @@ Z2U_INTRCV1:
 	JR	Z,Z2U_INTRCV4		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
 	INC	A			; INCREMENT THE COUNT
 	LD	(HL),A			; AND SAVE IT
-	;CP	Z2U_BUFSZ / 2		; BUFFER GETTING FULL?
-	;JR	NZ,Z2U_INTRCV2		; IF NOT, BYPASS CLEARING RTS
-	; THIS IS WHERE WE SHOULD DEASSERT RTS, BUT THE Z2U HAS NONE
+#IF (Z2U0HFC)
+	CP	Z2U_BUFSZ / 2		; BUFFER GETTING FULL?
+	JR	NZ,Z2U_INTRCV2		; IF NOT, BYPASS CLEARING RTS
+	PUSH	HL			; SAVE HL
+	LD	HL,0			; TC VALUE 0 CAUSES HIGH OUTPUT (RTS DEASSERTED)
+	LD	C,Z280_CT2_TC		; SET C/T 2
+	OUTW	(C),HL
+	POP	HL			; RESTORE HL
+#ENDIF
 Z2U_INTRCV2:
 	INC	HL			; HL NOW HAS ADR OF HEAD PTR
 	PUSH	HL			; SAVE ADR OF HEAD PTR
-	;LD	A,(HL)			; DEREFERENCE HL
-	;INC	HL
-	;LD	H,(HL)
-	;LD	L,A			; HL IS NOW ACTUAL HEAD PTR
-	.DB	$ED,$26			; LD HL,(HL) ; DEREFERENCE HL, HL IS NOW ACTUAL HEAD PTR
+	LD	HL,(HL)			; DEREFERENCE HL, HL IS NOW ACTUAL HEAD PTR
 	LD	(HL),B			; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
 	INC	HL			; BUMP HEAD POINTER
 	POP	DE			; RECOVER ADR OF HEAD PTR
@@ -219,10 +226,7 @@ Z2U_INTRCV2:
 	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
 Z2U_INTRCV3:
 	EX	DE,HL			; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
-	;LD	(HL),E			; SAVE UPDATED HEAD PTR
-	;INC	HL
-	;LD	(HL),D
-	.DB	$ED,$1E			;LD (HL),DE ; SAVE UPDATED HEAD PTR
+	LD	(HL),DE			; SAVE UPDATED HEAD PTR
 
 	; CHECK FOR MORE PENDING...
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -233,7 +237,7 @@ Z2U_INTRCV4:
 	; RESTORE I/O PAGE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
 	POP	HL			; RECOVER ORIGINAL I/O PAGE
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; RESTORE REGISTERS
 	POP	HL
@@ -267,7 +271,7 @@ Z2U_IN:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET CHAR
 	IN	A,(Z280_UARTRECV)	; GET A BYTE
@@ -276,7 +280,7 @@ Z2U_IN:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
@@ -292,7 +296,27 @@ Z2U_IN:
 	LD	A,(HL)			; GET COUNT
 	DEC	A			; DECREMENT COUNT
 	LD	(HL),A			; SAVE UPDATED COUNT
-	; THIS IS WHERE WE SHOULD ASSERT RTS, BUT THE Z2U HAS NONE
+;
+#IF (Z2U0HFC)
+	CP	Z2U_BUFSZ / 4		; BUFFER LOW THRESHOLD
+	JR	NZ,Z2U_IN1		; IF NOT, BYPASS SETTING RTS
+;
+	; ASSERT RTS
+	PUSH	HL
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	LDCTL	HL,(C)			; GET CURRENT I/O PAGE
+	PUSH	HL			; SAVE IT
+	LD	L,$FE			; NEW COUNTER/TIMER I/O PAGE
+	LDCTL	(C),HL
+	LD	HL,1			; TC VALUE ~0 CAUSES LOW OUTPUT (RTS ASSERTED)
+	LD	C,Z280_CT2_TC		; SET C/T 2
+	OUTW	(C),HL
+	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
+	POP	HL			; RECOVER ORIGINAL I/O PAGE
+	LDCTL	(C),HL
+	POP	HL
+#ENDIF
+;
 Z2U_IN1:
 	INC	HL			; HL := ADR OF TAIL PTR
 	INC	HL			; "
@@ -334,7 +358,7 @@ Z2U_OUT:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; WRITE CHAR
 	LD	A,E			; BYTE TO A
@@ -343,7 +367,7 @@ Z2U_OUT:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;	
 	XOR	A			; SIGNAL SUCCESS
 	RET				; DONE
@@ -356,7 +380,7 @@ Z2U_IST:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET RECEIVE STATUS
 	IN	A,(Z280_UARTRCTL)	; GET STATUS
@@ -365,11 +389,11 @@ Z2U_IST:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	OR	A			; SET FLAGS
 	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	
+;	
 	RET
 ;
 #ELSE
@@ -391,7 +415,7 @@ Z2U_OST:
 	; START BY SELECTING I/O PAGE $FE
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; GET TRANSMIT STATUS
 	IN	A,(Z280_UARTXCTL)	; GET STATUS
@@ -399,7 +423,7 @@ Z2U_OST:
 	; RESTORE I/O PAGE TO $00
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 	; CHECK FOR CHAR AVAILABLE
 	AND	$01			; ISOLATE CHAR AVAILABLE BIT
@@ -439,7 +463,6 @@ Z2U_INITDEVX:
 ;
 Z2U_INITDEV1:
 	LD	(Z2U_NEWCFG),DE		; SAVE NEW CONFIG
-	
 ;
 ; HACK FOR TESTING!!!
 ;
@@ -457,8 +480,6 @@ Z2U_INITDEV1:
 	;LD	HL,52			; 24MHZ / 8 / 52 = 57692 BAUD (~57600)
 	JP	Z2U_INITDEV8		; SKIP AHEAD TO IMPLMENT IT
 #ENDIF
-;
-;
 ;
 	LD	A,D			; HIWORD OF CONFIG
 	AND	$1F			; ISOLATE BAUD RATE
@@ -480,7 +501,6 @@ Z2U_INITDEV1:
 	; Z280 UART CAN USE 16, 32, OR 64 AS BAUD RATE DIVISOR
 	; SET E TO IMPLEMENT WHAT WE CAN
 	LD	E,%11000000		; 8N0, DIV 1, NO C/T
-	;JR	Z2U_INITDEV2		; *DEBUG*
 	CP	4			; DIV 16 POSSIBLE?
 	JR	C,Z2U_INITDEV2		; IF NOT, SKIP AHEAD
 	LD	E,%11000010		; 8N0, DIV 16, NO C/T
@@ -508,10 +528,7 @@ Z2U_INITDEV2:
 	LD	H,0			; H MUST BE ZERO
 	LD	DE,1			; RATIO, SO NO CONSTANT
 	CALL	DECODE			; DECODE INTO DE:HL
-	;LD	HL,626			; *DEBUG*
-	JR	NZ,Z2U_INITFAIL		; HANDLE FAILURE
-	;CALL	PC_SPACE		; *DEBUG* 
-	;CALL	PRTHEXWORDHL            ; *DEBUG*
+	JP	NZ,Z2U_INITFAIL		; HANDLE FAILURE
 ;
 	; SAVE CONFIG PERMANENTLY NOW
 	LD	DE,(Z2U_NEWCFG)		; GET NEW CONFIG BACK
@@ -523,7 +540,7 @@ Z2U_INITDEV8:
 	PUSH	HL			; SAVE HL
 	LD	L,$FE			; Z280 UART REGISTERS AT I/O PAGE $FE
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 	POP	HL			; RESTORE HL
 ;
 	DEC	HL			; ADJUST FOR T/C
@@ -539,9 +556,9 @@ Z2U_INITDEV8:
 #ENDIF
 	OUT	(Z280_CT1_CFG),A	; SET C/T 1
 	LD	C,Z280_CT1_TC		; SET C/T 1 FROM HL
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	LD	C,Z280_CT1_CT		; SET C/T 1 FROM HL
-	.DB	$ED,$BF			; OUTW (C),HL
+	OUTW	(C),HL
 	LD	A,%11100000		; CMD: EN, GT, TG
 	OUT	(Z280_CT1_CMDST),A	; SET C/T 1
 ;
@@ -562,11 +579,21 @@ Z2U_INITDEV9:
 	LD	A,%10000000		; ENABLE, NO RCV INTS
 #ENDIF
 	OUT	(Z280_UARTRCTL),A	; SET RCV CTL REGISTER
-;	
-	; RESTORE I/O PAGE TO $00
+;
+#IF (Z2U0HFC)
+	; SETUP C/T 2 FOR FLOW CONTROL
+	LD	A,%00001000		; CONFIG: TIMER
+	OUT	(Z280_CT2_CFG),A	; SET C/T 2 CONFIG
+	LD	HL,1			; TC VALUE ~0 CAUSES LOW OUTPUT (RTS ASSERTED)
+	LD	C,Z280_CT2_TC		; SET C/T 2
+	OUTW	(C),HL
+	LD	A,%00000000		; CMD: EN, GT
+	OUT	(Z280_CT2_CMDST),A	; SET C/T 2
+#ENDIF
+;
 	LD	L,$00			; NORMAL I/O REG IS $00
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
-	.DB	$ED,$6E			; LDCTL	(C),HL
+	LDCTL	(C),HL
 ;
 #IF (INTMODE == 3)
 ;

Source/ZRC/Build.cmd

@@ -1,13 +1,8 @@
 @echo off
 setlocal
 
-if not exist ..\..\Binary\RCZ80_zrc.rom goto :err
+if not exist ..\..\Binary\RCZ80_zrc.rom goto :eof
 
 copy /b zrc_cfldr.bin + zrc_ptbl.bin + zrc_fill_1.bin + zrc_mon.bin + zrc_fill_2.bin + ..\..\Binary\RCZ80_zrc.rom + zrc_fill_3.bin ..\..\Binary\hd1024_zrc_prefix.dat
 
-goto :eof
-
-:err
-
-echo *** Can't build ZRC prefix file -- missing "..\..\Binary\RCZ80_zrc.rom"
-exit /b 1
+copy /b ..\..\Binary\hd1024_zrc_prefix.dat + ..\..\Binary\hd1024_cpm22.img + ..\..\Binary\hd1024_zsdos.img + ..\..\Binary\hd1024_nzcom.img + ..\..\Binary\hd1024_cpm3.img + ..\..\Binary\hd1024_zpm3.img + ..\..\Binary\hd1024_ws4.img ..\..\Binary\hd1024_zrc_combo.img

Source/ZRC/Makefile

@@ -1,10 +1,13 @@
 HD1024ZRCPREFIX = hd1024_zrc_prefix.dat
+HD1024ZRCCOMBOIMG = hd1024_zrc_combo.img
 ZRCROM = ../../Binary/RCZ80_zrc.rom
+HD1024IMGS = ../../Binary/hd1024_cpm22.img ../../Binary/hd1024_zsdos.img ../../Binary/hd1024_nzcom.img \
+	../../Binary/hd1024_cpm3.img ../../Binary/hd1024_zpm3.img ../../Binary/hd1024_ws4.img
 
 OBJECTS :=
 
 ifneq ($(wildcard $(ZRCROM)),)
-	OBJECTS += $(HD1024ZRCPREFIX)
+	OBJECTS += $(HD1024ZRCPREFIX) $(HD1024ZRCCOMBOIMG)
 endif
 
 DEST=../../Binary
@@ -16,4 +19,7 @@ include $(TOOLS)/Makefile.inc
 DIFFPATH = $(DIFFTO)/Binary
 
 $(HD1024ZRCPREFIX):
-	cat zrc_cfldr.bin zrc_ptbl.bin zrc_fill_1.bin zrc_mon.bin zrc_fill_2.bin $(ZRCROM) zrc_fill_3.bin >$@
+	cat zrc_cfldr.bin zrc_ptbl.bin zrc_fill_1.bin zrc_mon.bin zrc_fill_2.bin $(ZRCROM) zrc_fill_3.bin >$@
+
+$(HD1024ZRCCOMBOIMG): $(HD1024ZRCPREFIX) $(HD1024IMGS)
+	cat $^ > $@

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.46"
+#DEFINE BIOSVER	"3.1.1-pre.54"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.46"
+	db	"3.1.1-pre.54"
 	endm

Tools/tasm32/TASM280.TAB

@@ -0,0 +1,608 @@
+"TASM Z80 Assembler.     "
+/****************************************************************************
+/* $Id: tasm80.tab 1.2 1998/02/28 14:31:22 toma Exp $
+/****************************************************************************
+/* This is the instruction set definition table 
+/*   for the Z280 version of TASM.
+/*
+/* Only a few Z280 specific instructions have been added!
+/*
+/*      Class bits assigned as follows:
+/*        Bit-0 = Z280          (base instruction set)
+/*  See TASM manual for info on table structure.
+/* 
+/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */
+/*-------------------------------------------*/
+
+ADC  A,(HL)  8E   1 NOP 1
+ADC  A,(IX*) 8EDD 3 ZIX 1
+ADC  A,(IY*) 8EFD 3 ZIX 1
+ADC  A,A     8F   1 NOP 1
+ADC  A,B     88   1 NOP 1
+ADC  A,C     89   1 NOP 1
+ADC  A,D     8A   1 NOP 1
+ADC  A,E     8B   1 NOP 1
+ADC  A,H     8C   1 NOP 1
+ADC  A,L     8D   1 NOP 1
+ADC  A,*     CE   2 NOP 1
+ADC  HL,BC   4AED 2 NOP 1
+ADC  HL,DE   5AED 2 NOP 1
+ADC  HL,HL   6AED 2 NOP 1
+ADC  HL,SP   7AED 2 NOP 1
+
+ADD  A,(HL)  86   1 NOP 1
+ADD  A,(IX*) 86DD 3 ZIX 1
+ADD  A,(IY*) 86FD 3 ZIX 1
+ADD  A,A     87   1 NOP 1
+ADD  A,B     80   1 NOP 1
+ADD  A,C     81   1 NOP 1
+ADD  A,D     82   1 NOP 1
+ADD  A,E     83   1 NOP 1
+ADD  A,H     84   1 NOP 1
+ADD  A,L     85   1 NOP 1
+ADD  A,*     C6   2 NOP 1
+ADD  HL,A    6DED 2 NOP 1	/* Z280 */
+ADD  HL,BC   09   1 NOP 1
+ADD  HL,DE   19   1 NOP 1
+ADD  HL,HL   29   1 NOP 1
+ADD  HL,SP   39   1 NOP 1
+ADD  IX,BC   09DD 2 NOP 1
+ADD  IX,DE   19DD 2 NOP 1
+ADD  IX,IX   29DD 2 NOP 1
+ADD  IX,SP   39DD 2 NOP 1
+ADD  IY,BC   09FD 2 NOP 1
+ADD  IY,DE   19FD 2 NOP 1
+ADD  IY,IY   29FD 2 NOP 1
+ADD  IY,SP   39FD 2 NOP 1
+
+AND  (HL)    A6   1 NOP 1
+AND  (IX*)   A6DD 3 ZIX 1
+AND  (IY*)   A6FD 3 ZIX 1
+AND  A       A7   1 NOP 1
+AND  B       A0   1 NOP 1
+AND  C       A1   1 NOP 1
+AND  D       A2   1 NOP 1
+AND  E       A3   1 NOP 1
+AND  H       A4   1 NOP 1
+AND  L       A5   1 NOP 1
+AND  *       E6   2 NOP 1
+
+BIT  *,(HL)  46CB 2 ZBIT 1
+BIT  *,(IX*) CBDD 4 ZBIT 1 0 4600
+BIT  *,(IY*) CBFD 4 ZBIT 1 0 4600
+BIT  *,A     47CB 2 ZBIT 1
+BIT  *,B     40CB 2 ZBIT 1
+BIT  *,C     41CB 2 ZBIT 1
+BIT  *,D     42CB 2 ZBIT 1
+BIT  *,E     43CB 2 ZBIT 1
+BIT  *,H     44CB 2 ZBIT 1
+BIT  *,L     45CB 2 ZBIT 1
+
+CALL C,*     DC   3 NOP 1
+CALL M,*     FC   3 NOP 1
+CALL NC,*    D4   3 NOP 1
+CALL NZ,*    C4   3 NOP 1
+CALL P,*     F4   3 NOP 1
+CALL PE,*    EC   3 NOP 1
+CALL PO,*    E4   3 NOP 1
+CALL Z,*     CC   3 NOP 1
+CALL *       CD   3 NOP 1
+
+CCF  ""      3F   1 NOP 1
+
+CP   (HL)    BE   1 NOP 1
+CP   (IX*)   BEDD 3 ZIX 1
+CP   (IY*)   BEFD 3 ZIX 1
+CP   A       BF   1 NOP 1
+CP   B       B8   1 NOP 1
+CP   C       B9   1 NOP 1
+CP   D       BA   1 NOP 1
+CP   E       BB   1 NOP 1
+CP   H       BC   1 NOP 1
+CP   L       BD   1 NOP 1
+CP   *       FE   2 NOP 1
+CPD  ""      A9ED 2 NOP 1
+CPDR ""      B9ED 2 NOP 1
+CPIR ""      B1ED 2 NOP 1
+CPI  ""      A1ED 2 NOP 1
+CPL  ""      2F   1 NOP 1
+
+DAA  ""      27   1 NOP 1
+
+DEC  (HL)    35   1 NOP 1
+DEC  (IX*)   35DD 3 ZIX 1
+DEC  (IY*)   35FD 3 ZIX 1
+DEC  A       3D   1 NOP 1
+DEC  B       05   1 NOP 1
+DEC  BC      0B   1 NOP 1
+DEC  C       0D   1 NOP 1
+DEC  D       15   1 NOP 1
+DEC  DE      1B   1 NOP 1
+DEC  E       1D   1 NOP 1
+DEC  H       25   1 NOP 1
+DEC  HL      2B   1 NOP 1
+DEC  IX      2BDD 2 NOP 1
+DEC  IY      2BFD 2 NOP 1
+DEC  L       2D   1 NOP 1
+DEC  SP      3B   1 NOP 1
+DI   ""      F3   1 NOP 1
+DJNZ *       10   2 R1  1
+
+EI   ""      FB   1 NOP 1
+EX   (SP),HL E3   1 NOP 1
+EX   (SP),IX E3DD 2 NOP 1
+EX   (SP),IY E3FD 2 NOP 1
+EX   AF,AF'  08   1 NOP 1
+EX   DE,HL   EB   1 NOP 1
+EXX  ""      D9   1 NOP 1
+HALT ""      76   1 NOP 1
+
+IM   0       46ED 2 NOP 1
+IM   1       56ED 2 NOP 1
+IM   2       5EED 2 NOP 1
+IM   3       4EED 2 NOP 1	/* Z280 */
+
+/* Alternate form of above
+IM0          46ED 2 NOP 1
+IM1          56ED 2 NOP 1
+IM2          5EED 2 NOP 1
+IM3          4EED 2 NOP 1	/* Z280 */
+
+IN   A,(C)   78ED 2 NOP 1
+IN   B,(C)   40ED 2 NOP 1
+IN   C,(C)   48ED 2 NOP 1
+IN   D,(C)   50ED 2 NOP 1
+IN   E,(C)   58ED 2 NOP 1
+IN   H,(C)   60ED 2 NOP 1
+IN   L,(C)   68ED 2 NOP 1
+
+IN   A,(*)   DB   2 NOP 1
+
+IN0   A,(*)  38ED 3 NOP 2
+IN0   B,(*)  00ED 3 NOP 2
+IN0   C,(*)  08ED 3 NOP 2
+IN0   D,(*)  10ED 3 NOP 2
+IN0   E,(*)  18ED 3 NOP 2
+IN0   H,(*)  20ED 3 NOP 2
+IN0   L,(*)  28ED 3 NOP 2
+
+INC  (HL)    34   1 NOP 1
+INC  (IX*)   34DD 3 ZIX 1
+INC  (IY*)   34FD 3 ZIX 1
+INC  A       3C   1 NOP 1
+INC  B       04   1 NOP 1
+INC  BC      03   1 NOP 1
+INC  C       0C   1 NOP 1
+INC  D       14   1 NOP 1
+INC  DE      13   1 NOP 1
+INC  E       1C   1 NOP 1
+INC  H       24   1 NOP 1
+INC  HL      23   1 NOP 1
+INC  IX      23DD 2 NOP 1
+INC  IY      23FD 2 NOP 1
+INC  L       2C   1 NOP 1
+INC  SP      33   1 NOP 1
+
+
+IND  ""      AAED 2 NOP 1
+INDR ""      BAED 2 NOP 1
+INI  ""      A2ED 2 NOP 1
+INIR ""      B2ED 2 NOP 1
+
+JP   (HL)    E9   1 NOP 1
+JP   (IX)    E9DD 2 NOP 1
+JP   (IY)    E9FD 2 NOP 1
+JP   C,*     DA   3 NOP 1
+JP   M,*     FA   3 NOP 1
+JP   NC,*    D2   3 NOP 1
+JP   NZ,*    C2   3 NOP 1
+JP   P,*     F2   3 NOP 1
+JP   PE,*    EA   3 NOP 1
+JP   PO,*    E2   3 NOP 1
+JP   Z,*     CA   3 NOP 1
+JP   *       C3   3 NOP 1
+
+JR   C,*     38   2 R1  1
+JR   NC,*    30   2 R1  1
+JR   NZ,*    20   2 R1  1
+JR   Z,*     28   2 R1  1
+JR   *       18   2 R1  1
+
+LD   (BC),A  02   1 NOP 1
+LD   (DE),A  12   1 NOP 1
+LD   (HL),A  77   1 NOP 1
+LD   (HL),B  70   1 NOP 1
+LD   (HL),C  71   1 NOP 1
+LD   (HL),D  72   1 NOP 1
+LD   (HL),E  73   1 NOP 1
+LD   (HL),H  74   1 NOP 1
+LD   (HL),L  75   1 NOP 1
+LD   (HL),DE 1EED 2 NOP 1	/* Z280 */
+LD   (HL),*  36   2 NOP 1
+LD   (IX*),A 77DD 3 ZIX 1
+LD   (IX*),B 70DD 3 ZIX 1
+LD   (IX*),C 71DD 3 ZIX 1
+LD   (IX*),D 72DD 3 ZIX 1
+LD   (IX*),E 73DD 3 ZIX 1
+LD   (IX*),H 74DD 3 ZIX 1
+LD   (IX*),L 75DD 3 ZIX 1
+LD   (IX*),* 36DD 4 ZIX 1
+LD   (IY*),A 77FD 3 ZIX 1
+LD   (IY*),B 70FD 3 ZIX 1
+LD   (IY*),C 71FD 3 ZIX 1
+LD   (IY*),D 72FD 3 ZIX 1
+LD   (IY*),E 73FD 3 ZIX 1
+LD   (IY*),H 74FD 3 ZIX 1
+LD   (IY*),L 75FD 3 ZIX 1
+LD   (IY*),* 36FD 4 ZIX 1
+LD   (*),A   32   3 NOP 1
+LD   (*),BC  43ED 4 NOP 1
+LD   (*),DE  53ED 4 NOP 1
+LD   (*),HL  22   3 NOP 1
+LD   (*),IX  22DD 4 NOP 1
+LD   (*),IY  22FD 4 NOP 1
+LD   (*),SP  73ED 4 NOP 1
+LD   A,(BC)  0A   1 NOP 1
+LD   A,(DE)  1A   1 NOP 1
+LD   A,(HL)  7E   1 NOP 1
+LD   A,(IX*) 7EDD 3 ZIX 1
+LD   A,(IY*) 7EFD 3 ZIX 1
+LD   A,A     7F   1 NOP 1
+LD   A,B     78   1 NOP 1
+LD   A,C     79   1 NOP 1
+LD   A,D     7A   1 NOP 1
+LD   A,E     7B   1 NOP 1
+LD   A,H     7C   1 NOP 1
+LD   A,I     57ED 2 NOP 1
+LD   A,L     7D   1 NOP 1
+LD   A,R     5FED 2 NOP 1
+LD   A,(*)   3A   3 NOP 1
+LD   A,*     3E   2 NOP 1
+LD   B,(HL)  46   1 NOP 1
+LD   B,(IX*) 46DD 3 ZIX 1
+LD   B,(IY*) 46FD 3 ZIX 1
+LD   B,A     47   1 NOP 1
+LD   B,B     40   1 NOP 1
+LD   B,C     41   1 NOP 1
+LD   B,D     42   1 NOP 1
+LD   B,E     43   1 NOP 1
+LD   B,H     44   1 NOP 1
+LD   B,L     45   1 NOP 1
+LD   B,*     06   2 NOP 1
+LD   BC,(*)  4BED 4 NOP 1
+LD   BC,*    01   3 NOP 1
+LD   C,(HL)  4E   1 NOP 1
+LD   C,(IX*) 4EDD 3 ZIX 1
+LD   C,(IY*) 4EFD 3 ZIX 1
+LD   C,A     4F   1 NOP 1
+LD   C,B     48   1 NOP 1
+LD   C,C     49   1 NOP 1
+LD   C,D     4A   1 NOP 1
+LD   C,E     4B   1 NOP 1
+LD   C,H     4C   1 NOP 1
+LD   C,L     4D   1 NOP 1
+LD   C,*     0E   2 NOP 1
+LD   D,(HL)  56   1 NOP 1
+LD   D,(IX*) 56DD 3 ZIX 1
+LD   D,(IY*) 56FD 3 ZIX 1
+LD   D,A     57   1 NOP 1
+LD   D,B     50   1 NOP 1
+LD   D,C     51   1 NOP 1
+LD   D,D     52   1 NOP 1
+LD   D,E     53   1 NOP 1
+LD   D,H     54   1 NOP 1
+LD   D,L     55   1 NOP 1
+LD   D,*     16   2 NOP 1
+LD   DE,(*)  5BED 4 NOP 1
+LD   DE,*    11   3 NOP 1
+LD   E,(HL)  5E   1 NOP 1
+LD   E,(IX*) 5EDD 3 ZIX 1
+LD   E,(IY*) 5EFD 3 ZIX 1
+LD   E,A     5F   1 NOP 1
+LD   E,B     58   1 NOP 1
+LD   E,C     59   1 NOP 1
+LD   E,D     5A   1 NOP 1
+LD   E,E     5B   1 NOP 1
+LD   E,H     5C   1 NOP 1
+LD   E,L     5D   1 NOP 1
+LD   E,*     1E   2 NOP 1
+LD   H,(HL)  66   1 NOP 1
+LD   H,(IX*) 66DD 3 ZIX 1
+LD   H,(IY*) 66FD 3 ZIX 1
+LD   H,A     67   1 NOP 1
+LD   H,B     60   1 NOP 1
+LD   H,C     61   1 NOP 1
+LD   H,D     62   1 NOP 1
+LD   H,E     63   1 NOP 1
+LD   H,H     64   1 NOP 1
+LD   H,L     65   1 NOP 1
+LD   H,*     26   2 NOP 1
+LD   HL,(HL) 26ED 2 NOP 1	/* Z280 */
+LD   HL,(*)  2A   3 NOP 1
+LD   HL,*    21   3 NOP 1
+LD   I,A     47ED 2 NOP 1
+LD   IX,(*)  2ADD 4 NOP 1
+LD   IX,*    21DD 4 NOP 1
+LD   IY,(*)  2AFD 4 NOP 1
+LD   IY,*    21FD 4 NOP 1
+LD   L,(HL)  6E   1 NOP 1
+LD   L,(IX*) 6EDD 3 ZIX 1
+LD   L,(IY*) 6EFD 3 ZIX 1
+LD   L,A     6F   1 NOP 1
+LD   L,B     68   1 NOP 1
+LD   L,C     69   1 NOP 1
+LD   L,D     6A   1 NOP 1
+LD   L,E     6B   1 NOP 1
+LD   L,H     6C   1 NOP 1
+LD   L,L     6D   1 NOP 1
+LD   L,*     2E   2 NOP 1
+LD   R,A     4FED 2 NOP 1
+LD   SP,(*)  7BED 4 NOP 1
+LD   SP,HL   F9   1 NOP 1
+LD   SP,IX   F9DD 2 NOP 1
+LD   SP,IY   F9FD 2 NOP 1
+LD   SP,*    31   3 NOP 1
+LDCTL (C),HL 6EED 2 NOP 1	/* Z280 */
+LDCTL HL,(C) 66ED 2 NOP 1	/* Z280 */
+LDCTL USP,HL 8FED 2 NOP 1	/* Z280 */
+LDCTL IY,(C) 66EDFD 3 NOP 1	/* Z280 */
+LDCTL (C),IY 6EEDFD 3 NOP 1	/* Z280 */
+LDD  ""      A8ED 2 NOP 1
+LDDR ""      B8ED 2 NOP 1
+LDI  ""      A0ED 2 NOP 1
+LDIR ""      B0ED 2 NOP 1
+MULTU A,*    F9EDFD 4 NOP 1	/* Z280 */
+NEG  ""      44ED 2 NOP 1
+NOP  ""      00   1 NOP 1
+
+MLT BC       4CED 2 NOP 2
+MLT DE       5CED 2 NOP 2
+MLT HL       6CED 2 NOP 2
+MLT SP       7CED 2 NOP 2
+
+OR   (HL)    B6   1 NOP 1
+OR   (IX*)   B6DD 3 ZIX 1
+OR   (IY*)   B6FD 3 ZIX 1
+OR   A       B7   1 NOP 1
+OR   B       B0   1 NOP 1
+OR   C       B1   1 NOP 1
+OR   D       B2   1 NOP 1
+OR   E       B3   1 NOP 1
+OR   H       B4   1 NOP 1
+OR   L       B5   1 NOP 1
+OR   *       F6   2 NOP 1
+
+OTDM ""      8BED 2 NOP 2
+OTDMR ""     9BED 2 NOP 2
+OTDR ""      BBED 2 NOP 1
+OTIM ""      83ED 2 NOP 2
+OTIMR ""     93ED 2 NOP 2
+OTIR ""      B3ED 2 NOP 1
+
+OUT  (C),A   79ED 2 NOP 1
+OUT  (C),B   41ED 2 NOP 1
+OUT  (C),C   49ED 2 NOP 1
+OUT  (C),D   51ED 2 NOP 1
+OUT  (C),E   59ED 2 NOP 1
+OUT  (C),H   61ED 2 NOP 1
+OUT  (C),L   69ED 2 NOP 1
+OUT  (*),A   D3   2 NOP 1
+
+OUT0 (*),A   39ED 3 NOP 2
+OUT0 (*),B   01ED 3 NOP 2
+OUT0 (*),C   09ED 3 NOP 2
+OUT0 (*),D   11ED 3 NOP 2
+OUT0 (*),E   19ED 3 NOP 2
+OUT0 (*),H   21ED 3 NOP 2
+OUT0 (*),L   29ED 3 NOP 2
+
+OUTD ""      ABED 2 NOP 1
+OUTI ""      A3ED 2 NOP 1
+
+OUTW (C),HL  BFED 2 NOP 1	/* Z280 */
+
+PCACHE ""    65ED 2 NOP 1	/* Z280 */
+
+POP  AF      F1   1 NOP 1
+POP  BC      C1   1 NOP 1
+POP  DE      D1   1 NOP 1
+POP  HL      E1   1 NOP 1
+POP  IX      E1DD 2 NOP 1
+POP  IY      E1FD 2 NOP 1
+
+PUSH AF      F5   1 NOP 1
+PUSH BC      C5   1 NOP 1
+PUSH DE      D5   1 NOP 1
+PUSH HL      E5   1 NOP 1
+PUSH IX      E5DD 2 NOP 1
+PUSH IY      E5FD 2 NOP 1
+
+RES  *,(HL)  86CB 2 ZBIT 1
+RES  *,(IX*) CBDD 4 ZBIT 1 0 8600
+RES  *,(IY*) CBFD 4 ZBIT 1 0 8600
+RES  *,A     87CB 2 ZBIT 1
+RES  *,B     80CB 2 ZBIT 1
+RES  *,C     81CB 2 ZBIT 1
+RES  *,D     82CB 2 ZBIT 1
+RES  *,E     83CB 2 ZBIT 1
+RES  *,H     84CB 2 ZBIT 1
+RES  *,L     85CB 2 ZBIT 1
+
+RET  ""      C9   1 NOP 1
+RET  C       D8   1 NOP 1
+RET  M       F8   1 NOP 1
+RET  NC      D0   1 NOP 1
+RET  NZ      C0   1 NOP 1
+RET  P       F0   1 NOP 1
+RET  PE      E8   1 NOP 1
+RET  PO      E0   1 NOP 1
+RET  Z       C8   1 NOP 1
+RETI ""      4DED 2 NOP 1
+RETN ""      45ED 2 NOP 1
+
+RL   (HL)    16CB 2 NOP 1
+RL   (IX*)   CBDD 4 ZIX 1 0 1600
+RL   (IY*)   CBFD 4 ZIX 1 0 1600
+RL   A       17CB 2 NOP 1
+RL   B       10CB 2 NOP 1
+RL   C       11CB 2 NOP 1
+RL   D       12CB 2 NOP 1
+RL   E       13CB 2 NOP 1
+RL   H       14CB 2 NOP 1
+RL   L       15CB 2 NOP 1
+RLA  ""      17   1 NOP 1
+
+RLC  (HL)    06CB 2 NOP 1
+RLC  (IX*)   CBDD 4 ZIX 1 0 0600
+RLC  (IY*)   CBFD 4 ZIX 1 0 0600
+RLC  A       07CB 2 NOP 1
+RLC  B       00CB 2 NOP 1
+RLC  C       01CB 2 NOP 1
+RLC  D       02CB 2 NOP 1
+RLC  E       03CB 2 NOP 1
+RLC  H       04CB 2 NOP 1
+RLC  L       05CB 2 NOP 1
+RLCA ""      07   1 NOP 1
+RLD  ""      6FED 2 NOP 1
+
+RR   (HL)    1ECB 2 NOP 1
+RR   (IX*)   CBDD 4 ZIX 1 0 1E00
+RR   (IY*)   CBFD 4 ZIX 1 0 1E00 
+RR   A       1FCB 2 NOP 1
+RR   B       18CB 2 NOP 1
+RR   C       19CB 2 NOP 1
+RR   D       1ACB 2 NOP 1
+RR   E       1BCB 2 NOP 1
+RR   H       1CCB 2 NOP 1
+RR   L       1DCB 2 NOP 1
+RRA  ""      1F   1 NOP 1
+RRC  (HL)    0ECB 2 NOP 1
+RRC  (IX*)   CBDD 4 ZIX 1 0 0E00
+RRC  (IY*)   CBFD 4 ZIX 1 0 0E00
+RRC  A       0FCB 2 NOP 1
+RRC  B       08CB 2 NOP 1
+RRC  C       09CB 2 NOP 1
+RRC  D       0ACB 2 NOP 1
+RRC  E       0BCB 2 NOP 1
+RRC  H       0CCB 2 NOP 1
+RRC  L       0DCB 2 NOP 1
+RRCA ""      0F   1 NOP 1
+RRD  ""      67ED 2 NOP 1
+
+RST  00H     C7   1 NOP 1
+RST  08H     CF   1 NOP 1
+RST  10H     D7   1 NOP 1
+RST  18H     DF   1 NOP 1
+RST  20H     E7   1 NOP 1
+RST  28H     EF   1 NOP 1
+RST  30H     F7   1 NOP 1
+RST  38H     FF   1 NOP 1
+
+/* Alternate form of above
+RST  00      C7   1 NOP 1
+RST  08      CF   1 NOP 1
+RST  10      D7   1 NOP 1
+RST  18      DF   1 NOP 1
+RST  20      E7   1 NOP 1
+RST  28      EF   1 NOP 1
+RST  30      F7   1 NOP 1
+RST  38      FF   1 NOP 1
+
+SBC  A,(HL)  9E   1 NOP 1
+SBC  A,(IX*) 9EDD 3 ZIX 1
+SBC  A,(IY*) 9EFD 3 ZIX 1
+SBC  A,A     9F   1 NOP 1
+SBC  A,B     98   1 NOP 1
+SBC  A,C     99   1 NOP 1
+SBC  A,D     9A   1 NOP 1
+SBC  A,E     9B   1 NOP 1
+SBC  A,H     9C   1 NOP 1
+SBC  A,L     9D   1 NOP 1
+SBC  HL,BC   42ED 2 NOP 1
+SBC  HL,DE   52ED 2 NOP 1
+SBC  HL,HL   62ED 2 NOP 1
+SBC  HL,SP   72ED 2 NOP 1
+SBC  A,*     DE   2 NOP 1
+SCF  ""      37   1 NOP 1
+
+SET  *,(HL)  C6CB 2 ZBIT 1
+SET  *,(IX*) CBDD 4 ZBIT 1 0 C600
+SET  *,(IY*) CBFD 4 ZBIT 1 0 C600
+SET  *,A     C7CB 2 ZBIT 1
+SET  *,B     C0CB 2 ZBIT 1
+SET  *,C     C1CB 2 ZBIT 1
+SET  *,D     C2CB 2 ZBIT 1
+SET  *,E     C3CB 2 ZBIT 1
+SET  *,H     C4CB 2 ZBIT 1
+SET  *,L     C5CB 2 ZBIT 1
+
+SLA  (HL)    26CB 2 NOP 1
+SLA  (IX*)   CBDD 4 ZIX 1 0 2600
+SLA  (IY*)   CBFD 4 ZIX 1 0 2600
+SLA  A       27CB 2 NOP 1
+SLA  B       20CB 2 NOP 1
+SLA  C       21CB 2 NOP 1
+SLA  D       22CB 2 NOP 1
+SLA  E       23CB 2 NOP 1
+SLA  H       24CB 2 NOP 1
+SLA  L       25CB 2 NOP 1
+
+SLP  ""      76ED 2 NOP 2
+
+SRA  (HL)    2ECB 2 NOP 1
+SRA  (IX*)   CBDD 4 ZIX 1 0 2E00
+SRA  (IY*)   CBFD 4 ZIX 1 0 2E00
+SRA  A       2FCB 2 NOP 1
+SRA  B       28CB 2 NOP 1
+SRA  C       29CB 2 NOP 1
+SRA  D       2ACB 2 NOP 1
+SRA  E       2BCB 2 NOP 1
+SRA  H       2CCB 2 NOP 1
+SRA  L       2DCB 2 NOP 1
+
+SRL  (HL)    3ECB 2 NOP 1
+SRL  (IX*)   CBDD 4 ZIX 1 0 3E00
+SRL  (IY*)   CBFD 4 ZIX 1 0 3E00
+SRL  A       3FCB 2 NOP 1
+SRL  B       38CB 2 NOP 1
+SRL  C       39CB 2 NOP 1
+SRL  D       3ACB 2 NOP 1
+SRL  E       3BCB 2 NOP 1
+SRL  H       3CCB 2 NOP 1
+SRL  L       3DCB 2 NOP 1
+
+SUB  (HL)    96   1 NOP 1
+SUB  (IX*)   96DD 3 ZIX 1
+SUB  (IY*)   96FD 3 ZIX 1
+SUB  A       97   1 NOP 1
+SUB  B       90   1 NOP 1
+SUB  C       91   1 NOP 1
+SUB  D       92   1 NOP 1
+SUB  E       93   1 NOP 1
+SUB  H       94   1 NOP 1
+SUB  L       95   1 NOP 1
+SUB  *       D6   2 NOP 1
+
+TST  A       3CED 2 NOP 2
+TST  B       04ED 2 NOP 2
+TST  C       0CED 2 NOP 2
+TST  D       14ED 2 NOP 2
+TST  E       1CED 2 NOP 2
+TST  H       24ED 2 NOP 2
+TST  L       2CED 2 NOP 2
+TST  (HL)    34ED 2 NOP 2
+TST  *       64ED 3 NOP 2
+
+TSTIO *      74ED 3 NOP 2
+
+XOR  (HL)    AE   1 NOP 1
+XOR  (IX*)   AEDD 3 ZIX 1
+XOR  (IY*)   AEFD 3 ZIX 1
+XOR  A       AF   1 NOP 1
+XOR  B       A8   1 NOP 1
+XOR  C       A9   1 NOP 1
+XOR  D       AA   1 NOP 1
+XOR  E       AB   1 NOP 1
+XOR  H       AC   1 NOP 1
+XOR  L       AD   1 NOP 1
+XOR  *       EE   2 NOP 1

Tools/unix/uz80as/z80.c

@@ -65,11 +65,13 @@ static const struct matchtab s_matchtab_z80[] = {
 	{ "LD R,A", "ED.4F.", 3, 0 },
 	{ "LD SP,HL", "F9.", 3, 0 },
 	{ "LD SP,e", "d0.F9.", 3, 0 },
+	{ "LD HL,(HL)", "ED.26.", 2, 0 }, // Z280
 	{ "LD HL,(a)", "2A.e0", 3, 0 },
 	{ "LD d,(a)", "ED.4Bf0.e1", 3, 0 },
 	{ "LD d,a", "01f0.e1", 3, 0 },
 	{ "LD e,(a)", "d0.2A.e1", 3, 0 },
 	{ "LD e,a", "d0.21.e1", 3, 0 },
+	{ "LD (HL),DE", "ED.1E.", 2, 0 }, // Z280
 	{ "LD (HL),b", "70c0.", 3, 0 },
 	{ "LD (HL),a", "36.d0.", 3, 0, "e8" },
 	{ "LD (BC),A", "02.", 3, 0 },
@@ -99,6 +101,7 @@ static const struct matchtab s_matchtab_z80[] = {
 	{ "CPIR", "ED.B1.", 3, 0 },
 	{ "CPD", "ED.A9.", 3, 0 },
 	{ "CPDR", "ED.B9.", 3, 0 },
+	{ "ADD HL,A", "ED.6D.", 2, 0 }, // Z280
 	{ "ADD HL,d", "09f0.", 3, 0 },
 	{ "ADD IX,i", "DD.09f0.", 3, 0 },
 	{ "ADD IY,j", "FD.09f0.", 3, 0 },
@@ -197,6 +200,15 @@ static const struct matchtab s_matchtab_z80[] = {
 	{ "TST (HL)", "ED.34.", 2, 0 },
 	{ "TST a", "ED.64.d0.", 2, 0, "e8" },
 	{ "TSTIO a", "ED.74.d0.", 2, 0, "e8" },
+	/* Z280 added instructions */
+	{ "PCACHE", "ED.65.", 2, 0 },
+	{ "LDCTL (C),HL", "ED.6E.", 2, 0 },
+	{ "LDCTL HL,(C)", "ED.66.", 2, 0 },
+	{ "LDCTL USP,HL", "ED.8F.", 2, 0 },
+	{ "LDCTL IY,(C)", "FD.ED.66.", 2, 0 },
+	{ "LDCTL (C),IY", "FD.ED.6E.", 2, 0 },
+	{ "MULTU A,a", "FD.ED.F9.d0.", 2, 0 },
+	{ "OUTW (C),HL", "ED.BF.", 2, 0 },
 	{ NULL, NULL },
 };
 
@@ -278,7 +290,7 @@ static int gen_z80(int *eb, char p, const int *vs, int i, int savepc)
 		  }
 		  b |= vs[i];
 		  break;
-	case 'k': if (s_pass > 0 && (vs[i] < 0 || vs[i] > 2)) {
+	case 'k': if (s_pass > 0 && (vs[i] < 0 || vs[i] > 3)) {
 			  eprint(_("invalid IM argument (%d)\n"),
 				vs[i]);
 			  eprcol(s_pline, s_pline_ep);
@@ -289,6 +301,8 @@ static int gen_z80(int *eb, char p, const int *vs, int i, int savepc)
 			  b = 0x56;
 		  else if (vs[i] == 2)
 			  b = 0x5E;
+		  else if (vs[i] == 3)
+			  b = 0x4E;
 		  break;
 	case 'm': if (s_pass == 0 && !s_extended_op) {
 			  if (vs[i] != 0 && vs[i] != 1 && vs[i] != 3) {