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Duo/MBC IM2 Hardware Timer support

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This commit is contained in:
b1ackmai1er
2023-08-21 16:00:47 +08:00
parent 59d04f2446
commit 9f5b3a8b1c
21 changed files with 172 additions and 57 deletions
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2
Source/HBIOS/Config/DUO_std.asm
View File

@@ -44,3 +44,5 @@ MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
;
UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
;UARTCFG .SET UARTCFG | SER_RTS
;
HWTENABLE .SET FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

4
Source/HBIOS/Config/MBC_std.asm
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@@ -58,3 +58,7 @@ CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PS2KENABLE .SET FALSE ; PS2 KEYBOARD ON IM2 INTERRUPT CIRCUIT
PS2PORT .SET $E2 ; PS2 KEYBOARD PORT
HWTENABLE .SET FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_duo.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR DUODYNE
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR DUODYNE
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -299,5 +299,7 @@ DMAENABLE .EQU TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $40 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_DUO ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_dyno.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR DYNO
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR DYNO
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -285,5 +285,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_master.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION MASTER
; ROMWBW 3.X CONFIGURATION MASTER
;==================================================================================================
;
; THIS FILE IS *NOT* A REAL CONFIGURATION FILE. IT IS A MASTER TEMPLATE FILE
@@ -373,5 +373,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

11
Source/HBIOS/cfg_mbc.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR MBC
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR MBC
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -297,6 +297,9 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
PS2KENABLE .EQU FALSE ; PS2 KEYBOARD ON IM2 INTERRUPT CIRCUIT
PS2PORT .EQU $E2 ; PS2 KEYBOARD PORT
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_mk4.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR MARK IV
; ROMWBW 3.X CONFIGURATION FOR MARK IV
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -294,5 +294,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_n8.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR N8
; ROMWBW 3.X CONFIGURATION FOR N8
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -287,5 +287,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_rcz180.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -311,5 +311,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .SET FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_rcz280.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -315,5 +315,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z280 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .SET FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_rcz80.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RCBUS Z80
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -309,5 +309,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

12
Source/HBIOS/cfg_rph.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION FOR RHYOPHYRE
; ROMWBW 3.X CONFIGURATION FOR RHYOPHYRE
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -87,7 +87,7 @@ DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
ICMPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF ICM PPI
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
PKDPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF PKD PPI
PKDPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF PKD PPI
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
;
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
@@ -256,7 +256,7 @@ PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
PIOSBASE .EQU RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
PIOSBASE .EQU RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR
@@ -276,5 +276,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_s100.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR S100 Z180
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 Z180
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -305,5 +305,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_sbc.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SBC
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SBC
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -275,5 +275,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_scz180.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -305,5 +305,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

4
Source/HBIOS/cfg_una.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR UNA
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR UNA
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -36,3 +36,5 @@ ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_z80retro.asm
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@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
; ROMWBW 32.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -236,5 +236,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

8
Source/HBIOS/cfg_zeta.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V1
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V1
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -207,5 +207,7 @@ DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

6
Source/HBIOS/cfg_zeta2.asm
View File

@@ -1,6 +1,6 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR ZETA V2
; ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V2
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
@@ -219,4 +219,6 @@ DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
;
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
;
HWTENABLE .EQU FALSE ; HARDWARE TIMER ON IM2 INTERRUPT CIRCUIT

27
Source/HBIOS/hbios.asm
View File

@@ -2148,11 +2148,36 @@ HB_CPU3:
LD HL,HB_TIMINT
CALL HB_ADDIM1 ; ADD TO IM1 CALL LIST
#ENDIF
;
#ENDIF
;
#ENDIF
;
#IF (HWTENABLE & (INTMODE == 2)) ; HARDWARE TIMER TICK
#IF (PLATFORM == PLT_MBC)
LD HL,HB_TIMINT
LD (IVT(INT_IM2PH7)),HL ; IVT ENTRY FOR TIMER
#ENDIF
#IF (PLATFORM == PLT_DUO)
LD HL,HB_TIMINT
LD (IVT(INT_IM2PH0)),HL ; IVT ENTRY FOR TIMER
#ENDIF
#ENDIF
;
; PS2 KEYBOARD INTERRUPT
;
; #IF (PS2KENABLE & !(CVDUENABLE | VGAENABLE) | GDCENABLE | (TMSENABLE & ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC))))
;
; #IF (INTMODE == 2)
; LD HL,KBD_INT
; LD (IVT(INT_IM2PH1)),HL ; IVT ENTRY FOR KEYBOARD
; #ENDIF
;
; #ENDIF
;
#IF (KIOENABLE)
CALL KIO_PREINIT
#ENDIF

59
Source/HBIOS/std.asm
View File

@@ -758,15 +758,30 @@ INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
#ENDIF
#IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
#IF (PLATFORM == PLT_MBC)
; MBC Z80
#IF (PLATFORM == PLT_MBC)
;
; MBC IM2 PINHEADER INTERRUPTS
;
;INT_IM2PH0 .EQU 0
INT_IM2PH1 .EQU 1 ; PS2 KEYBOARD
;INT_IM2PH2 .EQU 2
;INT_IM2PH3 .EQU 3
;INT_IM2PH4 .EQU 4
;INT_IM2PH5 .EQU 5
;INT_IM2PH6 .EQU 6
INT_IM2PH7 .EQU 7 ; HARDWARE TIMER TICK
;
; MBC Z80 INTERRUPTS
;
;INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
;INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
;INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
;INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_INT6 .EQU 6 ;
INT_INT7 .EQU 7 ;
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
@@ -778,9 +793,23 @@ INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
;INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
;INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ELSE
#ENDIF
; GENERIC Z80
#IF (PLATFORM == PLT_DUO)
; DUO IM2 PINHEADER INTERRUPTS
INT_IM2PH0 .EQU 0 ; HARDWARE TIMER TICK
;INT_IM2PH1 .EQU 1
;INT_IM2PH2 .EQU 2
;INT_IM2PH3 .EQU 3
;INT_IM2PH4 .EQU 4
;INT_IM2PH5 .EQU 5
;INT_IM2PH6 .EQU 6
INT_IM2PH7 .EQU 7 ; PCF I2C
;
; DUO Z80 IM2 INTERRUPTS
;
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
@@ -794,7 +823,27 @@ INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#ENDIF
#IF ((PLATFORM != PLT_MBC) & (PLATFORM != PLT_DUO))
; GENERIC Z80 M2 INTERRUPTS
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B
INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#ENDIF
#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1