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Fix Duodyne MMU Regression

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Wayne Warthen
2024-07-21 16:40:59 -07:00
parent 21df9d8797
commit a078820745
5 changed files with 26 additions and 12 deletions
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2
Source/HBIOS/cfg_duo.asm
View File

@@ -138,7 +138,7 @@ DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTOSC .EQU 7372800 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD

28
Source/HBIOS/cfg_mon.asm
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@@ -141,17 +141,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD
UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD
UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR
UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG
UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR
UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG
UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR
UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG
UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR
UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG
UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR
UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG
UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR
UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG
UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR
UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG
UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR
UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;

4
Source/HBIOS/hbios.asm
View File

@@ -615,7 +615,11 @@ HBX_ROM:
BIT 7,A ; BIT 7 SET REQUESTS RAM PAGE
JR Z,HBX_ROM ; NOT SET, SELECT ROM PAGE
RES 7,A ; RAM PAGE REQUESTED: CLEAR ROM BIT
#IF (PLATFORM == PLT_DUO)
ADD A,64 ; ADD 64 x 32K - RAM STARTS FROM 2048K
#ELSE
ADD A,ROMSIZE / 32 ; STARTING RAM BANK NUMBER OFFSET
#ENDIF
;
HBX_ROM:
RLCA ; TIMES 2 - GET 16K PAGE INSTEAD OF 32K