Fix Duodyne MMU Regression

Source/HBIOS/cfg_duo.asm

@@ -138,7 +138,7 @@ DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
 UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
 UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD

Source/HBIOS/cfg_mon.asm

@@ -141,17 +141,27 @@ DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
 DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
 UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
 UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
 UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UARTCFG		.EQU	DEFSERCFG | SER_RTS	; UART: LINE CONFIG FOR UART PORTS
-UARTSBC		.EQU	FALSE		; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART
-UARTSBCFORCE	.EQU	FALSE		; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
-UARTAUX		.EQU	FALSE		; UART: AUTO-DETECT AUX UART
-UARTCAS		.EQU	FALSE		; UART: AUTO-DETECT ECB CASSETTE UART
-UARTMFP		.EQU	FALSE		; UART: AUTO-DETECT MF/PIC UART
-UART4		.EQU	FALSE		; UART: AUTO-DETECT 4UART UART
-UARTRC		.EQU	TRUE		; UART: AUTO-DETECT RC UART
-UARTDUAL	.EQU	FALSE		; UART: AUTO-DETECT DUAL UART
+UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
 ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;

Source/HBIOS/hbios.asm

@@ -615,7 +615,11 @@ HBX_ROM:
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
 	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+  #IF (PLATFORM == PLT_DUO)
+	ADD	A,64			; ADD 64 x 32K - RAM STARTS FROM 2048K
+  #ELSE
 	ADD	A,ROMSIZE / 32		; STARTING RAM BANK NUMBER OFFSET
+  #ENDIF
 ;
 HBX_ROM:
 	RLCA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K

Source/ver.inc

@@ -2,7 +2,7 @@
 #DEFINE	RMN	5
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.5.0-dev.59"
+#DEFINE BIOSVER	"3.5.0-dev.60"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	5
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.5.0-dev.59"
+	db	"3.5.0-dev.60"
 	endm