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Merge pull request #198 from wwarthen/dev 

Dev
pull/224/head
b1ackmai1er 5 years ago
committed by GitHub
parent
20838c2f89 600aa2b2fb
commit
a0bf6659f1
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 47 additions and 37 deletions
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  1. 68
      Source/HBIOS/dsrtc.asm
  2. 8
      Source/HBIOS/hbios.asm
  3. 8
      Source/HBIOS/sd.asm

68
Source/HBIOS/dsrtc.asm
View File

@ -63,25 +63,25 @@
; ;
; CONSTANTS ; CONSTANTS
; ;
; RTC SBC SBC-004 MFPIC N8 N8-CSIO SC
; ----- ------- ------- ------- ------- ------- -------
; D7 WR RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
; D6 WR RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK
; D5 WR /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE
; D4 WR RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE
; D3 WR NC SPK /RTC_CE NC NC /SPI_CS2
; D2 WR NC CLKHI RTC_CLK SPI_CS SPI_CS /SPI_CS1
; D1 WR -- -- RTC_WE SPI_CLK NC FS
; D0 WR -- -- RTC_OUT SPI_DI NC I2C_SCL
;
; D7 RD -- -- -- -- -- I2C_SDA
; D6 RD CFG CFG -- SPI_DO CFG --
; D5 RD -- -- -- -- -- --
; D4 RD -- -- -- -- -- --
; D3 RD -- -- -- -- -- --
; D2 RD -- -- -- -- -- --
; D1 RD -- -- -- -- -- --
; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN
; RTC SBC SBC-004 MFPIC N8 N8-CSIO MK4 SC130 SC131 SC126
; ----- ------- ------- ------- ------- ------- ------- ------- ------- -------
; D7 WR RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT -- -- RTC_OUT, I2C_SDA
; D6 WR RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK -- -- RTC_CLK
; D5 WR /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE -- -- /RTC_WE
; D4 WR RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE -- -- RTC_CE
; D3 WR NC SPK /RTC_CE NC NC NC -- -- /SPI_CS2
; D2 WR NC CLKHI RTC_CLK SPI_CS SPI_CS NC /SPI_CS1/SPI_CS1/SPI_CS1
; D1 WR -- -- RTC_WE SPI_CLK NC NC -- -- FS
; D0 WR -- -- RTC_OUT SPI_DI NC NC -- -- I2C_SCL
;
; D7 RD -- -- -- -- -- -- -- -- I2C_SDA
; D6 RD CFG CFG -- SPI_DO CFG -- -- -- --
; D5 RD -- -- -- -- -- -- -- -- --
; D4 RD -- -- -- -- -- -- -- -- --
; D3 RD -- -- -- -- -- -- -- -- --
; D2 RD -- -- -- -- -- -- -- -- --
; D1 RD ---- -- -- -- -- -- -- -- --
; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN -- -- RTC_IN
; ;
#IF (DSRTCMODE == DSRTCMODE_STD) #IF (DSRTCMODE == DSRTCMODE_STD)
; ;
@ -95,7 +95,7 @@ DSRTC_CE .EQU %00010000 ; BIT 4 IS CHIP ENABLE (CE)
DSRTC_MASK .EQU %11110000 ; MASK FOR BITS WE OWN IN RTC LATCH PORT DSRTC_MASK .EQU %11110000 ; MASK FOR BITS WE OWN IN RTC LATCH PORT
DSRTC_IDLE .EQU %00100000 ; QUIESCENT STATE DSRTC_IDLE .EQU %00100000 ; QUIESCENT STATE
; ;
RTCDEF .SET DSRTC_IDLE ; FOR HBIOS MAINLINE
RTCDEF .SET RTCDEF | DSRTC_IDLE ; FOR HBIOS MAINLINE
; ;
#DEFINE DSRTC_OPRVAL RTCVAL #DEFINE DSRTC_OPRVAL RTCVAL
; ;
@ -195,7 +195,7 @@ DSRTC_INIT1:
CALL DSRTC_CLK2TIM CALL DSRTC_CLK2TIM
LD HL,DSRTC_TIMBUF LD HL,DSRTC_TIMBUF
CALL PRTDT CALL PRTDT
;
;
#IF DSRTCCHG ; FORCE_RTC_CHARGE_ENABLE #IF DSRTCCHG ; FORCE_RTC_CHARGE_ENABLE
LD C,$90 ; ACCESS CHARGE REGISTER LD C,$90 ; ACCESS CHARGE REGISTER
LD E,DS1d2k ; STD CHARGE VALUES LD E,DS1d2k ; STD CHARGE VALUES
@ -234,11 +234,11 @@ DSRTC_DISPATCH:
DEC A DEC A
JP Z,DSRTC_GETBLK ; GET NVRAM DATA BLOCK VALUES JP Z,DSRTC_GETBLK ; GET NVRAM DATA BLOCK VALUES
DEC A DEC A
JP Z,DSRTC_SETBLK ; SET NVRAM DATA BLOCK VALUES
JP Z,DSRTC_SETBLK ; SET NVRAM DATA BLOCK VALUES
DEC A DEC A
JP Z,DSRTC_GETALM ; GET ALARM JP Z,DSRTC_GETALM ; GET ALARM
DEC A DEC A
JP Z,DSRTC_SETALM ; SET ALARM
JP Z,DSRTC_SETALM ; SET ALARM
DEC A DEC A
JP Z,DSRTC_DEVICE ; REPORT RTC DEVICE INFO JP Z,DSRTC_DEVICE ; REPORT RTC DEVICE INFO
CALL SYSCHK CALL SYSCHK
@ -393,7 +393,7 @@ DSRTC_CLK2TIM:
LD (HL),A LD (HL),A
INC HL INC HL
LD A,(DSRTC_SEC) LD A,(DSRTC_SEC)
LD (HL),A
LD (HL),A
RET RET
; ;
; CONVERT DATA IN TIME BUFFER AT HL TO CLOCK BUFFER ; CONVERT DATA IN TIME BUFFER AT HL TO CLOCK BUFFER
@ -431,20 +431,20 @@ DSRTC_TSTCHG:
LD A,E ; VALUE TO A LD A,E ; VALUE TO A
AND %11110000 ; CHECK FOR AND %11110000 ; CHECK FOR
CP %10100000 ; ... ENABLED FLAG CP %10100000 ; ... ENABLED FLAG
RET
RET
; ;
; DETECT RTC HARDWARE PRESENCE ; DETECT RTC HARDWARE PRESENCE
; ;
DSRTC_DETECT: DSRTC_DETECT:
LD C,31 ; NVRAM INDEX 31
LD C,30 ; NVRAM INDEX 30
CALL DSRTC_GETBYT ; GET VALUE CALL DSRTC_GETBYT ; GET VALUE
LD A,E ; TO ACCUM LD A,E ; TO ACCUM
LD (DSRTC_TEMP),A ; SAVE IT LD (DSRTC_TEMP),A ; SAVE IT
XOR $FF ; FLIP ALL BITS XOR $FF ; FLIP ALL BITS
LD E,A ; TO E LD E,A ; TO E
LD C,31 ; NVRAM INDEX 31
LD C,30 ; NVRAM INDEX 30
CALL DSRTC_SETBYT ; WRITE IT CALL DSRTC_SETBYT ; WRITE IT
LD C,31 ; NVRAM INDEX 31
LD C,30 ; NVRAM INDEX 30
CALL DSRTC_GETBYT ; GET VALUE CALL DSRTC_GETBYT ; GET VALUE
LD A,(DSRTC_TEMP) ; GET SAVED VALUE LD A,(DSRTC_TEMP) ; GET SAVED VALUE
XOR $FF ; FLIP ALL BITS XOR $FF ; FLIP ALL BITS
@ -455,7 +455,7 @@ DSRTC_DETECT:
DSRTC_DETECT1: DSRTC_DETECT1:
PUSH AF ; SAVE STATUS PUSH AF ; SAVE STATUS
LD A,(DSRTC_TEMP) ; GET SAVED VALUE LD A,(DSRTC_TEMP) ; GET SAVED VALUE
LD C,31 ; NVRAM INDEX 31
LD C,30 ; NVRAM INDEX 30
CALL DSRTC_SETBYT ; SAVE IT CALL DSRTC_SETBYT ; SAVE IT
POP AF ; RECOVER STATUS POP AF ; RECOVER STATUS
OR A ; SET FLAGS OR A ; SET FLAGS
@ -506,7 +506,7 @@ DSRTC_WRBYT:
DSRTC_WRBYTWP: DSRTC_WRBYTWP:
LD D,C ; WRITE CMD TO D LD D,C ; WRITE CMD TO D
PUSH DE ; SAVE PARMS PUSH DE ; SAVE PARMS
;
;
; TURN OFF WRITE PROTECT ; TURN OFF WRITE PROTECT
LD C,$8E ; CMD LD C,$8E ; CMD
LD E,0 ; WRITE PROTECT OFF LD E,0 ; WRITE PROTECT OFF
@ -517,7 +517,7 @@ DSRTC_WRBYTWP:
LD C,D ; WRITE CMD BACK TO C LD C,D ; WRITE CMD BACK TO C
CALL DSRTC_WRBYT ; DO IT CALL DSRTC_WRBYT ; DO IT
; ;
; TURN WRITE PROTECT BACK ON
; TURN WRITE PROTECT BACK ON
LD C,$8E ; WRITE CMD TO D LD C,$8E ; WRITE CMD TO D
LD E,$80 ; WRITE PROTECT ON LD E,$80 ; WRITE PROTECT ON
CALL DSRTC_WRBYT ; DO IT CALL DSRTC_WRBYT ; DO IT
@ -619,7 +619,7 @@ DSRTC_PUT1:
AND ~DSRTC_CLK ; SET CLOCK LOW AND ~DSRTC_CLK ; SET CLOCK LOW
OUT (DSRTC_IO),A ; DO IT OUT (DSRTC_IO),A ; DO IT
CALL DLY1 ; DELAY 27 T-STATES CALL DLY1 ; DELAY 27 T-STATES
#IF (DSRTCMODE == DSRTCMODE_MFPIC) #IF (DSRTCMODE == DSRTCMODE_MFPIC)
RRA ; PREP ACCUM TO GET DATA BIT IN CARRY RRA ; PREP ACCUM TO GET DATA BIT IN CARRY
RR E ; ROTATE NEXT BIT TO SEND INTO CARRY RR E ; ROTATE NEXT BIT TO SEND INTO CARRY
@ -628,7 +628,7 @@ DSRTC_PUT1:
RLA ; PREP ACCUM TO GET DATA BIT IN CARRY RLA ; PREP ACCUM TO GET DATA BIT IN CARRY
RR E ; ROTATE NEXT BIT TO SEND INTO CARRY RR E ; ROTATE NEXT BIT TO SEND INTO CARRY
RRA ; ROTATE BITS BACK TO CORRECT POSTIIONS RRA ; ROTATE BITS BACK TO CORRECT POSTIIONS
#ENDIF
#ENDIF
OUT (DSRTC_IO),A ; ASSERT DATA BIT ON BUS OUT (DSRTC_IO),A ; ASSERT DATA BIT ON BUS
OR DSRTC_CLK ; SET CLOCK HI OR DSRTC_CLK ; SET CLOCK HI
OUT (DSRTC_IO),A ; DO IT OUT (DSRTC_IO),A ; DO IT
@ -710,7 +710,9 @@ DSRTC_END:
DSRTC_STAT .DB 0 ; DEVICE STATUS (0=OK) DSRTC_STAT .DB 0 ; DEVICE STATUS (0=OK)
DSRTC_TEMP .DB 0 ; TEMP VALUE STORAGE DSRTC_TEMP .DB 0 ; TEMP VALUE STORAGE
; ;
#IF (DSRTCMODE == DSRTCMODE_MFPIC)
DSRTC_RTCVAL .DB DSRTC_IDLE ; LOCAL LATCH SHADOW FOR MFPIC DSRTC_RTCVAL .DB DSRTC_IDLE ; LOCAL LATCH SHADOW FOR MFPIC
#ENDIF
; ;
; DSRTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS-1302 ; DSRTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS-1302
; FIELDS BELOW MATCH ORDER OF DS-1302 FIELDS (BCD) ; FIELDS BELOW MATCH ORDER OF DS-1302 FIELDS (BCD)

8
Source/HBIOS/hbios.asm
View File

@ -181,6 +181,10 @@ CTCD .EQU CTCBASE + 3 ; CTC: CHANNEL D REGISTER ADR
; ;
RTCDEF .EQU 0 ; ALLOWS DRIVERS TO SET BITS RTCDEF .EQU 0 ; ALLOWS DRIVERS TO SET BITS
; ;
#IF (PLATFORM == PLT_SCZ180)
RTCDEF .SET RTCDEF | %00000001 ; SC128 I2C SCL BIT
#ENDIF
;
; ;
; ;
#IFNDEF APPBOOT #IFNDEF APPBOOT
@ -5018,6 +5022,10 @@ SIZ_AY38910 .EQU $ - ORG_AY38910
.ECHO SIZ_AY38910 .ECHO SIZ_AY38910
.ECHO " bytes.\n" .ECHO " bytes.\n"
#ENDIF #ENDIF
;
.ECHO "RTCDEF="
.ECHO RTCDEF
.ECHO "\n"
; ;
#DEFINE USEDELAY #DEFINE USEDELAY
#INCLUDE "util.asm" #INCLUDE "util.asm"

8
Source/HBIOS/sd.asm
View File

@ -129,7 +129,7 @@ SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU) SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_IOBASE .EQU SD_OPRREG ; IOBASE
; ;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_N8) ; UNMODIFIED N8-2511 #IF (SDMODE == SDMODE_N8) ; UNMODIFIED N8-2511
@ -144,7 +144,7 @@ SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU)
SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU) SD_DO .EQU %01000000 ; RTC:6 IS DATA OUT (CARD -> CPU)
SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_IOBASE .EQU SD_OPRREG ; IOBASE
; ;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_CSIO) ; N8-2312 #IF (SDMODE == SDMODE_CSIO) ; N8-2312
@ -157,7 +157,7 @@ SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR SD_TRDR .EQU Z180_TRDR
SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_IOBASE .EQU SD_OPRREG ; IOBASE
; ;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_PPI) ; PPISD #IF (SDMODE == SDMODE_PPI) ; PPISD
@ -224,7 +224,7 @@ SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR SD_TRDR .EQU Z180_TRDR
SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_IOBASE .EQU SD_OPRREG ; IOBASE
; ;
RTCDEF .SET SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_MT) ; MT shift register for RC2014 (ref SDMODE_CSIO) #IF (SDMODE == SDMODE_MT) ; MT shift register for RC2014 (ref SDMODE_CSIO)

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