diff --git a/Source/HBIOS/ez80cpudrv.asm b/Source/HBIOS/ez80cpudrv.asm
index 22dc7bb3..b82274af 100644
--- a/Source/HBIOS/ez80cpudrv.asm
+++ b/Source/HBIOS/ez80cpudrv.asm
@@ -12,9 +12,11 @@
 ; to communicate with the firmware to perform a number of initialisation tasks.
 ; See also the associated ez80 platform drivers (ez80rtc, ez80systmr, ez80uart).
 ;
-; The driver 'exports' two key functions:
+; The driver 'exports' the following:
 ; 1. EZ80_PREINIT - This function is called by the HBIOS boot code to initialise the eZ80 firmware.
 ; 2. EZ80_RPT_TIMINGS - This function is called by the HBIOS boot code to report the platform timings.
+; 3. DELAY - pause for approx 17us
+; 4. VDELAY - pause for approx 17us * DE
 ;
 ; EZ80_PREINIT performs the following:
 ; 1. Exchange platform version numbers
@@ -124,7 +126,10 @@ EZ80_PREINIT:
 	EZ80_TMR_SET_FREQTICK
 
 	RET
-
+;
+; --------------------------------
+; eZ80 CPU DRIVER REPORT TIMINGS
+; --------------------------------
 EZ80_RPT_TIMINGS:
 	LD	A, (EZ80_PLT_MEMWS)
 	BIT	7, A
@@ -161,7 +166,79 @@ EZ80_RPT_FSH_TIMINGS:
 	LD	A, (EZ80_PLT_FLSHWS)
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" FSH W/S$"
+	.TEXT	" FSH W/S$";
+
+;--------------------------------------------------------------------------------------------------
+; DELAY LOOP TEST CALIBRATION
+;--------------------------------------------------------------------------------------------------
+;
+; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE * 16 
+; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS
+; AND BUS CYCLES
+;
+#IF FALSE
+
+;   7.3728 MHZ -- 1 MEM W/S, 6 I/O W/S, 0 FSH W/S - 428 - 26.7us
+;  18.4320 MHZ -- 2 MEM W/S, 6 I/O W/S, 1 FSH W/S - 284 - 17.8us
+;  20.0000 MHZ -- 2 MEM W/S, 6 I/O W/S, 1 FSH W/S - 281 - 17.6us
+;  25.0000 MHZ -- 2 MEM W/S, 3 I/O B/C, 1 FSH W/S - 271 - 16.9us
+;  32.0000 MHZ -- 3 MEM W/S, 4 I/O B/C, 2 FSH W/S - 289 - 18.0us
+
+
+PC_DR:		.equ	$009E
+PC_DDR:		.equ	$009F
+	DI
+
+	; ENABLE PC5 GPIO AS OUTPUT
+	LD	BC, PC_DDR
+	XOR	A
+	OUT	(C), A
+	PUSH	AF
+
+	LD	BC, PC_DR
+LOOP:
+
+	POP	AF
+	OUT	(C), A
+	CPL
+	PUSH	AF
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+	CALL	DELAY
+
+	JR	LOOP
+#ENDIF
+	RET
+
+DELAY:
+	EZ80_DELAY
+	EZ80_DELAY
+	EZ80_DELAY
+	RET
+
+VDELAY:
+	EZ80_DELAY
+	DEC	DE
+	LD	A,D
+	OR	E
+	JR	NZ, VDELAY
 	RET
 
 EZ80_RPT_FIRMWARE:
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index d2ed3154..5da3db4d 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -11,8 +11,11 @@
   #DEFINE EZ80_IO	.DB 	$49, $CF
   ; RST.L $10
   #DEFINE EZ80_FN 	.DB	$49, $D7
+  ; RST.L $18
+  #DEFINE EZ80_DELAY	.DB	$49, $DF
 
   #DEFINE EZ80_UTIL_VER_EXCH		XOR A \ LD B, 0 \ EZ80_FN
+  #DEFINE EZ80_UTIL_DELAY 		XOR A \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSTM 		XOR A \ LD B, 3 \ EZ80_FN
   #DEFINE EZ80_UTIL_SET_BUSFQ 		XOR A \ LD B, 4 \ EZ80_FN
   #DEFINE EZ80_UTIL_GET_CPU_FQ 		XOR A \ LD B, 5 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index b77bcb09..b86965e6 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2570,8 +2570,10 @@ HB_CPU3:
 ;
 ;;; LOCATION OF THIS CODE???
 ;
+#IF (CPUFAM != CPU_EZ80)
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
 ;--------------------------------------------------------------------------------------------------
 ; SYSTEM TIMER INITIALIZATION
@@ -2943,42 +2945,6 @@ PSCNX	.EQU	$ + 1
 	DJNZ	PSCN1
 ;
 #ENDIF
-
-#IF (CPUFAM == CPU_EZ80)
-;
-;--------------------------------------------------------------------------------------------------
-; DELAY LOOP TEST CALIBRATION
-;--------------------------------------------------------------------------------------------------
-;
-; IF ENABLED, THE GPIO PCBx PINS OF THE EZ80 WILL BE TOGGLED AT 'DELAY' RATE
-; CAN BE USED TO VERIFY DELAY WORKS SUFFICIENT FOR DIFFERENT EZ80 CLOCK SPEEDS
-; AND BUS CYCLES
-;
-#IF FALSE
-
-PC_DR:		.equ	$009E
-PC_DDR:		.equ	$009F
-
-	; ENABLE PC5 GPIO AS OUTPUT
-	LD	BC, PC_DDR
-	XOR	A
-	OUT	(C), A
-	PUSH	AF
-
-	LD	BC, PC_DR
-	LD	D, 0
-LOOP:
-	POP	AF
-	OUT	(C), A
-	CPL
-	PUSH	AF
-
-	LD	DE, 2
-	CALL	VDELAY
-	JR	LOOP
-#ENDIF
-#ENDIF
-
 ;
 ;--------------------------------------------------------------------------------------------------
 ; CPU SPEED DETECTION ALIGNMENT TEST
@@ -5595,9 +5561,11 @@ SYS_SETCPUSPD2:
 	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
 	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
+#IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
 SYS_SETCPUSPD3:
 	XOR	A
@@ -5640,9 +5608,11 @@ SYS_SETCPUSPD2:
 	ADC	A,C			; C -> A; ADD CF FOR ROUNDING
 	LD	(CB_CPUMHZ),A		; SAVE IT
 ;
+#IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
 	XOR	A			; SIGNAL SUCCESS
 	RET
@@ -5777,9 +5747,11 @@ SYS_SETCPUSPD4:
 	LD	A,L			; WORKING VALUE TO A
 	OUT0	(Z180_DCNTL),A		; IMPLEMENT NEW VALUE
 ;
+#IF (CPUFAM != CPU_EZ80)
 	;  REINIT DELAY ROUTINE
 	LD	A,(CB_CPUMHZ)		; CPU SPEED TO ACCUM AND INIT
 	CALL	DELAY_INIT		; .. SPEED COMPENSATED DELAY
+#ENDIF
 ;
   #IF ((INTMODE == 2) & (Z180_TIMER))
 	; THE Z180 TIMER IS BASED ON CPU SPEED.  SO HERE
diff --git a/Source/HBIOS/util.asm b/Source/HBIOS/util.asm
index 1cf2fbd3..55c65f43 100644
--- a/Source/HBIOS/util.asm
+++ b/Source/HBIOS/util.asm
@@ -554,7 +554,7 @@ BYTE2BCD1:
 	RET
 
 #IFDEF USEDELAY
-
+#IF (CPUFAM != CPU_EZ80)
 ;
 ; DELAY 16US (CPU SPEED COMPENSATED) INCUDING CALL/RET INVOCATION
 ; REGISTER A AND FLAGS DESTROYED
@@ -632,6 +632,7 @@ VDELAY1:			;				|	|
 ;									|
 	RET			; 10TS (FINAL RETURN)			|
 	;---------------------------------------------------------------+
+#ENDIF
 ;
 ; DELAY ABOUT 0.5 SECONDS
 ; 500000US / 16US = 31250
@@ -644,6 +645,7 @@ LDELAY:
 	POP	DE
 	POP	AF
 	RET
+#IF (CPUFAM != CPU_EZ80)
 ;
 ; INITIALIZE DELAY SCALER BASED ON OPERATING CPU SPEED
 ; ENTER WITH A = CPU SPEED IN MHZ
@@ -666,6 +668,8 @@ CPUSCL	.DB	CPUMHZ - 2		; OTHERWISE 2 LESS THAN PHI MHZ
   #ENDIF
 ;
 #ENDIF
+#ENDIF
+
 ;
 ; SHORT DELAY FUNCTIONS.  NO CLOCK SPEED COMPENSATION, SO THEY
 ; WILL RUN LONGER ON SLOWER SYSTEMS.  THE NUMBER INDICATES THE