Merge pull request #17 from wwarthen/master

Resync
This commit is contained in:
b1ackmai1er
2019-09-22 14:46:34 +08:00
committed by GitHub
9 changed files with 56 additions and 5 deletions

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@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.10"
#DEFINE BIOSVER "2.9.2-pre.11"

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@@ -1187,6 +1187,57 @@ HB_CPU1:
OUT (CTCB),A ; SETUP CTCC
LD A,1 ; CTCC TIMER CONSTANT = 1
OUT (CTCB),A ; SETUP CTCC TIMER CONSTANT
;
; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO
; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
;
#IF (INTMODE == 2)
;
; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT
LD HL,HB_TIMINT ; TIMER INT HANDLER ADR
LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D
;
; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE
; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
; IVT CORRESPOND TO CTC CHANNELS A-D
LD A,0
OUT (CTCA),A ; SETUP CTC BASE INT VECTOR
;
; CTCC IS SLAVED (WIRED) TO TO CTCD TO ACT AS A PRESCALER
; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS
; CTC CLK = 1,843,200HZ
; CTCC TIME CONSTANT = 256
; CTCD TIME CONSTANT = 144
; INT FREQ IS CTC CLK / CTCC TC / CTCD TC
; WHICH IS 1,843,200HZ / 256 / 144 = 50HZ
LD A,%01010111 ; CTCC CONTROL WORD VALUE
; |||||||+-- 1=CONTROL WORD FLAG
; ||||||+--- 1=SOFTWARE RESET
; |||||+---- 1=TIME CONSTANT FOLLOWS
; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
; |||+------ 1=RISING EDGE TRIGGER
; ||+------- 1=PRESCALER OF 16 (NOT USED)
; |+-------- 1=COUNTER MODE
; +--------- 0=NO INTERRUPTS
OUT (CTCC),A ; SETUP CTCC
LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256
OUT (CTCC),A ; SETUP CTCA TIMER CONSTANT
LD A,%11010111 ; CTCD CONTROL WORD VALUE
; |||||||+-- 1=CONTROL WORD FLAG
; ||||||+--- 1=SOFTWARE RESET
; |||||+---- 1=TIME CONSTANT FOLLOWS
; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
; |||+------ 1=RISING EDGE TRIGGER
; ||+------- 1=PRESCALER OF 16 (NOT USED)
; |+-------- 1=COUNTER MODE
; +--------- 1=ENABLE INTERRUPTS
OUT (CTCD),A ; SETUP CTCD
LD A,144 ; CTCD TIMER CONSTANT = 144
OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT
#ENDIF
;
#ENDIF
;
@@ -1229,7 +1280,7 @@ HB_CPU1:
LD DE,(CPUOSC / 2) / 1000
;
#IF (Z180_CLKDIV >= 1)
LD A,L ; CPU TYPE
LD (HB_CPUTYPE),A ; CPU TYPE
CP 2 ; Z8S180 REV K OR BETTER?
JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
@@ -1241,7 +1292,6 @@ HB_CPU1:
#ENDIF
#IF (Z180_CLKDIV >= 2)
LD A,L ; CPU TYPE
CP 3 ; Z8S180 REV N OR BETTER?
JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED

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@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.10"
#DEFINE BIOSVER "2.9.2-pre.11"

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