mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
@@ -2,4 +2,4 @@
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#DEFINE RMN 9
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#DEFINE RUP 2
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#DEFINE RTP 0
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#DEFINE BIOSVER "2.9.2-pre.10"
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#DEFINE BIOSVER "2.9.2-pre.11"
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@@ -1187,6 +1187,57 @@ HB_CPU1:
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OUT (CTCB),A ; SETUP CTCC
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LD A,1 ; CTCC TIMER CONSTANT = 1
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OUT (CTCB),A ; SETUP CTCC TIMER CONSTANT
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;
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; ONLY IM2 IMPLEMENTED BELOW. I DON'T SEE ANY REASONABLE WAY TO
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; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
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; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
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; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
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;
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#IF (INTMODE == 2)
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;
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; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT
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LD HL,HB_TIMINT ; TIMER INT HANDLER ADR
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LD (IVT(INT_CTC0D)),HL ; IVT ENTRY FOR CTC0D
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;
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; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
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; EACH CHANNEL. BELOW WE SET THE BASE VECTOR TO THE
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; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
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; IVT CORRESPOND TO CTC CHANNELS A-D
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LD A,0
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OUT (CTCA),A ; SETUP CTC BASE INT VECTOR
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;
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; CTCC IS SLAVED (WIRED) TO TO CTCD TO ACT AS A PRESCALER
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; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS
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; CTC CLK = 1,843,200HZ
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; CTCC TIME CONSTANT = 256
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; CTCD TIME CONSTANT = 144
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; INT FREQ IS CTC CLK / CTCC TC / CTCD TC
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; WHICH IS 1,843,200HZ / 256 / 144 = 50HZ
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LD A,%01010111 ; CTCC CONTROL WORD VALUE
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; |||||||+-- 1=CONTROL WORD FLAG
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; ||||||+--- 1=SOFTWARE RESET
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; |||||+---- 1=TIME CONSTANT FOLLOWS
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; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
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; |||+------ 1=RISING EDGE TRIGGER
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; ||+------- 1=PRESCALER OF 16 (NOT USED)
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; |+-------- 1=COUNTER MODE
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; +--------- 0=NO INTERRUPTS
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OUT (CTCC),A ; SETUP CTCC
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LD A,0 ; CTCC TIMER CONSTANT = 256, 0 MEANS 256
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OUT (CTCC),A ; SETUP CTCA TIMER CONSTANT
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LD A,%11010111 ; CTCD CONTROL WORD VALUE
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; |||||||+-- 1=CONTROL WORD FLAG
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; ||||||+--- 1=SOFTWARE RESET
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; |||||+---- 1=TIME CONSTANT FOLLOWS
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; ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
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; |||+------ 1=RISING EDGE TRIGGER
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; ||+------- 1=PRESCALER OF 16 (NOT USED)
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; |+-------- 1=COUNTER MODE
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; +--------- 1=ENABLE INTERRUPTS
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OUT (CTCD),A ; SETUP CTCD
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LD A,144 ; CTCD TIMER CONSTANT = 144
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OUT (CTCD),A ; SETUP CTCD TIMER CONSTANT
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#ENDIF
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;
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#ENDIF
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;
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@@ -1229,7 +1280,7 @@ HB_CPU1:
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LD DE,(CPUOSC / 2) / 1000
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;
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#IF (Z180_CLKDIV >= 1)
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LD A,L ; CPU TYPE
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LD (HB_CPUTYPE),A ; CPU TYPE
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CP 2 ; Z8S180 REV K OR BETTER?
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JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
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; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
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@@ -1241,7 +1292,6 @@ HB_CPU1:
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#ENDIF
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#IF (Z180_CLKDIV >= 2)
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LD A,L ; CPU TYPE
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CP 3 ; Z8S180 REV N OR BETTER?
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JR C,HB_CPU2 ; IF NOT, NOT POSSIBLE!
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; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
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@@ -2,4 +2,4 @@
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#DEFINE RMN 9
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#DEFINE RUP 2
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#DEFINE RTP 0
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#DEFINE BIOSVER "2.9.2-pre.10"
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#DEFINE BIOSVER "2.9.2-pre.11"
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