From a92aebddd7c439453d27a0bb74674729cb29b907 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 1 Jun 2024 15:03:27 +1000
Subject: [PATCH] eZ80: hbios i/o operations updated for FPLED_IO and ram bank
 initialisation

---
 Source/HBIOS/cfg_rcez80.asm |  1 +
 Source/HBIOS/hbios.asm      | 55 +++++++++++++++++++++++++++++++++----
 Source/HBIOS/std.asm        |  1 +
 3 files changed, 51 insertions(+), 6 deletions(-)

diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index aa3a6cbe..629de8cb 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -17,6 +17,7 @@
 ;
 PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
 CPUFAM		.EQU	CPU_EZ80	; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80]
+EZ80IOBASE	.EQU	$FF		; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO
 BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
 BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
 HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 99920627..b588ae73 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -1397,7 +1397,12 @@ BOOTWAIT:
 ;
 	;LD	A,(RTCDEFVAL)		; GET DEFAULT VALUE
 	LD	A,RTCDEF		; DEFAULT VALUE
+#IF (CPUFAM == CPU_EZ80)
+	LD	BC,EZ80IOBASE << 8 + RTCIO
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+#ELSE
 	OUT	(RTCIO),A		; SET IT
+#ENDIF
 ;
 #IF (PLATFORM == PLT_N8)
 	LD	A,N8_DEFACR		; ENSURE N8 ACR
@@ -1421,9 +1426,16 @@ BOOTWAIT:
 	LD	A,DIAG_01
   #ENDIF
 ;
+#IF (CPUFAM == CPU_EZ80)
+	LD	BC,EZ80IOBASE << 8 + FPLED_IO
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+#ELSE
 	OUT	(FPLED_IO),A
 #ENDIF
+
+#ENDIF
 ;
+
 #IF (LEDENABLE)
   #IF ((LEDMODE == LEDMODE_STD) | (LEDMODE == LEDMODE_SC))
 	XOR	A			; LED IS INVERTED, TURN IT ON
@@ -1688,28 +1700,49 @@ ROMRESUME:
 ;
 #IF (MEMMGR == MM_Z2)
 ;
-  #IFDEF ROMBOOT
+  #IF (CPUFAM == CPU_EZ80)
+	XOR	A
+	LD	BC,EZ80IOBASE << 8 + MPGSEL_0
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+	INC	A
+	INC	BC			; BC = MPGSEL_1
+	OUT	(C),A			; OUT (MPGSEL_1), $01
+
+	LD	A,64 - 2
+	INC	BC			; BC = MPGSEL_2
+	OUT	(C),A			; PROG THIRD 16K MMU REGISTER
+	INC	A
+	INC	BC			; BC = MPGSEL_3
+	OUT	(C),A			; PROG FOURTH 16K MMU REGISTER
+	; ENABLE PAGING
+	LD	A,1
+	INC	BC			; BC =  MPGENA
+	OUT	(C),A			; ENABLE MMU NOW
+
+  #ELSE
+    #IFDEF ROMBOOT
 	; IF THIS IS A ROM BOOT, SETUP THE FIRST 2 16K MMU REGISTERS
 	; TO MAP THE LOWEST 32K OF PHYSICAL ROM TO THE LOW 32K OF
 	; CPU ADDRESS SPACE (BANKING AREA).  THE FIRST 16K MAPPING IS
 	; REDUNDANT BECAUSE WE ARE ALREADY RUNNING IN THIS AREA.  THE
 	; MAPPING OF THE SECOND 16K IS CRITICAL BECAUSE ALL ZETA 2
 	; MMU REGISTERS WILL BE 0 AT RESET!
+
 	XOR	A
 	OUT	(MPGSEL_0),A		; PROG FIRST 16K MMU REGISTER
 	INC	A
 	OUT	(MPGSEL_1),A		; PROG SECOND 16K MMU REGISTER
-  #ENDIF
-;
-  #IF (PLATFORM == PLT_DUO)
+    #ENDIF
+; 
+    #IF (PLATFORM == PLT_DUO)
 	; DUO HAS VARIABLE RAM SIZE.  RAM ALWAYS STARTS AT 2048K.
 	; SETUP COMMON RAM FOR HIGHEST 32K OF RAM BASED ON TOTAL RAM.
 	LD	A,128 + (RAMSIZE / 16) - 2
-  #ELSE
+    #ELSE
 	; NORMAL ZETA 2 SYSTEM HAS FIXED 512K OF RAM.  SETUP COMMON
 	; FOR TOP 32K OF THIS.
 	LD	A,64 - 2
-  #ENDIF
+    #ENDIF
 ;
 	OUT	(MPGSEL_2),A		; PROG THIRD 16K MMU REGISTER
 	INC	A
@@ -1717,7 +1750,9 @@ ROMRESUME:
 	; ENABLE PAGING
 	LD	A,1
 	OUT	(MPGENA),A		; ENABLE MMU NOW
+  #ENDIF
 #ENDIF
+
 ;
 ;--------------------------------------------------------------------------------------------------
 ; PROXY INSTALLATION
@@ -7117,7 +7152,15 @@ FP_SETLEDS:
   #IF (FPLED_INV)
 	XOR	$FF			; INVERT BITS IF NEEDED
   #ENDIF
+
+  #IF (CPUFAM == CPU_EZ80)
+	PUSH	BC
+	LD	BC,EZ80IOBASE << 8 + FPLED_IO
+	OUT	(C),A			; BC IS THE APPLIED IO ADDRESS
+	POP	BC
+  #ELSE
 	OUT	(FPLED_IO),A		; WRITE 
+  #ENDIF
 FP_SETLEDS1:
 	POP	HL			; RESTORE HL
 	RET				; DONE
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 9a51e3a3..3a90169d 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -63,6 +63,7 @@ CPU_NONE	.EQU	0		; NO CPU TYPE DEFINED
 CPU_Z80		.EQU	1		; Z80 FAMILY
 CPU_Z180	.EQU	2		; Z180 FAMILY
 CPU_Z280	.EQU	3		; Z280 FAMILY
+CPU_EZ80	.EQU	4		; eZ280 FAMILY
 ;
 ; BIOS MODE
 ;