mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Update ppide.asm
Initial multi device ppide
This commit is contained in:
b1ackmai1er
@@ -29,11 +29,6 @@ PPIDE_IO_BASE .EQU $80
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PPIDE_IO_BASE .EQU $4C
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#ENDIF
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;
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PPIDE_IO_DATALO .EQU PPIDE_IO_BASE + 0 ; IDE DATA BUS LSB (8255 PORT A)
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PPIDE_IO_DATAHI .EQU PPIDE_IO_BASE + 1 ; IDE DATA BUS MSB (8255 PORT B)
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PPIDE_IO_CTL .EQU PPIDE_IO_BASE + 2 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)
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PPIDE_IO_PPI .EQU PPIDE_IO_BASE + 3 ; 8255 CONTROL PORT
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;
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; THE CONTROL PORT OF THE 8255 IS PROGRAMMED AS NEEDED TO READ OR WRITE
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; DATA ON THE IDE BUS. PORT C OF THE 8255 IS ALWAYS IN OUTPUT MODE BECAUSE
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; IT IS DRIVING THE ADDRESS BUS AND CONTROL SIGNALS. PORTS A & B WILL BE
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@@ -173,6 +168,11 @@ PPIDE_REG_DRVADR .EQU PPIDE_CTL_CS3FX | $07 ; DRIVE ADDRESS REGISTER (R)
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; PPIDE2: SECONDARY MASTER
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; PPIDE3: SECONDARY SLAVE
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;
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PPIDE0IO .EQU PPIDE_IO_BASE
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PPIDE1IO .EQU 20H
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PPIDE2IO .EQU 00H
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PPIDE3IO .EQU 00H
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;
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PPIDE_DEVCNT .EQU 2 ; ASSUME ONLY PRIMARY INTERFACE
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;
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; COMMAND BYTES
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@@ -213,7 +213,7 @@ PPIDE_DRVSLAVE .DB %11110000 ; LBA, SLAVE DEVICE
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;
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; PPIDE DEVICE CONFIGURATION
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;
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PPIDE_CFGSIZ .EQU 12 ; SIZE OF CFG TBL ENTRIES
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PPIDE_CFGSIZ .EQU 16 ; SIZE OF CFG TBL ENTRIES
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;
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; PER DEVICE DATA OFFSETS
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;
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@@ -223,6 +223,11 @@ PPIDE_TYPE .EQU 2 ; DEVICE TYPE (BYTE)
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PPIDE_FLAGS .EQU 3 ; FLAG BITS BIT 0=CF, 1=LBA (BYTE)
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PPIDE_MEDCAP .EQU 4 ; MEDIA CAPACITY (DWORD)
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PPIDE_LBA .EQU 8 ; OFFSET OF LBA (DWORD)
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PPIDE_PORT .EQU 12 ; PORT ADDRESS OF THIS DEVICE (BYTE)
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PPIDE_DATALO .EQU 12 ; IDE DATA BUS LSB (8255 PORT A) (BYTE)
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PPIDE_DATAHI .EQU 13 ; IDE DATA BUS MSB (8255 PORT B)(BYTE)
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PPIDE_CTL .EQU 14 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)(BYTE)
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PPIDE_PPI .EQU 15 ; 8255 CONTROL PORT(BYTE)
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;
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PPIDE_CFGTBL:
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; DEVICE 0, PRIMARY MASTER
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@@ -232,6 +237,10 @@ PPIDE_CFGTBL:
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.DB 0 ; FLAGS BYTE
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.DW 0,0 ; DEVICE CAPACITY
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.DW 0,0 ; CURRENT LBA
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.DB PPIDE0IO ; DATALO IDE DATA BUS LSB (8255 PORT A)+ BASE ADDRESS OF PORT
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.DB PPIDE0IO+1 ; DATAHI IDE DATA BUS MSB (8255 PORT B)
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.DB PPIDE0IO+2 ; CTL IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)
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.DB PPIDE0IO+3 ; PPI 8255 CONTROL PORT
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; DEVICE 1, PRIMARY SLAVE
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.DB 1 ; DRIVER DEVICE NUMBER
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.DB 0 ; DEVICE STATUS
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@@ -239,6 +248,10 @@ PPIDE_CFGTBL:
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.DB 0 ; FLAGS BYTE
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.DW 0,0 ; DEVICE CAPACITY
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.DW 0,0 ; CURRENT LBA
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.DB PPIDE0IO ; DATALO IDE DATA BUS LSB (8255 PORT A)+ BASE ADDRESS OF PORT
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.DB PPIDE0IO+1 ; DATAHI IDE DATA BUS MSB (8255 PORT B)
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.DB PPIDE0IO+2 ; CTL IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)
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.DB PPIDE0IO+3 ; PPI 8255 CONTROL PORT
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;
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#IF ($ - PPIDE_CFGTBL) != (PPIDE_DEVCNT * PPIDE_CFGSIZ)
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.ECHO "*** INVALID PPIDE CONFIG TABLE ***\n"
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@@ -275,6 +288,7 @@ PPIDE_INIT:
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LD (PPIDE_TOSCALER),HL ; SAVE IT
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;
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PRTS(" IO=0x$") ; LABEL FOR IO ADDRESS
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LD IY,PPIDE_CFGTBL
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LD A,PPIDE_IO_BASE
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CALL PRTHEXBYTE
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;
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@@ -375,11 +389,15 @@ PPIDE_DETECT:
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; THEN THE BUS HOLD CIRCUITRY WILL READ BACK THE ZERO. SINCE
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; WE ARE IN WRITE MODE, AN IDE CONTROLLER WILL NOT BE ABLE TO
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; INTERFERE WITH THE VALUE BEING READ.
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LD C,(IY+PPIDE_PPI)
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LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
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OUT (PPIDE_IO_PPI),A ; OUTPUT TO CONTROL WORD
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LD C,PPIDE_IO_DATALO ; PPI PORT A
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OUT (C),A ; OUTPUT TO CONTROL WORD
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LD C,(IY+PPIDE_DATALO) ; PPI PORT A
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XOR A ; VALUE ZERO
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OUT (C),A ; PUSH VALUE TO PORT
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;; OUT (C),0
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;; .DB $ED,$71
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IN A,(C) ; GET PORT VALUE
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DCALL PC_SPACE
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DCALL PRTHEXBYTE
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@@ -717,7 +735,7 @@ PPIDE_RUNCMD:
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JP NZ,PPIDE_CMDERR
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RET
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;
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;
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; READ IDE DATA INTO BUFFER POINTED TO BY HL
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;
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PPIDE_GETBUF:
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#IF (PPIDETRACE >= 3)
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@@ -729,19 +747,22 @@ PPIDE_GETBUF:
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RET NZ ; BAIL OUT IF TIMEOUT
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;
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; SETUP PPI TO READ
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LD C,(IY+PPIDE_PPI) ;;
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LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ
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OUT (PPIDE_IO_PPI),A ; DO IT
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OUT (C),A ; DO IT
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;
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; SELECT READ/WRITE IDE REGISTER
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LD C,(IY+PPIDE_CTL) ;;
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LD A,PPIDE_REG_DATA ; DATA REGISTER
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OUT (PPIDE_IO_CTL),A ; DO IT
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OUT (C),A ; DO IT
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LD E,A ; E := READ UNASSERTED
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XOR PPIDE_CTL_DIOR ; SWAP THE READ LINE BIT
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LD D,A ; D := READ ASSERTED
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;
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; LOOP SETUP
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LD B,0 ; 256 ITERATIONS
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LD C,PPIDE_IO_DATALO ; SETUP C WITH IO PORT (LSB)
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LD C,(IY+PPIDE_DATALO) ; SETUP C WITH IO PORT (LSB)
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;
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#IF (!PPIDE8BIT)
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INC C ; PRE-INCREMENT C
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@@ -761,16 +782,22 @@ PPIDE_GETBUF:
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RET
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;
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PPIDE_GETBUF1: ; START OF READ LOOP
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LD A,D ; ASSERT READ
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OUT (PPIDE_IO_CTL),A ; DO IT
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PUSH BC ;;
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LD C,(IY+PPIDE_CTL) ;;
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OUT (C),D ; ASSERT READ
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POP BC ;;
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#IF (!PPIDE8BIT)
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DEC C
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INI ; GET AND SAVE NEXT BYTE
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INC C ; LSB -> MSB
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#ENDIF
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INI ; GET AND SAVE NEXT BYTE
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LD A,E ; DEASSERT READ
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OUT (PPIDE_IO_CTL),A ; DO IT
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PUSH BC ;;
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LD C,(IY+PPIDE_CTL) ;;
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OUT (C),E ; DEASSERT READ
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POP BC ;;
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;
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JR NZ,PPIDE_GETBUF1 ; LOOP UNTIL DONE
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RET
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@@ -787,19 +814,23 @@ PPIDE_PUTBUF:
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RET NZ ; BAIL OUT IF TIMEOUT
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;
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; SETUP PPI TO WRITE
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LD C,(IY+PPIDE_PPI) ;;
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LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
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OUT (PPIDE_IO_PPI),A ; DO IT
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OUT (C),A ; DO IT
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;
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; SELECT READ/WRITE IDE REGISTER
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LD C,(IY+PPIDE_CTL) ;;
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LD A,PPIDE_REG_DATA ; DATA REGISTER
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OUT (PPIDE_IO_CTL),A ; DO IT
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OUT (C),A ;;
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LD E,A ; E := WRITE UNASSERTED
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XOR PPIDE_CTL_DIOW ; SWAP THE READ LINE BIT
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LD D,A ; D := WRITE ASSERTED
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;
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; LOOP SETUP
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LD B,0 ; 256 ITERATIONS
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LD C,PPIDE_IO_DATALO ; SETUP C WITH IO PORT (LSB)
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LD C,(IY+PPIDE_DATALO) ; SETUP C WITH IO PORT (LSB)
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;
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#IF (!PPIDE8BIT)
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INC C ; PRE-INCREMENT C
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@@ -825,10 +856,12 @@ PPIDE_PUTBUF1: ; START OF READ LOOP
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INC C
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#ENDIF
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OUTI
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LD A,D ; ASSERT WRITE
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OUT (PPIDE_IO_CTL),A ; DO IT
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LD A,E ; DEASSERT WRITE
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OUT (PPIDE_IO_CTL),A ; DO IT
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PUSH BC
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LD C,(IY+PPIDE_CTL) ; ASSERT WRITE
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OUT (C),D ; DO IT
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LD C,(IY+PPIDE_CTL) ; DEASSERT WRITE
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OUT (C),E ; DO IT
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POP BC
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;
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JR NZ,PPIDE_PUTBUF1 ; LOOP UNTIL DONE
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RET
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@@ -860,17 +893,26 @@ PPIDE_GETRES:
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;
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PPIDE_RESET:
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;
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PUSH BC
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; SETUP PPI TO READ
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LD C,(IY+PPIDE_PPI) ;;
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LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ
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OUT (PPIDE_IO_PPI),A ; DO IT
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;
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OUT (C),A ; DO IT
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; PULSE IDE RESET LINE
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LD C,(IY+PPIDE_CTL)
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LD A,PPIDE_CTL_RESET
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OUT (PPIDE_IO_CTL),A
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OUT (C),A
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;
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LD DE,20
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CALL VDELAY
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XOR A
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OUT (PPIDE_IO_CTL),A
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;
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XOR A
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OUT (C),A
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;; OUT (C),0
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;; .DB $ED,$71
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;
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LD DE,20
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CALL VDELAY
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;
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@@ -909,6 +951,7 @@ PPIDE_RESET1:
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DJNZ PPIDE_RESET1 ; LOOP AS NEEDED
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;
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POP IY ; RECOVER DEVICE CFG PTR
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POP BC
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;
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XOR A ; SIGNAL SUCCESS
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RET ; AND DONE
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@@ -973,9 +1016,13 @@ PPIDE_PROBE:
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; RETURN SOMETHING OTHER THAN ZERO. IF AN IDE CONTROLLER IS
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; THERE, THEN THE VALUE WRITTEN TO PPI PORT A IS IGNORED
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; BECAUSE THE WRITE SIGNAL IS NEVER PULSED.
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XOR A
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OUT (PPIDE_IO_DATALO),A
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; IN A,(PPIDE_REG_STAT) ; GET STATUS
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;
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LD C,(IY+PPIDE_DATALO)
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XOR A
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OUT (C),A
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;; OUT (C),0
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;; .DB $ED,$71
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;
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CALL PPIDE_IN
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.DB PPIDE_REG_STAT
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DCALL PC_SPACE
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@@ -1207,48 +1254,61 @@ PPIDE_WAITBSY2:
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;
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;
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;
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PPIDE_IN:
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PPIDE_IN: ; IY POINT TO CURRENT CFG TABLE
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PUSH BC ; SAVE INCOMING BC ; 11TS
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LD C,(IY+PPIDE_PPI) ; ; 19TS
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LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ ; 7TS
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OUT (PPIDE_IO_PPI),A ; DO IT ; 11TS
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OUT (C),A ; DO IT ; 12TS
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POP BC ; RECOVER INCOMING BC ; 10TS
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EX (SP),HL ; GET PARM POINTER ; 19TS
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;
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PUSH BC ; SAVE INCOMING BC ; 11TS
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LD B,(HL) ; GET CTL PORT VALUE ; 7TS
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LD C,PPIDE_IO_CTL ; SETUP PORT TO WRITE ; 7TS
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LD C,(IY+PPIDE_CTL) ; SETUP PORT TO WRITE ; 19TS
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OUT (C),B ; SET ADDRESS LINES ; 12TS
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SET 6,B ; TURN ON WRITE BIT ; 8TS
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OUT (C),B ; ASSERT WRITE LINE ; 12TS
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;NOP
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;NOP
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IN A,(PPIDE_IO_DATALO) ; GET DATA VALUE FROM DEVICE ; 11TS
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;NOP
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;NOP
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;NOP
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;NOP
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LD C,(IY+PPIDE_DATALO) ; ; 19TS
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IN A,(C) ; GET DATA VALUE FROM DEVICE ; 12TS
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;NOP
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;NOP
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RES 6,B ; CLEAR WRITE BIT ; 8TS
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LD C,(IY+PPIDE_CTL) ; 19TS
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OUT (C),B ; DEASSERT WRITE LINE ; 12TS
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POP BC ; RECOVER INCOMING BC ; 10TS
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INC HL ; POINT PAST PARM ; 6TS
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EX (SP),HL ; RESTORE STACK ; 19TS
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RET ; 10TS
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; ; -----
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; ; 170TS
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; ; 243TS WAS 170TS
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; ; -----
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; OUTPUT A TO
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;
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PPIDE_OUT:
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PUSH AF ; PRESERVE INCOMING VALUE
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LD A,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
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OUT (PPIDE_IO_PPI),A ; DO IT
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POP AF ; RECOVER VALUE TO WRITE
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PPIDE_OUT: ; IY POINT TO CURRENT CFG TABLE
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PUSH BC ; SAVE INCOMING BC
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LD C,(IY+PPIDE_PPI)
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LD B,PPIDE_DIR_WRITE ; SET DATA BUS DIRECTION TO WRITE
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OUT (C),B ; DO IT
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POP BC ;;
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EX (SP),HL ; GET PARM POINTER
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PUSH BC ; SAVE INCOMING BC
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LD B,(HL) ; GET IDE ADDRESS VALUE
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LD C,PPIDE_IO_CTL ; SETUP PORT TO WRITE
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LD C,(IY+PPIDE_CTL) ; SETUP PORT TO WRITE
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;
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OUT (C),B ; SET ADDRESS LINES
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SET 5,B ; TURN ON WRITE BIT
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OUT (C),B ; ASSERT WRITE LINE
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;NOP
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;NOP
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OUT (PPIDE_IO_DATALO),A ; SEND DATA VALUE TO DEVICE
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;NOP
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;NOP
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;NOP
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;NOP
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LD C,(IY+PPIDE_DATALO) ;;
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OUT (C),A ; SEND DATA VALUE TO DEVICE
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;NOP
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;NOP
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RES 5,B ; CLEAR WRITE BIT
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LD C,(IY+PPIDE_CTL)
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OUT (C),B ; DEASSERT WRITE LINE
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POP BC ; RECOVER INCOMING BC
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INC HL ; POINT PAST PARM
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@@ -1354,29 +1414,42 @@ PPIDE_PRTSTAT3:
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; PRINT ALL REGISTERS DIRECTLY FROM DEVICE
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; DEVICE MUST BE SELECTED PRIOR TO CALL
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;
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;
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; PRINT ALL REGISTERS DIRECTLY FROM DEVICE
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; DEVICE MUST BE SELECTED PRIOR TO CALL
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;
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PPIDE_REGDUMP:
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PUSH AF
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PUSH BC
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PUSH DE
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CALL PC_SPACE
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CALL PC_LBKT
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LD C,(IY+PPIDE_PPI) ;
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LD A,PPIDE_DIR_READ ; SET DATA BUS DIRECTION TO READ
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OUT (PPIDE_IO_PPI),A ; DO IT
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LD C,PPIDE_REG_CMD
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LD B,7
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OUT (C),A ; DO IT
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LD E,PPIDE_REG_CMD
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LD D,7
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PPIDE_REGDUMP1:
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LD A,C ; REGISTER ADDRESS
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OUT (PPIDE_IO_CTL),A ; SET IT
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LD A,E ; REGISTER ADDRESS
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LD C,(IY+PPIDE_CTL)
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OUT (C),A ; SET IT
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XOR PPIDE_CTL_DIOR ; SET BIT TO ASSERT READ LINE
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OUT (PPIDE_IO_CTL),A ; ASSERT READ
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IN A,(PPIDE_IO_DATALO) ; GET VALUE
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OUT (C),A ; ASSERT READ
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;
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LD C,(IY+PPIDE_DATALO)
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IN A,(C) ; GET VALUE
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CALL PRTHEXBYTE ; DISPLAY IT
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LD A,C ; RELOAD ADDRESS W/ READ UNASSERTED
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OUT (PPIDE_IO_CTL),A ; AND SET IT
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DEC C ; NEXT LOWER REGISTER
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DEC B ; DEC LOOP COUNTER
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;
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LD A,E ;
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LD C,(IY+PPIDE_CTL) ; RELOAD ADDRESS W/ READ UNASSERTED
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OUT (C),E
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;
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DEC E ; NEXT LOWER REGISTER
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DEC D ; DEC LOOP COUNTER
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CALL NZ,PC_SPACE ; FORMATTING
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JR NZ,PPIDE_REGDUMP1 ; LOOP AS NEEDED
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CALL PC_RBKT ; FORMATTING
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POP DE
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POP BC
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POP AF
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RET
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