diff --git a/Source/HBIOS/Config/RC_std.asm b/Source/HBIOS/Config/RC_std.asm
index b6b76d74..8141b71d 100644
--- a/Source/HBIOS/Config/RC_std.asm
+++ b/Source/HBIOS/Config/RC_std.asm
@@ -5,4 +5,9 @@
 ;
 #include "cfg_rc.asm"
 ;
-IDEENABLE	.SET	TRUE		; TRUE FOR IDE DEVICE SUPPORT
+CPUOSC		.SET	7372800		; CPU OSC FREQ
+DEFSERCFG	.SET	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
+;
+SIOENABLE	.SET	TRUE		; TRUE FOR ZILOG SIO/2 SUPPORT
+;
+IDEENABLE	.SET	TRUE		; TRUE FOR IDE DEVICE SUPPORT
\ No newline at end of file
diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm
index 38536f97..16af327c 100644
--- a/Source/HBIOS/ide.asm
+++ b/Source/HBIOS/ide.asm
@@ -750,7 +750,7 @@ IDE_GETRES:
 ;
 IDE_RESET:
 ;
-#IF (PLATFORM == PLT_MK4)
+#IF (IDEMODE == IDEMODE_MK4)
 	; USE HARDWARE RESET LINE
 	LD	A,$80			; HIGH BIT OF XAR IS IDE RESET
 	OUT	(MK4_XAR),A
@@ -758,7 +758,22 @@ IDE_RESET:
 	CALL	VDELAY
 	XOR	A			; CLEAR RESET BIT
 	OUT	(MK4_XAR),A
-#ELSE
+#ENDIF
+
+#IF (IDEMODE == IDEMODE_RC)
+	; RC2014 CANNOT ADDRESS THE DEVICE CONTROL PORT AND
+	; HAS NO WAY TO PERFORM A HARD RESET FROM SOFTWARE,
+	; SO FAKE IT BY SETTING THE REGISTERS TO THE SAME
+	; VALUES THAT A RESET WOULD CAUSE.
+	XOR	A
+	OUT	(IDE_IO_CYLLO),A
+	OUT	(IDE_IO_CYLHI),A
+	INC	A
+	OUT	(IDE_IO_COUNT),A
+	OUT	(IDE_IO_SECT),A
+#ENDIF
+
+#IF ((IDEMODE != IDEMODE_MK4) & (IDEMODE != IDEMODE_RC))
 	; INITIATE SOFT RESET
 	LD	A,%00001110		; NO INTERRUPTS, ASSERT RESET BOTH DRIVES
 	OUT	(IDE_IO_CTRL),A
@@ -767,9 +782,11 @@ IDE_RESET:
 	LD	DE,2			; DELAY 32US (SPEC IS >= 25US)
 	CALL	VDELAY
 ;
+#IF (IDEMODE != IDEMODE_RC)
 	; CONFIGURE OPERATION AND END SOFT RESET
 	LD	A,%00001010		; NO INTERRUPTS, DEASSERT RESET
 	OUT	(IDE_IO_CTRL),A		; PUSH TO REGISTER
+#ENDIF
 ;
 ; SPEC ALLOWS UP TO 450MS FOR DEVICES TO ASSERT THEIR PRESENCE
 ; VIA -DASP.  I ENCOUNTER PROBLEMS LATER ON IF I DON'T WAIT HERE